IET Power Electronics

Research Article

Two- and three-winding coupled-inductor- ISSN 1755-4535

Received on 29th January 2019
Revised 4th October 2019
based high step-up DC–DC converters for Accepted on 10th October 2019
E-First on 8th November 2019
sustainable energy applications doi: 10.1049/iet-pel.2019.0139
www.ietdl.org

Mahmoodreza Eskandarpour Azizkandi1, Farzad Sedaghati1 , Hossein Shayeghi1, Frede Blaabjerg2

1Department of Electrical and Computer Engineering, University of Mohaghegh Ardabili, Ardabil, Iran
2Department of Energy Technology, Aalborg University, Aalborg, Denmark
E-mail: farzad.sedaghati@uma.ac.ir

Abstract: This study proposes two configurations for a non-isolated, high step-up, single-switch, coupled-inductor-based DC–
DC converter. A coupled inductor and voltage multiplier cells are used in the presented topologies to obtain a high voltage gain.
Also, a passive clamp circuit is applied in the topologies to reduce voltage stress of the main power switch. This leads to utilising
a power switch with lower on-state resistance, which decreases the conduction loss. Several advantages such as low operating
duty cycle, high voltage conversion ratio, reduced voltage stress of semiconductors, low turn ratio of the coupled inductor,
leakage inductance energy recovery and high efficiency operation make the presented structures appropriate for sustainable
energy applications. The operational principle and steady-state analysis of the suggested topologies in continuous conduction
mode are expressed in detail. Also, design procedure and theoretical efficiency of the topologies are presented. Then, the
suggested topologies are compared with several similar high step-up topologies to prove their advantages. Finally, the
performance and feasibility of the proposed DC–DC converter configurations are confirmed through experimental measurement
results of 29 V input and 435 V/213 W and 480 V/238 W output laboratory prototypes at 50 kHz switching frequency.

1 Introduction secondary leakage inductance. The efficiency of the converter can

In recent years, renewable energy resources have drawn many
researchers’ attention because of the increasing consumption of
fossil fuels and growing environmental problems, such as air
pollution, climate change, and global warming. The renewable
energy resources such as photovoltaic and fuel cell generally need
high step-up DC–DC converters in their output section to boost and
regulate their output voltage [1]. High efficiency, high voltage gain
and low voltage stress on components are the main and basic
features of the high step-up DC–DC converters. Recently, various
DC–DC converters have been presented to boost the voltage gain
[2].
Generally, isolated converters have a high voltage conversion
ratio due to utilising transformers with large turn ratio. However,
these converters have low conversion efficiency and poor
performance because of leakage inductance [3, 4]. Moreover, when
galvanic isolation in the power grid is not needed, the traditional
boost converter becomes the first choice. However, the high
voltage stress of the power switch and diode and also, extreme duty
ratio are the basic problems of this converter at high output powers.
Switched inductor boost converters and switched capacitor boost
converters are common as well [5–7]. These converters have been
utilised widely to obtain high voltage gain. However, in switched
inductor topologies, the voltage stress across switches and diodes is
high and in the switched capacitor converters, the high current
stress on the semiconductors is the major problem.
Coupled-inductor-based high step-up DC–DC converters were
presented to resolve the above problems. This type of converter can
provide a high voltage conversion ratio with a low operating duty
ratio by using a proper turn ratio of the coupled inductor.
However, in the coupled-inductor-based converters, the
remained energy in the leakage inductance of the coupled inductor
should be recovered otherwise, this causes severe voltage spikes.
Structures such as active and passive clamps circuits have been
introduced to overcome this problem. It should be noted that in the
coupled-inductor converters with clamp circuits, the switch voltage
stress is low. Therefore, switches with low Rds(on) and low
conduction loss can be utilised. Furthermore, these converters have
low reverse recovery ringing of the output diode because of their
be increased and the voltage stress on the power switch can be
reduced due to utilising a passive clamp circuit. Moreover, it
should be considered that using a higher turn ratio to achieve a
higher voltage gain causes higher electromagnetic interference
noise and power losses. Recently, some high step-up DC–DC
converters based on two-winding coupled inductor (2WCI) are
presented in [8–17]. Moreover, several recent high step-up DC–DC
converters with three-winding coupled inductor (3WCI) have been
presented in [18–22], which leads to having more flexible
regulation on voltage stress and voltage gain. However, the
conversion ratio is still not large enough and should be raised up.
In this study, two configurations of a high step-up single-switch
DC–DC converter with 2WCI and 3WCI are introduced. The
presented converters integrate voltage multiplier cells and a
coupled inductor to achieve a high voltage gain. The coupled
inductor can be utilised to step up the static gain, and the voltage
multiplier cell proffers extra voltage gain. Also, by utilising a
coupled inductor with three winding in one of the presented
configurations, it leads to having more flexible regulation of
voltage gain and voltage stress on each semiconductor component.
A passive voltage clamp circuit is utilised in the converter to
recover the remained energy of the coupled inductor. The main
advantages of the suggested structures are achieving high voltage
conversion ratio in low duty cycles by using low turn ratio of the
coupled inductor, utilisation of only one power switch, reduced
voltage stress on the semiconductors, low conduction and
switching losses, leakage inductance energy recovery and high
efficiency. Thus, the suggested topologies are very appropriate for
sustainable energy resource applications. In the following,
operational principle and steady-state analysis of the presented
converter are provided. Also, values of voltage and current stresses
of semiconductors, voltage gain, minimum amount of magnetic
inductance, size of capacitors and theoretical efficiency of the
proposed topologies are calculated. Moreover, a comparison of the
presented configurations with several similar converters is
performed. Finally, the experimental measurement results of
implemented prototypes are presented to verify their performance.

IET Power Electron., 2020, Vol. 13 Iss. 1, pp. 144-156 144

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Fig. 1  The configuration of the proposed DC-DC converters
(a) Power circuit of proposed 2WCI DC–DC converter, (b) Equivalent circuit of the
2WCI converter, (c) Power circuit of proposed 3WCI DC-DC converter, (d)
Equivalent circuit of the 3WCI converter
2 Operation principle and steady-state analysis of
proposed configurations of the DC–DC converter
2.1 Proposed DC–DC converter with 2WCI
The power circuit of a proposed high step-up single switch 2WCI
DC–DC converter is indicated in Fig. 1a. As shown in this figure,
the presented converter consists of a power switch S, five
capacitors C1, C2, C3, C4, and C5, five diodes D1, D2, D3, D4, and
D5, one coupled inductor with two windings, output diode DO,
output filter capacitor CO, input DC voltage Vin, and output load
RO. The simplified equivalent circuit of the suggested 2WCI DC–
DC converter is indicated in Fig. 1b. According to this figure, the
2WCI is modelled as an ideal transformer with a turn ratio (N1:N2),
a leakage inductance, LLk, and a magnetising inductance, Lm. N1
and N2 are the ideal transformer primary and secondary windings
turn numbers, respectively. Thus, the coupled inductor turn's ratio
is presumed as n = N2/N1. Capacitor C1 and diode D1 act as clamp
circuit components to recycle the leakage inductor energy.
Therefore, the efficiency of the converter can be enhanced.
Capacitor C2, diodes D2 and D3, and the secondary side of the
coupled inductor are the circuit elements of the voltage multiplier
IET Power Electron., 2020, Vol. 13 Iss. 1, pp. 144-156
© The Institution of Engineering and Technology 2019
cell, which increases the voltage of clamping capacitor C1.
Moreover, the capacitor C3 is employed as a voltage lift capacitor
and also, the capacitors C4 and C5 and diodes D4 and D5 operate as
a voltage multiplier cell to increase the converter voltage gain.
In order to perform the steady-state analysis of the suggested
structure, the following assumptions are considered:
• All capacitors' size is large enough as the voltage of the
capacitors is assumed to be constant.
• All semiconductor components are considered to be ideal.
Operation principle of the presented 2WCI DC–DC converter in
continuous conduction mode (CCM) includes five time intervals.
Fig. 2 shows the current flow path of the suggested 2WCI topology
at several operating modes, and main waveforms of the converter
operation in CCM are also illustrated in Fig. 3. The five states are
described as follow:
Mode 1 [t0, t1]: In the first mode, the power switch S starts to
conduct, and diodes D3, D4, and DO are on.
According to Fig. 2a, the currents of leakage and magnetising
inductance increase linearly. Capacitor C2 is charged through the
second winding. Moreover, the magnetising inductance is charged
by the input DC voltage, and the energy of capacitors C3 and C4
are delivered to the load. This stage finishes when the current of
leakage inductance reaches the magnetising inductance current.
Mode 2 [t1, t2]: In the second mode, the power switch S is still
on and the diodes D1, D3, D4, and DO are reverse biased and the
diodes D2 and D5 are forward biased as indicated in Fig. 2b. In this
mode, the input source energy is transferred to the magnetising
inductance and the capacitor C4 is charged through the capacitor
C5. Moreover, the secondary side of the transformer charges the
capacitor C3 and the capacitor CO supplies the energy of load. This
mode finishes when the main power switch is turned off.
In this mode, the following equations can be determined for the
voltage of magnetising inductance and capacitors:
V Lm = V in (1)
V C3 − V C2 − V C1 = nV in (2)
V C1 + V C2 + V C4 − V C5 = 0 (3)
Mode 3 [t2, t3]: As shown in Fig. 2c, during this stage, switch S is
turned off, and diodes D1, D2, and D5 conduct. The current of
leakage inductor reduces linearly and flows through diode D1 and
turns it on. In this mode, capacitor C2 is charged through diode D2.
Moreover, capacitor C4 is still charged through capacitor C5. Also,
the energy of capacitor CO is transferred to the load. This time
transition finishes when the magnetising and leakage inductance
currents become equal.
Mode 4 [t3, t4]: During this mode, switch S is still in off-state,
and diodes D1, D3, D4, and DO are in on-state and diodes D2 and
D5 are blocked. In this time interval, the currents of leakage
inductance, ILk, and magnetising inductance, ILm, decrease linearly.
The stored energy in the leakage inductance is demagnetised to
capacitor C1 through diode D1. Meanwhile, the input voltage
source, Vin, and capacitors C3 and C4 charge output capacitor, CO,
and transfer energy to the load. When diode D1 is blocked at t = t4,
this time interval finishes. As shown in Fig. 2d, the following
equations can be achieved for this mode:
V Lm = V in − V C1 (4)
V O = V C5 + V C4 (5)
Mode 5 [t4, t5]: As shown in Fig. 2e, in this state, the switch S is
still off and diodes D3, D4, and DO forward biased. The leakage
and magnetising inductance currents decrease linearly, too. In this
145
mode, energies of the magnetising inductance, leakage inductance, V Lm = V in − V C5 + V C2 + V C3 (6)
and input source Vin along with capacitors C3 and C4 are delivered
to the capacitor CO and load. This time transition ends by turning The voltage of capacitor C2, V C2, is calculated as
on the main power switch again, and the next switching period
starts. Moreover, the voltage across the magnetising inductance is V C2 = nV C1 − nV in (7)
determined by using the following equation:
Furthermore, in this mode, the following equations are obtained:

ILmode 5

V Lmode 5
= k
L (8)
k (Dt4, 5)T s k

ILmode
k
5
= ILm − IN 1 (9)

According to these equations, the slope of the leakage inductance

current depends on the slope of magnetising inductance current.
Neglecting the current ripple of the magnetising inductance yields
the current slope of the leakage inductance to be zero. Thus, the
voltage across the leakage inductance is zero. According to this
equation, when the switch is turned on at the beginning of the first
mode, its current is zero. Therefore, the switch is turned on under
zero current switching conditions.
To simplify the steady-state analysis of the converter, the
coupled inductor leakage inductance, LLk, is neglected. Also,
power losses of the switching devices are not considered. In CCM
analysis, only modes 2, 4, and 5 are considered because the time
intervals of stages 1 and 3 are short significantly. Therefore, by

Fig. 2  Current flow paths of presented 2WCI converter in one switching

cycle at CCM operation
(a) Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4, (e) Mode 5 Fig. 3  Typical waveforms of suggested 2WCI converter operation in CCM

146 IET Power Electron., 2020, Vol. 13 Iss. 1, pp. 144-156

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using the inductor volt-second balance law for magnetising 2IO
ID(peak )
= ID(peak )
= (21)
inductance, the following equation is obtained: 4 O (1 − D)
DT s Ts
∫0
V in dt + ∫DT s
V in − V C1 dt = 0 (10)
As indicated in Fig. 3, the average of diodes D1 and D3 currents
can be obtained as follows:

From (8), the voltage across capacitor C1 is equal to (11) ID(peak )

Dt3, 4
⟨iD1⟩ = 1
= IO (22)
2
V in
V C1 = (11)
1−D ID(peak )
Dt4, 5
⟨iD3⟩ = 3
= IO (23)
2
where D is the power switch duty cycle.
By using (7) and (11), the voltages across capacitor C2 is
According to the charge balance principle of capacitor C3, the time
determined as follows:
transition of modes 4 and 5, Dt3, 4 and Dt4, 5, are determined as
nD
V C2 = V (12) 2(1 − D) 2(1 − D)
1 − D in Dt3, 4 = = (24)
3n + 3 3(n + 1)
According to (2), (11), and (12), the voltage across capacitor C3 is
obtained by using the following equation: 2(3n + 3)IO 6(n + 1)IO
Dt4, 5 = 1 − D − Dt3, 4 = = (25)
(3n + 1)(1 − D) (3n + 1)(1 − D)
(n + 1)
V C3 = V (13) Therefore, by using (22)–(25), the peak value of diodes current, ID1
1 − D in
and ID3, are derived as follows:
From (6) and also, by using (12) and (13), the voltage across
capacitor C5 is derived as 2IO 3(n + 1)IO
ID(peak )
= = (26)
1 Dt3, 4 (1 − D)
(2 + n + nD)
V C5 = V in (14)
1−D 2IO 6(n + 1)IO
ID(peak )
= = (27)
3 Dt4, 5 (3n + 1)(1 − D)
By substituting (9), (12), and (14) into (3), the voltage of the
capacitor C4 is expressed as follows: (peak)
Finally, the peak value of the main switch current, Iswitch, is
(n + 1) expressed as follows:
V C4 = V (15)
1 − D in
(peak) 4 − D + nD(2 + D) DV in
Iswitch2WCI = IO + (28)
From (5), (14), and (15), the voltage conversion ratio of the 2WCI D(1 − D) Lm f s
DC–DC converter in CCM, MCCM(2WCI), is achieved as
2.2 Proposed DC–DC converter with 3WCI
V O (3 + 2n + nD)
MCCM(2WCI) = = (16) The power circuit of the suggested step-up DC–DC converter with
V in (1 − D)
3WCI is illustrated in Fig. 1c. Also, the simplified equivalent
circuit of the presented structure is illustrated in Fig. 1d. By
According to a steady-state analysis, the current ripple of the
utilising 3WCI an ultra-high step-up voltage conversion ratio is
magnetising inductance of the 2WCI converter in CCM operation
provided by adjusting the turn ratio of the windings. It is found that
is determined as follows:
the connection of tertiary winding beside capacitor C4 with diodes
DV in DV inT s D4 and D5 and capacitor C5 leads to extra voltage gain compared to
ΔILm = = (17) 2WCI converter. According to Fig. 1d, the 3WCI is modelled as an
Lm f s Lm
ideal transformer with a turn ratio (N1:N2:N3), a leakage
Moreover, the average of magnetising inductance current is inductance, LLk, and a magnetising inductance, Lm. N1, N2, and N3
achieved as are the numbers of primary, secondary, and tertiary winding turn's
ratio of the ideal transformer, respectively. Therefore, the coupled
(3 + 2n + nD) inductor turn's ratio is presumed as n = N2/N1 and n3 = N3/N1. To
ILm = Iin = IO (18)
(1 − D) simplify the circuit analysis, all assumptions of the previous
section are considered.
Thus, the peak value of the magnetic inductance current is derived The operation principle of the presented 3WCI DC–DC
as follows: converter in CCM includes five time intervals. Fig. 4 shows the
current direction of the suggested configuration at several
(3 + 2n + nD) DV in operating modes, and typical waveforms of the converter operation
IL(peak )
= IO + (19) in CCM are also illustrated in Fig. 5. The five modes are explained
m (1 − D) Lm f s
as follows:
By applying the ampere-second balance law on all capacitors D1– Mode 1 [t0, t1]: In the first mode, the switch S starts to conduct,
D5 and CO, it can be proved that the average of diodes D1–D5 and and diodes D3, D4, and DO are on. According to Fig. 4a, the
DO, currents are equal to IO. Thus, as indicated in Fig. 3, the peak capacitors C2 and C5 are charged through the second winding.
values of diode currents are calculated as follows: Moreover, the magnetising inductance, Lm, is charged by the input
source and the energy of capacitors C3 and C4 are delivered to the
2IO load. The first time transition finishes when the currents iLk and iLm
ID(peak )
= ID(peak )
= (20)
2 5 D become identical.
Mode 2 [t1, t2]: During the second time transition, switch S is
still conducting and diodes D1, D3, D4, and DO are blocked and

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diodes D2 and D5 are turned on. The capacitor C4 is charged by the off, this mode ends. According to Fig. 4b, the voltage across Lm
tertiary winding of coupled inductor, and capacitors C5 and C2 are and capacitors are calculated as given in (29)–(31)
discharged through diodes D5 and D2, respectively. The load is
supplied by the output capacitor, CO. When the switch S is turned V Lm = V in (29)

nV in = V C3 − V C1 − V C2 (30)

n3V in = V C2 + V C1 − V C5 + V C4 (31)

Mode 3 [t2, t3]: As indicated in Fig. 4c, the switch S is turned off,
and diodes D1, D2, and D5 are conducting. The current of leakage
inductor, ILk, decreases linearly. Capacitor C1 is charged through
diode D1 and magnetising inductor. The load is also supplied by
the output capacitor. This time transition finishes when the
magnetising and leakage inductance currents become equal.
Mode 4 [t3, t 4]: In this stage, the switch S is off, and diodes D1,
D3, D4, and DO are forward biased and diodes D2 and D5 are
reverse biased. In this mode, the current of leakage inductance, ILk,
is less than the current of the magnetising inductor, ILm.

Fig. 4  Current flow paths of presented 3WCL converter in one switching

cycle at CCM operation
(a) Mode 1, (b) Mode 2, (c) Mode 3, (d) Mode 4, (e) Mode 5 Fig. 5  Typical waveforms of presented 3WCI converter operation in CCM

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 The leakage inductance is demagnetised to capacitor C1 through (3 + 2n + n3 + nD) DV in
IL(peak )
= IO + (42)
diode D1. The input DC voltage Vin, magnetising inductor Lm, m (1 − D) Lm f s
secondary and tertiary windings of the coupled inductor and
capacitors C3 and C4 are in series to transfer energy to the capacitor 2IO
ID(peak )
= ID(peak )
= (43)
CO and load R. This time interval finishes when the diode D1 turns 2 5 D
off. Moreover, the following equations can be obtained for this
time interval as shown in Fig. 4d 2IO
ID(peak )
= ID(peak )
= (44)
4 O (1 − D)
V Lm = V in − V C1 (32)
As illustrated in Fig. 5, the diodes D1 and D3 average current can
V O = V C4 + V C5 − n3V in + n3V C1 (33) be expressed as

Mode 5 [t4, t5]: In the latest mode, diodes D3, D4, and DO are on ID(peak )
Dt3, 4
⟨iD1⟩ = 1
= IO (45)
and the switch S is still off. The currents of leakage and 2
magnetising inductance are reduced linearly, and energies of the
magnetising and leakage inductances and input source Vin along ID(peak )
Dt4, 5
with capacitors C3 and C4 are delivered to the load. This time ⟨iD3⟩ = 3
= IO (46)
2
transition finishes by turning on the power switch S at t = t5. As
shown in Fig. 4e, the following equations are written for this mode: Based on the charge balance of capacitor C3, the time transition of
modes 4 and 5, Dt3, 4 and Dt4, 5, are achieved as follows:
V Lm = V in + V C2 + V C3 − V C5 (34)
2(1 − D)
The voltage of capacitor C2 is determined as follows: Dt3, 4 = (47)
3n + n3 + 3
V C2 = nV C1 − nV in (35) 2(3n + n3 + 3)IO
Dt4, 5 = 1 − D − Dt3, 4 = (48)
(3n + 1)(1 − D)
To simplify the converter analysis in a steady state, all assumptions
of the previous section are considered. Thus, by using the inductor Therefore, by using (47) and (48), the peak value of diodes
volt-second balance law for the Lm, the voltage across capacitor C1 currents, ID1 and ID3, are obtained as
is obtained as follows:
2IO (3n + 3 + n3)IO
V in ID(peak )
= = (49)
V C1 = (36) 1 Dt3, 4 (1 − D)
1−D
2IO 2(3n + n3 + 3)IO
where D is the switch duty cycle. ID(peak )
= = (50)
According to (35) and (36), the voltage across capacitor C2 is
3 Dt4, 5 (3n + 1)(1 − D)
derived as
(peak)
Finally, the peak value of the main switch current, Iswitch, is written
nD as follows:
V C2 = V (37)
1 − D in
(peak) 4 + n3 − D + nD(2 + D) DV in
By using (30), (36), and (37), the voltage across capacitor C3 is Iswitch(3WCI) = IO + (51)
D(1 − D) Lm f s
equal to (38)

(n + 1) 3 Design procedure of proposed converters

V C3 = V (38)
1 − D in 3.1 Voltage stress analysis

From (34) and also, by using (37) and (38), the voltage across 3.1.1 DC–DC converter with 2WCI: To choose the proper power
capacitor C5 is achieved as follows: switch and diodes for suggested 2WCI configuration, their voltage
stress must be determined. According to the 2WCI converter
operation principle, the voltage stresses of semiconductor
(2 + n + nD)
V C5 = V in (39) components are calculated as given in (52)–(56)
1−D
1 M+n
By substituting (36), (37), and (39) into (31), the voltage of V stress − S1 = V = V (52)
1 − D in M(3n + 3) O
capacitor C4 is expressed as
1 M+n
(1 + n + n3 − n3D) V stress − D1 = − V = − V (53)
V C4 = V in (40) 1 − D in M(3n + 3) O
1−D
n+1 M+n
From (36), (39), (40), and (33), the voltage gain of the 3WCI DC– V stress − D2 = − V = − V (54)
1 − D in 3M O
DC converter in CCM, MCCM(3WCI), is obtained as follows:
n n(M + n)
V O (3 + 2n + n3 + nD) V stress − D3 = − V = − V (55)
MCCM(3WCI) = = (41) 1 − D in M(3n + 3) O
V in (1 − D)
n+1 M+n
V stress − D4, 5, O = − V = − V (56)
According to Fig. 5, in terms of the steady-state analysis of the 1 − D in 3M O
3WCI converter at CCM operation and by using the ampere-second
balance law on all capacitors C1–C5 and CO, the peak current value where M is the voltage conversion ratio of the 2WCI converter in
of diodes and magnetising inductance are calculated as follows: CCM operation.

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© The Institution of Engineering and Technology 2019
3.1.2 DC–DC converter with 3WCI: According to the suggested resistance (ESR) of the primary, secondary, and tertiary side of
3WCI DC–DC converter operation principle, the voltage stresses coupled inductors, respectively. RFD1–RFD5 and RFDO are diodes
of the main power switch and diodes of the converter are obtained D1–D5 and DO forward resistances, respectively, and VFD1–VFD5
as follows: and VFDO are their threshold voltages. Also, rC1–rC5 and rCO are
ESR of capacitors C1–C5 and CO, respectively. Thus, efficiencies
1 M+n
V stress − S1 = V = V (57) of 2WCI and 3WCI converters are formulated as given in (67)–
1 − D in M(3n + 3 + n3) O
(70)
1 M+n
V stress − D1 = − V = − V (58) PO
1 − D in M(3n + 3 + n3) O η2WCI = × 100 (67)
PO + Ploss2WCI
n+1 (M + n)(n + 1)
V stress − D2, 4 = − V = − V (59) PO
1 − D in (3 + 3n + n3)M O η3WCI = × 100 (68)
PO + Ploss3WCI
n n(M + n)
V stress − D3 = − V = − V (60)
1 − D in M(3n + 3 + n3) O Ploss2WCI = A1 + A2 + A3 + A4 + A5 + A6 (69)

n + n3 + 1 (M + n)(n + n3 + 1) Ploss3WCI = A1∗ + A2∗ + A3∗ + A4∗ + A5∗ + A6∗ + A7 (70)

V stress − D5, O = − V in = − V O (61)
1−D (3 + 3n + n3)M
where A1 and A1∗ are conduction losses of switches in 2WCI and
The same as the previous section, M is the voltage conversion ratio
of the 3WCI converter in CCM operation. 3WCI configurations, respectively, and equal to
As the voltage stress analysis show, the main merits of the
presented 2WCI and 3WCI configurations of the DC-DC converter A1 = rDS − on × (Irms, S(2WCI))2
is that the voltage stress across the semiconductors is lower than DV in 2 2 (71)
4 − D + nD(2 + D)
the output voltage. = rDS − on × D IO +
D(1 − D) Lm f s
3.2 Magnetising inductance design
A1∗ = rDS − on × (Irms, S(3WCI))2
In order to guarantee the operation of the presented converters in 2 2
CCM, the average current through the magnetic inductance, Lm, 4 + n3 − D + nD(2 + D) DV in (72)
= rDS − on × D IO +
should be higher than half of the current ripple of the inductor. The D(1 − D) Lm f s
continuity of the magnetising current is also considered in the
design of the magnetising inductance. Therefore, by using (18) and A2 and A2∗ are switching losses of the 2WCI and 3WCI
(19), the minimum value of the magnetising inductance for the configurations, respectively, and can be derived as follows:
2WCI converter is obtained as follows:
2
M2WCI + n
D(1 − D)V inRO A2 = f SCSV S2 (2WCI) = f SCS V (73)
Lm ≥ (62) M2WCI(3n + 3) O
2 f s(3 + 2n + nD)V O
2
M3WCI + n
Also, according to (42), the minimum value of magnetising A2∗ = f SCSV S2 (3WCI) = f SCS V (74)
inductance for the 3WCI converter is determined using the M3WCI(3n + 3 + n3) O
following equation:
A3 and A3∗ are the diodes forward resistance losses of the 2WCI and
D(1 − D)V inRO 3WCI configurations, respectively, and can be calculated as given
Lm ≥ (63)
2 f s(3 + 2n + n3 + nD)V O in (75) and (76)
2
3.3 Capacitors design 2
3 Dt3, 4 n + 1 IO
A3 = RFD1 − 5, O × Irms, D1 − 5, O = RFD1
1−D
All capacitors are designed by assuming the same voltage ripple
2
for the presented converters. According to (11)–(15) and (36)–(40), 2IO 2 6 Dt3, 4 n + 1 IO
voltages of capacitors C1–C5 for both 2WCI and 3WCI +(RFD2 + RFD5) + RFD3 (75)
D 3n + 1 1 − D
configurations are achieved. Since the charge absorbed or produced 2
by all the capacitors are equal, the sizes of the capacitors are 2IO
+(RFD4 + RFDO)
derived as given in (64)–(66) 1−D

DIO Dt3, 4 3n + n3 + 1 IO
2
ΔQ = v (64) 2
fS A3∗ = RFD1 − 5, O Irms, D1 − 5, O = RFD1
1−D
2
ΔQ 2IO
ΔV C = (65) +(RFD2 + RFD5)
C D
2
(76)
DIO 2 Dt3, 4 3n + n3 + 1 IO
Ci = (66) +RFD3
ΔV Ci f S 3n + 1 1 − D
2
2IO
where i = 1, 2, 3, 4 and 5. +(RFD4 + RFDO)
1−D

4 Efficiency analysis of proposed converters A4 and A4∗ are the diodes forward voltage losses of the 2WCI and
In efficiency analysis of the presented converters, parasitic 3WCI configurations, and can be determined as
resistances are considered and defined as follows: rDS-onis switch
on-state resistance, RLN1, RLN2, and RLN3 are equivalent series

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Table 1 Comparison of presented DC–DC converters with several similar topologies
Number of components Voltage gain Voltage stress on the main switch
Diode Cap Switch Core
reference proposed 2WCI converter 6 6 1 1 3 + 2n + nD M+n
V
(1 − D) M(3n + 3) O
proposed 3WCI converter 6 6 1 1 (three-winding) 3 + 2n + n3 + nD M+n
V
(1 − D) M(3n + n3 + 3) O
converter in [19] 5 5 1 1 (three-winding) 4 + n(1 − D) + 3n3(1 − D) − 2D M − n − 3n3 − 2
VO
(1 − D) 2M
converter in [18] 6 6 1 1 (three-winding) 2 + n + 2n3 − n3D M − n3
V
(1 − D) M(n3 + n + 2) O
converter in [22] 8 7 2 2 (three-winding) 3n + 1 1
V
(1 − D) (3n + 1) O
converter in [20] 4 4 1 1 (three-winding) 2 + n + n3 − D(n + 1) M−n−1
V
(1 − D) M(n3 + 1) O
converter in [14] 5 5 1 1 2 + 3n − nD M−n
V
(1 − D) M(2n + 2) O
converter in [16] 6 6 1 1 1 + 2n + nD M+n
V
(1 − D) M(3n + 1) O
converter in [15] 6 6 1 1 1 + 2n + nD M+n
V
(1 − D) M(3n + 1) O
converter in [17] 6 6 1 1 2 + 2n + nD M+n
V
(1 − D) M(3n + 2) O

A4 = A4∗ = V FD1 − 5, O × ID1 − 5, O(ave)

(77)
= IO(V FD1 + V FD2 + V FD3 + V FD4 + V FD5 + V FDO)

A5 and A5∗ are the power losses of capacitors of the 2WCI and
3WCI configurations, respectively, which are equal to
2
A5 = rC1, 2, 3, 4, 5, O × (Irms , C 1, 2, 3, 4, 5, O)2WCI (78)

A5∗ = rC1, 2, 3, 4, 5, O × (Irms

2
, C 1, 2, 3, 4, 5, O)3WCI (79)

A6 and A6∗ are the conduction losses of the primary and secondary
sides of a coupled inductor in the 2WCI and 3WCI configurations,
which can be formulated as follows:
2 2
A6 = RLN1(Irms , LN1) + RLN2(Irms, LN2) (80)

A6∗ = RLN1(Irms
2 2
, LN1) + RLN2(Irms, LN2) (81)

Finally, A7is the conduction loss of the tertiary side of the coupled
inductor in 3WCL converter that is equal to
2
A7 = RLN3(Irms , LN3) (82)

5 Comparison study
In order to clarify the merits of presented configurations, some
comparisons are discussed in this section. Some features of the
suggested converters and similar structures presented in [14–20,
22] are indicated in Table 1. As shown in this table, considering the
voltage gain, the components’ number of both suggested 2WCI and
3WCI converters is equal to the converters presented in [15–18],
however, the voltage conversion ratio of the presented topologies is
higher than the other topologies. Moreover, it is worth noting that Fig. 6  Comparison results of proposed topologies with some similar step-
the voltage conversion ratio of converter presented in [22] is lower up structures
than both proposed converters with a more number of power (a) Voltage gain of several structures for different duty cycles, (b) Normalised voltage
components. Although, the components’ number of the converters stress of main power switch against voltage gain in several topologies (for n = 2 and
presented in [14, 19, 20] is lower than the proposed converters. n3 = 1)
However, their voltage gain is lower than both presented
configurations. According to Table 1, it is obvious that the 3WCI Fig. 6a shows voltage gain comparison results of suggested
configuration has higher voltage gain than the 2WCI configuration, configurations and topologies presented in [14–20] for various duty
and their only structural difference is that the 3WCI converter has a cycles with n = 2 and n3 = 1. According to this figure, the voltage
3WCI. It should be noted that the converters proposed in [18–20] gain of both proposed configurations is greater than the others for
have 3WCI. With consideration of n3 = 1, these converters have all ranges of duty cycles. This advantage is due to the integration of
lower voltage gain than the 2WCI converter. a coupled inductor with voltage multiplier cells in the suggested

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© The Institution of Engineering and Technology 2019
 ^
configurations. As indicated in Fig. 6b, the normalised voltage u^ = V in , y^ = V O (90)
stress across the main switch in the both presented topologies is
less than the other topologies for any value of the duty cycle.
The matrixes related to (83) and (84) are given as follows:
Thus, a power switch with low RDS(on) resistance can be used in
(see (91))
the presented converters to decrease the cost and enhance the
overall efficiency. According to this section, both proposed 1
converters have a high voltage conversion ratio with less voltage Lm
stress on the switch which makes them appropriate for sustainable
energy applications. 0
0
6 Dynamic analysis of the proposed converters B = 0 , C = 1 0 0 0 0 0 0 0 (92)
In order to obtain the transfer functions, the state space average 0
method is applied. The equations of state variables and output 0
variables are presented as functions of the state, input, and control
0
variables, which are obtained using Kirchhoff's voltage and current
laws. The state equations and output variables are given in state 0
space form as follows:
The dynamic performance of the presented converters can be
˙
x^ i(t) = A x^ i(t) + B u^ i(t) analysed using the small-signal frequency response. In this section,
(83)
the values of elements are selected as Lm = 100 μH, C1 = C2 = C3 = 
C4 = C5 = 47 µF, Co = 220 µF, D = 0.5, n2 = 2, n3 = 1. The
y^ i(t) = C x^ i(t) + D u^ i(t) (84)
simulation results of control to output transfer function in the
frequency domain (the magnitude dB and phase frequency
The state variables and input variables vectors of 2WCI converter response) of both proposed converters are shown in Fig. 7.
are specified as follows: A control block diagram of the proposed converter is shown in
^ ^ ^ ^ ^ ^ ^ ^ T
Fig. 8. To control the output voltage, a proportional–integral (PI)
x^ = I LN1, I LN2, V C1, V C2, V C3, V C4, V C5, V CO (85) controller is utilised. In Fig. 8, the output voltage is compared with
the appropriate value of the output voltage when there is a
u^ = V in , y^ = V O
^ difference between Vout and Vref, it is applied to the controller to
(86)
produce an appropriate duty cycle. The proper interpolated is
produced by comparing the appropriate duty cycle with a carrier
The matrixes related to (83) and (84) are given as follows: wave. It has to be mentioned that the PI controller includes a gain
(see (87)) and time constant and that their values are obtained using a trade-
off.
1
Lm
7 Experimental measurement results
0
In order to confirm the performance and feasibility of presented
0
configurations of DC–DC converter, their laboratory prototypes are
B = 0 , C = 1 0 0 0 0 0 0 0 (88) designed and implemented. The photo of the experimental set and
0 implemented power circuit is shown in Fig. 9.
0 In all of the figures, the time per division is set to be 8 µs. The
specifications of the implemented 2WCI configuration are given as
0 follows:
0 Output power: 213 W; input voltage: 29 V; output voltage: 435 
V; power switch S: IRFP260n; D1–D5 and DO: MUR1560; C1–C5:
Moreover, the state variables and input variables’ vectors of the 47 μF/250 V; CO: 220 μF/450 V; Cin: 470 μF/63 V; Lm: 100 μH
3WCI converter are specified as follows: and Lk: 8 μH; N1 : N2 = 1 : 2; core: EE55; switching frequency: 50 
^ ^ ^ ^ ^ ^ ^ ^ ^ kHz; duty cycle: 0.5.
x^ = I LN1, I LN2, I LN3, V C1, V C2, V C3, V C4, V C5, V CO (89) Experimental measurement results of the 2WCI converter
operation in CCM are given in Figs. 10 and 11. Input and output

1−D
0 − 0 0 0 0 0 0
Lm
D 1 1−D
0 0 0 − 0 − 0
LN2 LN2 LN2
D 2(1 − D)
− 0 0 0 0 0 0
C1 C2
1−D 1+D
− 0 0 0 0 0 0
C2 C2
A = (87)
2(1 − D) D
− − 0 0 0 0 0 0
C3 C3
(2C1 + C2)D (1 − D)
0 − 0 0 0 0 0
C2C4 CO
1−D (2C1 + C2)D (1 − D)
0 0 0 0 0
C3 C2C4 CO
1
0 0 0 0 0 0 0 −
ROCO
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 Fig. 8  Control scheme of the proposed converters

Fig. 7  Frequency response of the proposed converters for phase and gain
margins
(a) 2WCI converter, (b) 3WCI converter
voltage waveforms are illustrated in Fig. 10a(left). The input and
output voltages are equal to 29 and 435 V, respectively. Also, as
shown in this figure, the ripple of the output voltage is very low.
The voltage and current of power switch S are indicated in
Figs. 10a(centre) and 8a(right), respectively. It is obvious that the
maximum voltage on the main power switch is about 60 V.
Therefore, a switch with low RDS(on) resistant can be utilised.
According to Fig. 10a(centre), the duty ratio of the main switch is
close to 0.5. The coupled inductor leakage current is indicated in
Fig. 10b(left). The resultant waveform is similar to Fig. 3, which
confirms the theoretical analysis.
As shown in Fig. 10b(left), due to the series connection of the
primary side of the coupled inductor with input source, the input
current ripple of the proposed converter is discontinuous and
pulsating. In order to solve this problem, an input capacitor is
needed to make input current continuous and decrease its ripple. In
Fig. 9  The photograph of the implemented converter experimental set and
power circuit
(a) Overall system of the experimental setup, (b) Implemented power circuit
Fig. 10a(centre), the measured input current ripple waveform
(Isource) of the converter is presented. As depicted in this figure
(Isource), an input capacitor (Cin) is utilised to decrease the input
current ripple and make it appropriate for renewable energy
applications.
Figs. 10b(centre and right) and c(left and centre) represent the
voltage waveforms across diodes. The measured voltage across the
diodes D1, D3, D4, and DO are found to be about 60, 102, 158, and
157 V, respectively. It is obvious that the diodes voltage stresses
are far lower than the output voltage; hence, the ultrafast diodes are
employed to completely eliminate the reverse recovery current.
The capacitors C1–C5 voltage waveforms are shown in

1−D
0 0 0 − 0 0 0 0 0
Lm
1 − 2D D 1 1−D
0 0 0 − 0 − 0
LN2 LN2 LN2 LN2
1 1 1 1
0 0 0 0 − 0
LN3 LN3 LN3 LN3
1−D D D
− − 0 0 0 0 0 0
C1 C1 C1
1−D D D
A = − − 0 0 0 0 0 0 (91)
C1 C1 C1
1−D D D
− − 0 0 0 0 0 0
C2 C2 C1
1 − 2D
0 0 0 0 0 0 0 0
C4
1−D D
0 − 0 0 0 0 0 0
C3 C5
1
0 0 0 0 0 0 0 0 −
ROCO
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Fig. 10  Experimental measurement results of 2WCI converter
(a) Input and output voltages (left), voltage of switch S and Isource (centre), and current of switch S (right), (b) Leakage current of coupled inductor (left), voltage of diode D1
(centre), and voltage of diode D3 (right), (c) Voltage of diode D4 (left), voltage of diode DO (centre), and voltage of capacitors C1 and C3 (right), (d) Voltage of capacitors C2 and
C4 (left), voltage of capacitor C5 (centre), and current of diode D1 (right)

Fig. 11  Experimental measurement results of 2WCI converter: current of diode D3 (left), current of diode D5 (centre), and current of diode DO (right)

Figs. 10c(left) and d(left and right) which are in consistency with
(9)–(13). The current of diodes D1, D3, D5, and DOare depicted in
Figs. 10d(left) and 11. The obtained waveforms confirm theoretical
waveforms, given in Fig. 3.
Experimental results of the 3WCI configuration are shown in
Figs. 12 and 13. The specifications of the implemented 3WCI
configuration are given as follows:
Output power: 238 W; input voltage: 29 V; output voltage: 480  respectively. It is clear that the maximum voltage on the power
V; power switch S: IRFP260n; D1–D5 and DO: MUR1560; C1–C5:
47 μF/250 V; CO: 220 μF/450 V; Cin: 470 μF/63 V; Lm: 100 μH
and Lk: 8 μH; N1:N2:N3 = 1:2:1; core: EE55; switching frequency:
50 kHz; duty cycle: 0.5.
Input and output voltage waveforms are indicated in
Fig. 12a(left). The input and output voltages are equal to 29 and
480 V, respectively. Also, as shown in this figure, the ripple of the
output voltage is very low. The voltage and current of power
switch S are indicated in Figs. 12a(centre) and a(right),
switch is very lower than the output voltage. Thus, a switch with
low RDS(on) resistance can be used. According to Fig. 12a(centre),
the duty ratio of the main switch is close to 0.5. The coupled

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Fig. 12  Experimental measurement results of 3WCI converter
(a) Input and output voltages (left), voltage of switch S and Isource (centre), and current of switch S (right), (b) Leakage current of coupled inductor (left), voltage of diode D1
(centre), and voltage of diode D2 (right), (c) Voltage of diode D3 (left), voltage of diode D5 (center), and voltage of capacitors C1 and C4 (right), (d) Voltage of capacitors C3 and C5
(left), voltage of capacitor C2 (centre), and current of diode D1 (right)

Fig. 13  Experimental measurement results of 3WCI converter: current of diode D2 (left), current of diode D4 (centre), and current of diode DO (right)

inductor leakage current is indicated in Fig. 12b(left). The resultant
waveform is similar to Fig. 5, which confirms the theoretical
analysis. Moreover, the declined input current ripple waveform of
the 3WCI converter is presented in Fig. 12a(centre). As it is
depicted in this figure (ISource), an input capacitor (Cin) can be
utilised to decline the input current ripple and make it suitable for
renewable energy applications.
Figs. 12b(centre and right) and c(left and centre) represent the
voltage waveforms across diodes. It is obvious that the diodes
voltage stresses are far lower than the output voltage; hence, the
ultrafast diodes are employed to entirely rectify the reverse
recovery current. The capacitors C1–C5 voltage waveforms are
shown in Figs. 12c(left) and d(left and right) which are in a good
agreement with (34)–(38). The current of diodes D1, D2, D4 and
DO are illustrated in Figs. 12d(left) and 13. The obtained
waveforms confirm theoretical waveforms, given in Fig. 5.
According to experimental results, in the same condition (D = 0.5,
n = 2, n3 = 1 and output power approximately equal to 220 W) the
2WCI and 3WCI configurations convert 29 V input voltage to 435
and 480 V output voltage, respectively.
Fig. 14 shows measured efficiencies of the suggested 2WCI and
3WCI configurations under several output powers for Vin = 29 V,

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© The Institution of Engineering and Technology 2019

Fig. 14  Measured efficiencies of presented 2WCI and 3WCI converters
Fig. 15  Pie graph of components loss breakdown at 238 W (Vin = 29 V, D  voltage multiplier cell’, IEEE Trans. Power Electron., 2019, Early Access,
= 0.5, fs = 50 kHz, Cs = 600 pF, VFD = 1.2 V)
(a) Proposed 2WCI converter, (b) Proposed 3WCI converter
D = 0.5, fs = 50 kHz, n = 2, and n3 = 1. The maximum efficiency of
the 2WCI and 3WCI configurations under the output power of 102
and 107 W are equal to 93.7 and 94.7%, respectively, and the
measured efficiency of the 2WCI and 3WCI for the output power
of 213 and 238 W are equal to 93.1 and 92.6%, respectively.
According to the calculated efficiencies for the proposed converters
in Section 4, the power losses can be determined for the presented
converters as indicated in Fig. 15. It is obvious that dominant
power losses in the suggested structures are diodes total losses that
can be further improved to enhance the conversion efficiency.
Finally, according to the experimental measurement results, the
feasibility and performance of the suggested topologies are
confirmed. Several features of the proposed converters such as
high voltage gain without an extra duty cycle with a low turn ratio
of a coupled inductor, low voltage stress across main switch and
diodes, leakage inductance energy recovery and high efficiency
make it appropriate for renewable energy applications.
8 Conclusions
In this study, two configurations based on the coupled inductor
with two or three windings for a non-isolated, high step up, single
switch DC–DC converter was proposed. In the presented
configurations, high voltage gain is achieved by utilising a 2WCI
or 3WCI and voltage multiplier cells. The voltage conversion ratio
of the presented converters is increased by raising the coupled
inductor turn's ratio. The voltage stress on the main switch is low
and so, a power switch with low on-state resistance can be selected.
The converters’ operation and steady-state analysis in CCM were
discussed in detail. Moreover, the design procedure and theoretical
efficiency of the suggested topologies were calculated. Then, the
presented converters are compared with several similar converters
156
where the comparison results show that the proposed converter
voltage conversion ratio is higher and voltage stress of the power
switch is lower than the other topologies.
Finally, to demonstrate the performance of the presented
converters, experimental measurement results were presented.
9 References
[1] Forouzesh, M., Shen, Y., Yari, K., et al.: ‘High-efficiency high step-up DC–
DC converter with dual coupled inductors for grid-connected photovoltaic
systems’, IEEE Trans. Power Electron., 2018, 33, (7), pp. 5967–5982
[2] Forouzesh, M., Siwakoti, Y.P., Gorji, S.A., et al.: ‘Step-up DC–DC
converters: a comprehensive review of voltage-boosting techniques,
topologies, and applications’, IEEE Trans. Power Electron., 2017, 32, (12),
pp. 9143–9178
[3] Sedaghati, F., Hosseini, S.H., Sabahi, M., et al.: ‘Extended configuration of
dual active bridge DC–DC converter with reduced number of switches’, IET
Power Electron., 2015, 8, (3), pp. 401–416
[4] Sedaghati, F., Hosseini, S.H., Sabahi, M., et al.: ‘Analysis and implementation
of a modular isolated zero-voltage switching bidirectional DC–DC converter’,
IET Power Electron., 2014, 7, (8), pp. 2035–2049
[5] Moradpour, R., Ardi, H., Tavakoli, A.: ‘Design and implementation of a new
SEPIC-based high step-up DC/DC converter for renewable energy
applications’, IEEE Trans. Ind. Electron., 2018, 65, (2), pp. 1290–1297
[6] Sedaghati, F., Eskandarpour Azizkandi, M., Latifi, S.H., et al.: ‘A high-
efficiency non-isolated high-gain interleaved DC–DC converter with reduced
voltage stress on devices’. 10th Int. Power Electronics, Drive Systems
Technologies Conf. (PEDSTC), Shiraz, Iran, 2019, pp. 729–734
[7] Hsieh, Y.P., Chen, J.F., Liang, T.J., et al.: ‘Novel high step-up DC–DC
converter for distributed generation system’, IEEE Trans. Ind. Electron.,
2013, 60, (4), pp. 1473–1482
[8] Farakhor, A., Abapour, M., Sabahi, M.: ‘Study on the derivation of the
continuous input current high-voltage gain DC/DC converters’, IET Power
Electron., 2018, 11, (10), pp. 1652–1660
[9] Eskandarpour Azizkandi, M., Sedaghati, F., Shayeghi, H., et al.: ‘A high
voltage gain DC–DC converter based on three winding coupled inductor and
doi: 10.1109/TPEL.2019.2944518
[10] Ajami, A., Ardi, H., Farakhor, A.: ‘A novel high step-up DC–DC converter
based on integrating coupled inductor and switched-capacitor techniques for
renewable energy applications’, IEEE Trans. Power Electron., 2015, 30, (8),
pp. 4255–4263
[11] Pourjafar, S., Sedaghati, F., Shayeghi, H., et al.: ‘A new high step-up DC–DC
converter with coupled inductor and voltage lift circuit combination suitable
for renewable applications’, IET Power Electron., 2019, 12, (1), pp. 92–101
[12] Babaei, E., Saadatizadeh, Z.: ‘High voltage gain DC–DC converters based on
coupled inductors’, IET Power Electron., 2018, 11, (3), pp. 434–452
[13] Eskandarpour Azizkandi, M., Sedaghati, F., Shayeghi, H.: ‘Design and
analysis of a high step-up single-switch coupled inductor DC–DC converter
with low-voltage stress on components for PV power application’, Int. J.
Circuit Theory Appl., 2019, 47, (7), pp. 1121–1151
[14] Chen, Y.T., Lu, Z.X., Liang, R.H., et al.: ‘Analysis and implementation of a
novel high step-up DC–DC converter with low switch voltage stress and
reduced diode voltage stress’, IET Power Electron., 2016, 9, (9), pp. 2003–
2012
[15] Hsieh, Y.P., Chen, J.F., Liang, T.J.P., et al.: ‘Novel high step-up DC–DC
converter with coupled-inductor and switched-capacitor techniques for a
sustainable energy system’, IEEE Trans. Power Electron., 2011, 26, (12), pp.
3481–3490
[16] Hsieh, Y.P., Chen, J.F., Liang, T.J., et al.: ‘Novel high step-up DC–DC
converter with coupled-inductor and switched-capacitor techniques’, IEEE
Trans. Ind. Electron., 2012, 59, 2, pp. 998–1007
[17] Honarjoo, B., Madani, S.M., Niroomand, M., et al.: ‘Analysis and
implementation of a new single switch, high voltage gain DC–DC converter
with a wide CCM operation range and reduced components voltage stress’, J.
Power Electron., 2018, 18, (1), pp. 11–22
[18] Khalilzadeh, M., Abbaszadeh, K.: ‘Non-isolated high step-up DC–DC
converter based on coupled inductor with reduced voltage stress’, IET Power
Electron., 2015, 8, (11), pp. 1755–4535
[19] Hu, X., Wang, J., Li, L., et al.: ‘A three-winding coupled-inductor DC–DC
converter topology with high voltage gain and reduced switch stress’, IEEE
Trans. Power Electron., 2018, 33, (2), pp. 1453–1462
[20] Tseng, K.-C., Lin, J.-T., Huang, C.-C.: ‘High step-up converter with three-
winding coupled inductor for fuel cell energy source applications’, IEEE
Trans. Power Electron., 2015, 30, (2), pp. 574–581
[21] Li, F., Liu, H.: ‘A cascaded coupled inductor-reverse high step-up converter
integrating three-winding coupled inductor and diode–capacitor technique’,
IEEE Trans. Ind. Inf., 2017, 13, (3), pp. 1121–1130
[22] Nouri, T., Hosseini, S.H., Babaei, E., et al.: ‘Interleaved high step-up DC–DC
converter based on three-winding high-frequency coupled inductor and
voltage multiplier cell’, IET Power Electron., 2015, 8, (2), pp. 175–189
IET Power Electron., 2020, Vol. 13 Iss. 1, pp. 144-156
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