Microprocessor & Microcontroller (Module - 3)

Mr. Kaushik Neogi

DEPT. OF EE, ASANSOL ENGINEERING COLLEGE
Paper Code: PC-EE-602

Lecture 1
Contents: 2

 Interfacing
 Memory Interfacing
 References
Interface:
3

An interface is a medium through which two separate components of a compute system

exchange information or interact with each other. The exchange can be between software,
computer hardware, peripheral devices, humans and combinations of these.
1. Memory Interfacing
2. I/O Interfacing
Memory Interfacing:
4
 Memory is made up of registers.
 Each register in the memory is one storage location.
 Each location is identified by an address.
 Each register consists of storage elements (flip flops) and element stores one bit of data.
 A storage element is called cell.
 The data stored in a memory by a process is called writing and are retrieved from the
memory by a process is called reading.
Memory Interfacing:
5
 Memory structure and its requirements
 The read / write memories consist of an array of registers in which each register has unique
address.
 The size of memory is N * M as shown in figures. Where N is number of register and M is
the word length, in number of bits.
Memory Interfacing:
6
As shown in Figure below memory chip has 11 address lines A0 – A10, one chip select (CS), and
two control lines, Read (RD) to enable output buffer and Write (WR) to enable the input buffer.
The internal decoder is used to decoder the address lines.
Memory Interfacing:
7
Below Figure shows the logic diagram of a typical EPROM (Erasable Programmable Read-Only
Memory) with 4096 (4K) register. It has 12 address lines A0 – A11, one chip select (CS), one read
control signal.
Since EPROM does not require the (WR) signal. EPROM (or EPROMs) is used as a program
memory and RAM (or RAMs) as a data memory.
Memory Interfacing:
8
The following table summarize the memory capacity and address lines required for memory
interfacing.
74LS138 (Decoder / Demultiplexer):
9
A decoder is a logic circuit that accepts a set of inputs that represents a binary number and
activates only the output that corresponds to the input number.
In other words, a decoder circuit looks at its inputs, determines which binary number is
present there, and activates the one output that corresponds to that number ; all other
outputs remain inactive.
74LS138 (Decoder / Demultiplexer):
10
In its general form, a decoder has N input lines to handle N bits and form one to 2N output
lines to indicate the presence of one or more N-bit combinations. The following figure shows
the block diagram of Decoder.
74LS138 (Decoder / Demultiplexer):
11
The 74LS138 is a high speed 1-of-8 Decoder (3 to 8 decoder). It could also be called a binary-
octal decoder or converters because it takes a three bit binary input code and activates the one
of the eight outputs corresponding to that code.
It is also referred to as a 1-of-8 decoder, because only 1 of the 8 outputs is activated at one time.
The pin diagram and the truth table of decoder is shown in the below figures.
Memory Interfacing:
12
Basic concepts in Memory Interfacing
8085 access 64 Kbytes memory since its address bus is 16-bit. It’s not compulsory to use full 64
Kbytes address space. The total memory depends upon the applications.
Usually EPROM is used as a program memory and RAM used as a data memory.
Number of EPROM and RAM is depends on requirement of applications.
Microprocessor can communicate (read / write) with only one device at a time. Since the data,
address and control buses are common for all the devices. Decoding is necessary to
communicate with devices (Memory / I/O). The common address decoding techniques are:
 Absolute decoding
 Linear decoding
Memory Interfacing:
13
Absolute Decoding:
In the absolute decoding technique the memory chip is selected only for the specified logic level
on the address lines: no other logic levels can select the chip. Figure shows the memory
interface with absolute decoding. Two 8K EPROMs (2764) are used to provide even and odd
memory banks.
Control signals BHE and A0 are use to enable output of odd and even memory banks
respectively. As each memory chip has 8K memory locations, thirteen address lines are
required to address each locations, independently. All remaining address lines are used to
generate an unique chip select signal. This address technique is normally used in large memory
systems.
Absolute Decoding:
14
Memory Interfacing:
15
Linear Decoding:
In small system hardware for the decoding logic can be eliminated by using only required
number of addressing lines (not all). Other lines are simple ignored. This technique is
referred as linear decoding or partial decoding.
Figure shows the addressing of 16K RAM (6264) with linear decoding. Control signals BHE
and A0 are used to enable odd and even memory banks, respectively. The address line A19 is
used to select the RAM chips. When A19 is low, chip is selected, otherwise it is disabled. The
status of A14 to A18 does not affect the chip selection logic. This gives you multiple addresses.
This technique reduces the cost of Address Decoding Techniques in 8086 Microprocessor
circuit, but it has drawback of multiple addresses.
Linear Decoding:
16
References: 17

1. Advanced Microprocessors and Peripheral, Koshor M Bhurchandi, Ajay Kumar

Ray, 3rd Edition, MC Graw hill education.
2. Microprocessor & Interfacing, D.V. Hall, Mc Graw Hill.
3. Microprocessor & Peripherals, S.P. Chowdhury & S. Chowdhury, Scitech.
4. The 8086 Microprocessors: Programming & Interfacing the PC, K.J.Ayala,
Thomson.