Chapter 6 Counters

Counter
Counting events or periods of time
Putting events into sequence
Dividing frequency

6.1 Ripple Counters

Counting sequence for an electric counter
BINARY COUNTING
DECIMAL
D C B A
COUNTING
8s 4s 2s 1s
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Fig. 6-1

Modulo (mod)-16 counter [4-bit ripple counter]

A counter to count from binary 0000 to 1111
Device that has 16 different output states

The modulus of a counter

The number of different states the counter must go through to complete its counting cycle

- 1-
Logic diagram of a mod-16 counter

1 𝐽 𝑄 1 𝐽 𝑄 1 𝐽 𝑄 1 𝐽 𝑄 D C B A
Clock pulses
1 FF1 FF2 FF3 FF4
2 1 0 𝐶𝐿𝐾 𝐶𝐿𝐾 𝐶𝐿𝐾 𝐶𝐿𝐾 BINARY
0
INPUT OUTPUT
1 𝐾 1 𝐾 1 𝐾 1 𝐾
𝐶𝐿𝑅 𝐶𝐿𝑅 𝐶𝐿𝑅 𝐶𝐿𝑅

Fig. 6-2

Waveform diagram of a mod-16 counter

1
INPUT CLK 0 1 2 3 4 5 6 7 8 9
0

FF1 𝑄 A

FF2 𝑄 B
OUTPUTS
FF3 𝑄 C

FF4 𝑄 D

Binary count 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010

Fig. 6-3

The changing of states is a chain reaction that ripples through the counter.

Ripple Counter

6.2 Mod-10 Ripple Counters

Mod-10 ripple counter [Decade (meaning 10) counter]
A counter to count from binary 0000 to 1001 (0 to 9 in decimal)
Device that has 10 different output states

- 2-
Logic diagram of a mod-10 counter (PS=1)

1 𝐽 𝑄 1 𝐽 𝑄 1 𝐽 𝑄 1 𝐽 𝑄 D C B A
Clock pulses
1 FF1 FF2 FF3 FF4
2 1 0 𝐶𝐿𝐾 𝐶𝐿𝐾 𝐶𝐿𝐾 𝐶𝐿𝐾 BINARY
0
INPUT OUTPUT
1 𝐾 1 𝐾 1 𝐾 1 𝐾
𝐶𝐿𝑅 𝐶𝐿𝑅 𝐶𝐿𝑅 𝐶𝐿𝑅

Added reset circuit B

Fig. 6-4

A NAND gate is added to the ripple counter to clear all the flip-flops back to zero
immediately after the 1001 (9) count.

The two 1s in the 1010 are fed into a NAND gate.

The NAND gate clears the flip-flop back to 0000. [Asynchronous reset]

The counter starts its count from 0000 up to 1001 again.

6.3 Synchronous Counters

Asynchronous counter
A counter that does not trigger each flip-flop exactly in step with the clock pulse
The ripple counters

Synchronous counter
A counter that triggers all the flip-flops at the same instant

- 3-
Logic diagram for a 3-bit synchronous counter (PS=1, CLR=1)

1 𝐽 𝑄 𝐽 𝑄 𝐽 𝑄 C B A
FF1 FF2 FF3
𝐶𝐿𝐾 𝐶𝐿𝐾 𝐶𝐿𝐾 BINARY
OUTPUT
Clock pulses 𝐾 𝐾 𝐾
1
0
INPUT
Fig. 6-5

Waveform diagram of a 3-bit synchronous counter

1
INPUT CLK 0 1 2 3 4 5 6 7 8
0
FF1 Mode toggle
FF1 𝑄 A

FF2 Mode hold toggle hold toggle hold toggle hold toggle hold toggle
OUTPUTS FF2 𝑄 B

FF3 Mode hold toggle hold toggle hold

FF3 𝑄 C

Binary count 000 001 010 011 100 101 110 111 000 001

Fig. 6-6

The J-K flip-flops are master-slave type.

6.4 Down Counters

Down counter
A counter that counts from higher to lower numbers

- 4-
Logic diagram of a 3-bit ripple down counter (CLR=1)

Preset

𝑃𝑆 𝑃𝑆 𝑃𝑆
1 𝐽 𝑄 1 𝐽 𝑄 1 𝐽 𝑄 C B A
Clock pulses
1 FF1 FF2 FF3
2 1 0 𝐶𝐿𝐾 𝐶𝐿𝐾 𝐶𝐿𝐾 BINARY
0
INPUT OUTPUT
1 𝐾 𝑄ത 1 𝐾 𝑄ത 1 𝐾 𝑄ത
𝐶𝐿𝑅 𝐶𝐿𝑅 𝐶𝐿𝑅

Fig. 6-7

Asynchronous set (PS = 0)

• A preset (PS) control to preset the counter to 111 (decimal 7) to start the download
count

Waveform diagram of a 3-bit ripple down counter

1
INPUT CLK 0 1 2 3 4 5 6 7 8 9
0

FF1 𝑄 A

FF1 𝑄ത

OUTPUTS FF2 𝑄 B

FF2 𝑄ത

FF3 𝑄 C

Binary count 111 110 101 100 011 010 001 000 111 110 101

Fig. 6-8

6.5 Self-Stopping Counters

The down counter shown in Section 6-4 recirculates.

Self-stopping counter
A counter to stop when a sequence is finished

- 5-
Logic diagram of a 3-bit ripple down counter with self-stopping feature

Preset

𝑃𝑆 𝑃𝑆 𝑃𝑆
𝐽 𝑄 1 𝐽 𝑄 1 𝐽 𝑄 C B A
Clock pulses
1 FF1 FF2 FF3
2 1 0 𝐶𝐿𝐾 𝐶𝐿𝐾 𝐶𝐿𝐾
0
INPUT
𝐾 𝑄ത 1 𝐾 𝑄ത 1 𝐾 𝑄ത
𝐶𝐿𝑅 𝐶𝐿𝑅 𝐶𝐿𝑅

Fig. 6-9

An OR gate is added to the 3-bit down counter to place FF1 in the hold mode
immediately after the 000 count.

All 0s in the 000 are fed into an OR gate.

The OR gate outputs the logical 0.

The logical 0s fed back to the J and K inputs of FF1 place it in the hold mode.

This stops FF 1 from toggling, thereby stopping the count at 000.

6.6 Counters as Frequency Dividers

An common use of counter for frequency division

A 1-second timer system

INPUT OUTPUT
Divide by 1 Hz (One pulse
60 Hz
60 circuit per second)

Fig. 6-10

The circuit divides the 60-Hz input frequency by 60.

The output will be one pulse per second (1 Hz).

Divide-by-10 counter
A counter that the output frequency is only one-tenth the input frequency

- 6-
Logic diagram of a decade counter used as a divide-by-10 counter
Decade
INPUT counter OUTPUTS

QD D C B A
Clock
QC
CLK
QB
QA

Fig. 6-11

Waveform diagram of a decade counter used as a divide-by-10 counter

INPUT
CLK 0 1 2 3 4 5 6 7 8 9 0 1 2 4 4 5 6 7 8 9 0 1 2 3

OUTPUT
QD

Fig. 6-12

Logic diagram of a mod-6 counter used as a divide-by-6 counter

Mod-6 OUTPUTS
counter
INPUT C B A
Clock QC
CLK QB
QA

Fig. 6-13

Waveform diagram of a mod-6 counter used as a divide-by-6 counter

INPUT
CLK 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5

OUTPUT
QC

Fig. 6-14

The decade counter and a mod-6 counter in series

The divide-by-60 circuit in Fig. 6-10

- 7-