5.

Synchronous Sequential Logic

Outline:
§ Introduction
§ Storage Elements
§ Latches
§ Flip-flops
§ Analysis of Sequential Circuits
§ Summary

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5.1. Introduction
o Sequential Circuits
n Outputs depend on inputs and previous values of outputs (in
contrast to combinational circuits that depends only on current
values of inputs)
n State is stored in memory elements or binary storage elements
o Registers, latches, flipflops

o Most real-world circuits also contain memory.

n Pocket calculators
n Counters, hand-held devices, cell phones, navigation receivers
n Computer systems, digital cameras, personal media players, etc

The binary information

stored in the memory elements
at any given time defines the
state of the sequential circuit at
that time.

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 Introduction…
o Synchronous vs Non-Synchronous Sequential
Circuits:
n Synchronous:
o Behavior can be defined from the knowledge of its signals at discrete
instants of time.
o Storage elements change only at discrete instances of time
o Timing controlled by “clock”, a periodic enable signal
o Clock generator provides train of clock pulses:
• They are called synchronous
circuits because the activity
within the circuit and the
FIGURE 5.2 resulting updating of stored
Synchronous values is synchronized to the
clocked occurrence of clock pulses.
sequential
circuit • The storage elements
(memory) used in clocked
sequential circuits are called
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Introduction…
o Asynchronous:
o Behavior depends up on the input signals at any instant of
time and the order in which the inputs change.
o Circuit can change at any moment in time
o Storage elements are often time delay devices.
o Often the internal propagation delay of logic gates is
sufficient to produce the needed delay.

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5.2. Storage Elements
o Binary storage device capable of storing one bit
o Latch: level-sensitive device
n Control signal: Enable
n State changes with input when enabled (e.g., when Enable = 1)
n Holds last input value when disabled (when Enable = 0)
o Flip-flop: edge-triggered device
n Control signal: periodic clock
n State of flip-flop can only change during clock transition
n Example: Flip-flops change on rising/falling edge of clock
o Why change on an edge?
n Couldn’t we change state while clock is 1?
n That would be a latch!
n Edge is a moment in time, state is duration
n Feedback would continue during clock being 1

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Storage Elements…
o Latches are level-sensitive

o Flip-flops are edge-sensitive

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5.3. Latches
o Characteristics
n Can store one bit of binary information
n Level-sensitive devices, useful for the design of
asynchronous circuits.
n Are basic circuits from which all flip-flops are constructed.
o SR Latch
n Named after functionality: S = set, R = reset
n Specification:
o Inputs: S and R
o Outputs: Q and Q’
n Operation:
o Q=1 and Q’=0 when in set state
o Q=0 and Q’=1 when in reset state
o Under normal conditions, both inputs remain at 0 unless the pulse on S
or R sets or resets latch respectively.
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SR Latch
NOR
o Circuit diagram: implementation
of SR-Latch
Consequently, in
practical applications,
setting both inputs to 1
is forbidden as it
(forbidden ) creates an undefined
next state.
o When set, S=1 and R=0, output Q=1 and Q’=0
n The S input must go back to zero before any other changes.
n Outputs Q & Q’ are normally complement of each other.
o Set and Reset are stable states
n If S=0 and R=0, then state will not change by itself
o What happens if both S,R = 1?
n Both NOR outputs become 0
n Unstable state after releasing S and R

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SR Latch with NAND Gates
o SR Latch can also be implemented with NAND gates.

(forbidden )

n Normally, both inputs are at 1, unless the state has to be

changed.
n Input of 0 to either S or R indicates set or reset
o When S=0 and R=1, Q=1, and it is the set state
o When S=1 and R=0, Q=0 and it is the reset state
n Circuit goes back to 1 after set or reset for next change to occur.
o Referred to as S’R’ latch or SRlatch

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SR Latch with Control Input
o We want to control when latch can change
n Extra control input En (enable)
o SR latch with control input
n Problem: indeterminate state for S=R=1, when En=1
o Circuit:
n NAND gates and S’R’ latch

SR

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 D Latch
o How to remove state for S=1, R=1 ?
o Solution
n Just use one input pin D to indicate set or reset
n Enable bit (En) ensures that latch is only set when
intended
o D latch
n Inputs:
o D (data)
o En (enable)
o Circuit:
The binary information present
at the data input of the D latch
is transferred to the Q output
when the enable input is
asserted.
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D Latch Operation
o Removes disallowed R,S combination
n D latch forwards data while En=1
n D latch holds data when En=0

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D Latch Operation…
o Show the output for this D
latch

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Latch Symbols
o Graphic symbols for latches:
n One output represents the normal output and the other with
the bubble designates the complement output.
n In the case of a NAND gate latch, the bubbles are added to
the inputs to indicate that setting and resetting occur with a
logical 0 signal.

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5.4. Flipflops
o In a flip-flop, data is stored on edge transitions
in contrast to latches.
n Latches: are level triggered

n Flipflops: are edge triggered

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Edge Triggered D Flipflop
o Construct D flip-flop from two latches:
With only a single
input, the D flip-flop
can set or reset the
output, depending on
the value of the D
input immediately
before the clock
o Primary latch transition.
n Reads value of D while CLK is high
n Is disabled when clock is low
o Secondary latch:
n Is disabled when CLK is high (i.e., holds previous value)
n Takes value from master on negative edge of clock

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Operation of D Flipflop

o Edge Triggering:

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Positive Edge Triggered D Flipflop
o Requires three SR latches
o Operation:
n If CLK=0, then S=R=1
o Q remains stable
n If CLK=1 and D=0, then R=0
o Q is reset to 0
o Q remains 0 independent of D
n If CLK=0, then S=R=1
n If CLK=1 and D=1, then S=0
o Q is set to 1
o Q remains 1 independent of D

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Positive Edge …
o Requires three SR latches
o Operation:
n If CLK=0, then S=R=1
o Q remains stable = Q-1
regardless of D (=x)
n If CLK=1 and D=0, then R=0
o Q is reset to 0
n If CLK=1 and D=1, R=0
o Q=0
n If CLK=0, Q remains 0 then
S=R=1
o independent of D
n If CLK=1 and D=1, then S=0
o Q is set to 1
o remains 1 independent of D
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 Other Flip-flops
o J-K Flip flop
n D=JQ’+K’Q
o J=1 and K=0, D=Q’+Q=1 g next clock edge sets output to 1.
o J=0 and K=1, D=0 g next clock edge resets output to 0.
o J=K=1, D=Q’ g next clock edge complements output.
o J= K=0, D=Q g next clock edge leaves output unchanged

• Q ( t ) refers to the present state (i.e., the state present prior to the application of a clock edge).
Q(t + 1) is the next state one clock period later (the state that results from the clock transition).

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Other Flip-flops…
o T Flip flop
n Can be constructed from J-K flip-flop with J=K=T
n D=TQ’+T’Q=TÅQ
o T=0 and D=Q
o T=1 and D=Q’

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5.5. Analysis of Sequential Circuits
o Behavior of clocked sequential circuit determined by
n Inputs
n Outputs
n State of flip-flops
o Analysis process
n Consider all combinations of
o Inputs
o Flip-flop states
n Determine next state and output of circuit
o Concept of a Finite State Machine (FSM)
o Methods
n State equations also called a transition equations
n State table
n State diagram

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 State Equations
o Specifies next state as a
function of current state and
the inputs
o Example 1: State equation for
flip-flops:
n A(t+1) = A(t) x(t) + B(t) x(t)
n B(t+1) = A’(t) x(t)
o Output expression:
n y(t) = (A(t) + B(t)) x’(t)
o Simplification of expression:
n Omit the designation (t) in all
variables since they are
functions of present time.
o A(t+1) = A x + B x
o B(t+1) = A’ x
o y = (A+B) x’
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Flip-flop Input Equations
o Similar to state equations
o Specifies type of flip-flop
used
o In case of D-FFs they are
the same as state
equations.
o Example:
n D = A x + B x=A(t+1)
A

n D = A’ x=B(t+1)
B

n y = (A + B) x’

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State Table
o What needs to be considered in table?
n Inputs
n State of flip-flops
n Next state of flip-flops
n Outputs
o How many entries in state table?
n n inputs
n m states
n Total of 2m+n entries
o For every entry
n Determine flip-flop change by input and current state
o State equation
n Determine the output
o Output equation

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State Table
o State Table

A(t+1)= A x + B x
B(t+1)= A’ x
y(t)= (A + B) x’
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State Table
o Alternate State Table
o Note that state combinations can be
concatenated
n AB = 00 instead of A = 0 and B = 0

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State Diagram
o State diagrams are state transitions represented as graph
n The state diagram gives a pictorial view of state transitions and is
the form more suitable for human interpretation.
n of the circuit’s operation
n Vertices indicate states
n Edges represent transitions
o Edge annotation: “x/y” meaning input is x and output is y
o Easily generated from state table

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Circuit Analysis-Example 2
o Example 2:

o Equation:
n A(t+1) = AÅxÅy (state
equation)
n DA(t+1) = AÅxÅy (flip-flop
equation)
o State Diagram
n Note: no outputs

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Analysis with JK Flip-Flops
o For a D -type flip-flop, the state equation is the same as the
input equation.
o When a flip-flop other than the D type is used, such as JK or
T, it is necessary to refer to the corresponding characteristic
table or characteristic equation to obtain the nextstate values.
o The next-state values of a sequential circuit that uses JK - or
T type flip-flops can be derived as follows:
1. Determine the flip-flop input equations in terms of
the present state and input variables.
2. List the binary values of each input equation.
3. Use the corresponding flip-flop characteristic table
to determine the next-state values in the state
table.

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Analysis with JK Flip-Flops
o Example 3:
o The circuit can be specified by the flip-flop input equations

The circuit has no outputs;

therefore, the state table does
not need an output column.
(The outputs of the flip-flops
may be considered as the
outputs in this case.)

FIGURE 5.18
Sequential circuit with JK
flip-flop

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Analysis with JK Flip-Flops
Step 3:
Use the
o Example 3 Continued:
corresponding flip-
flop characteristic
table to determine
the next-state values
in the state table.

When the present state AB is 10 and

input x is 0, JA and KA are both
equal to 0 and the present state of A
is 1. Therefore, the
next state of A remains the same and
is equal to 1.

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Analysis with JK Flip-Flops
o The next-state values can also be obtained by
evaluating the state equations from the
characteristic equation. This is done by using the
following procedure:
1. Determine the flip-flop input equations in terms of the
present state and input variables.
2. Substitute the input equations into the flip-flop
characteristic equation to obtain the state equations.
3. Use the corresponding state equations to determine the
next-state values in the state table
o The characteristic equations for the flip-flops are
obtained by substituting A or B for the name of the
flip-flop, instead of Q.

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Analysis with JK Flip-Flops
o Example 3 Continued:
o The characteristic equations for the flip-flops are obtained by
substituting A or B for the name of the flip-flop, instead of Q.
o Example for JK-flip-flop, the flip-flop characteristics
equation is:
Q(t + 1) = JQ'+ K ' Q
o Therefore, for the above example: the –flip-flop
characteristics equations are

o Flip-flop input equations are:

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Analysis with JK Flip-Flops
o Example 3 Continued:

o Substituting the values of JA and KA from the input equations,

we obtain the state equation for A

o The state equation provides the bit values for the column
headed “Next State” for A in the state table.
o Similarly, the state equation for flip-flop B can be derived
from the characteristic equation by substituting the values of
JB and KB:

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Analysis with JK Flip-Flops
o Example 3 Continued:
o Result of the state transition equations gives us the same
table as in Table 5.4..

FIGURE
5.19
State
diagram
of the
circuit of
Fig. 5.18

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Analysis with T Flip-Flops
o The analysis of a sequential circuit with T flip-flops
follows the same procedure outlined for JK flip-
flops. The next-state values in the state table can
be obtained by using either the characteristic
table listed in Table 5.1 or the characteristic
equation.
The characteristic table
The characteristic equation

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Analysis with T Flip-Flops
o Example 4- The following circuit has two flip-flops A and B, one
input x, and one output y and can be described algebraically by two
input equations and an output equation:

FIGURE 5.20
Sequential circuit with T
flip-flops (Binary Counter)

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Analysis with T Flip-Flops
o Example 4 Continued
o The values for the next state can be derived from the state
equations by substituting TA and TB in the characteristic equations,
yielding

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Analysis with T Flip-Flops
o Example 4 Continued
• The next-state values for A and B in the
state table are obtained from the
expressions of the two state equations.
• The state diagram of the circuit is
shown in Fig. 5.20 (b). As long as input
x is equal to 1, the
• circuit behaves as a binary counter
with a sequence of states 00, 01, 10,
11, and back to 00.
• When x = 0, the circuit remains in the
same state.
• Output y is equal to 1 when the present
state is 11. Here, the output depends on
the present state only and is
independent of the input.
• The two values inside each circle and
separated by a slash are for the present
state and output.

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5.6. Summary
o Sequential circuits
n Outputs depend on inputs and previous output
values (“history”)
o Binary storage elements (state registers)
n Latches
o Level sensitive (Enable signal)
n Flip-flops
o Edge sensitive (periodic clock signal)
o Positive-edge or negative–edge triggered flip-flops
o D, JK, T flipflops
o Analysis of sequential circuits
n State Equation
n State Table
n State Diagram
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