National Central University 111 Spring Fundamentals of Electronics II

PH Wang

Fundamentals of Electronics II
基礎電學2
2023 Spring
Section 23
Instructor: Assistant Professor Pei-Hsun Wang
王培勳 助理教授
Department of Optics and Photonics

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Latch & Flip-Flops

• Combinational: Output is a function of the present inputs
only.
• Sequential : Output is function both the present and
the past sequence of inputs.
• Circuit “remembers” previous history
• → Latches : with no clock input (on clock level)
• → Flip Flop (F/F): with clock input (on clock edge)

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Edge-triggered D Flip-flop
• Truth table is similar to D latch, but the state only updates at
clock edge.

D Q D Q

CLK L CLK L
Q’ Q’

Rising-edge trigger Falling-edge trigger

D Qn Qn+1
0 0 0
0 1 0 Q+=D
1 0 1
1 1 1 3

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

 National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Edge-triggered D Flip-flop

Rising-edge
Fundamentals of Logic Design, 7th
Edition, Roth/Kinney
4

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

 National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Setup time for Flip-Flop

Fundamentals of Logic Design, 7th

Edition, Roth/Kinney
5

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

National Central University 111 Spring Fundamentals of Electronics II
PH Wang

SR Flip-Flop
• Truth table is similar to SR latch, but the state only updates
at clock edge.

S Q

CLK Qn: present state

R Q’ Qn+1: next state

S R Qn+1
0 0 Qn (no state change)
0 1 0
1 0 1
1 1 - Not allowed
6

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

 National Central University 111 Spring Fundamentals of Electronics II
PH Wang

SR Flip-Flop

Master-slave FF

Rising-edge

Fundamentals of Logic Design, 7th

Edition, Roth/Kinney

Not an edge-triggered point: can be solved by only allowing

S/R changes during high clock. 7

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

National Central University 111 Spring Fundamentals of Electronics II
PH Wang

JK Flip-Flop
• Extended version of the SR flip-flop: a 1 input may be
simultaneously applied to J and K.

J Q J Q

CLK CLK
K Q’ K Q’

Rising-edge trigger Falling-edge trigger

S R Qn+1
0 0 Qn (no state change)
0 1 0 Q+=JQ’+K’Q
1 0 1
1 1 Qn’ (state change)
8

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

 National Central University 111 Spring Fundamentals of Electronics II
PH Wang

JK Flip-Flop

Fundamentals of Logic Design, 7th

Edition, Roth/Kinney

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

National Central University 111 Spring Fundamentals of Electronics II
PH Wang

T Flip-Flop
The one previously used for unreliable D-latch
• Trigger / Toggle flip-flop

T Q

Q’
CLK

T Q Qn+1
0 0 0
0 1 1 Q+=T’Q+TQ’=T⊕Q
1 0 1 Fundamentals of Logic Design, 7th
Edition, Roth/Kinney
1 1 0
10

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

National Central University 111 Spring Fundamentals of Electronics II
PH Wang

T Flip-Flop
If Q=1->R=1 (if T have not terminated)->Q=0
• Trigger / Toggle flip-flop
T must terminate before Q changes state
=> a delay may be needed.
Time sequence
S Q Q t
T CLK delay delay
T t
R Q’
S t

T Q Qn+1 T Qn+1 R t
0 0 0 0 Qn
delay Q
0 1 1 1 Qn ’
1 0 1
R=QT
1 1 0 delay Q’
S=Q’T
11

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

National Central University 111 Spring Fundamentals of Electronics II
PH Wang

Clocked Flip-Flop with Clear and Preset

• CLR = 0 => Q = 0
• PRE = 0 => Q=1
• CLK = PRE = 1 => normal operation

PRE/SET

J Q

CLK
K Q’

CLR

12

E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151