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    This document discusses a class on fundamentals of electronics taught by Assistant Professor Pei-Hsun Wang at National Central University. It covers topics like registers and counters, shift registers, and binary counter design. Registers are groups of flip-flops that store binary data. Counters cycle through a fixed sequence of states using shift registers. Binary counters can be designed systematically using state tables to determine the logic for each bit based on the values of lower order bits and a clock signal.

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    Fundamentals of Electronics 24

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    This document discusses a class on fundamentals of electronics taught by Assistant Professor Pei-Hsun Wang at National Central University. It covers topics like registers and counters, shift registers, and binary counter design. Registers are groups of flip-flops that store binary data. Counters cycle through a fixed sequence of states using shift registers. Binary counters can be designed systematically using state tables to determine the logic for each bit based on the values of lower order bits and a clock signal.

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    This document discusses a class on fundamentals of electronics taught by Assistant Professor Pei-Hsun Wang at National Central University. It covers topics like registers and counters, shift registers, and binary counter design. Registers are groups of flip-flops that store binary data. Counters cycle through a fixed sequence of states using shift registers. Binary counters can be designed systematically using state tables to determine the logic for each bit based on the values of lower order bits and a clock signal.

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    7 views19 pages

    Fundamentals of Electronics 24

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    This document discusses a class on fundamentals of electronics taught by Assistant Professor Pei-Hsun Wang at National Central University. It covers topics like registers and counters, shift registers, and binary counter design. Registers are groups of flip-flops that store binary data. Counters cycle through a fixed sequence of states using shift registers. Binary counters can be designed systematically using state tables to determine the logic for each bit based on the values of lower order bits and a clock signal.

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    of 19

    National Central University 111 Spring Fundamentals of Electronics II

    PH Wang

    Fundamentals of Electronics II
    基礎電學2
    2023 Spring
    Section 24
    Instructor: Assistant Professor Pei-Hsun Wang
    王培勳 助理教授
    Department of Optics and Photonics

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Registers and Counters


    • Registers and register transfers:
    • Registers: group of flip-flop with a common clock input,
    which used to store and shift binary data.

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney
    2

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Registers and Counters


    • Data transfer between registers which is equivalent to 2:1
    MUX

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney
    3

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Registers and Counters


    • Data transfer using tri-state bus.

    10
    00 01 11

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney
    4

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Parallel Adder with Accumulator


    X=xnxn-1…x1

    What is the delay


    requirement for Full
    Adder?
    Y=ynyn-1…y1
    Equivalent diagram:

    Adder with MUX to load initial value


    Fundamentals of Logic Design, 7th
    Edition, Roth/Kinney 5

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Shift Registers
    • A group of flip-flops can store a set of binary number. This
    number can be shifted left or right when a shift signal is
    applied.

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney
    6

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Shift Registers

    Why not use 8 D-FF?

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney
    The output signal has the period synchronized with the clock.
    7

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Shift Registers

    Parallel in, parallel out

    Keep

    Shift
    Load
    Fundamentals of Logic Design, 7th
    Edition, Roth/Kinney 8

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Shift Registers

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney 9

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Shift Registers and Counter


    • Counter: circuit that cycles through a fixed sequence of
    states.

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney 10

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Design of a Binary Counter


    • CBA sequential: 000 => 001 => 010 => 011 => 100 =>101
    =>110 => 111
    • Synchronous counter triggered by a clock
    C’ C B’ B A’ A

    F/F F/F F/F

    Tc TB TA

    A changes as long as T-F/F (A) triggered.


    B changes as long as A=1 &T-F/F (B) triggered.
    C changes as long as A=B=1 &T-F/F (C) triggered.
    Fundamentals of Logic Design, 7th
    Edition, Roth/Kinney 11

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Systematic method (State table)

    Tc=AB TB=A “1” determines the state change of


    the corresponding bit.

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney 12

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Design of a Binary Counter


    Dc DB DA
    • If the T-F/F is replaced with the D F/F

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney

    DB = B ⊕ A DA = A’

    DC=C’AB+CA’+CB’
    = C ⊕ AB

    13

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Up-down Counter
    • U=D=1 is not allowed.

    U=1 D=1

    DC = C ⊕ (UAB+DB’A’) DB = B ⊕ (UA+DA’) DA = A ⊕(U+D)

    If U=1 D=0: DC =C ⊕ AB, B ⊕ A, DA = A’ Fundamentals of Logic Design, 7th


    If U=0 D=1: DC =C ⊕ A’B’, B ⊕ A’, DA = A’ Edition, Roth/Kinney

    14

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Up-down Counter
    DC = C ⊕ (UAB+DB’A’) DB = B ⊕ (UA+DA’) DA = A ⊕(U+D)

    If U=1 D=0: DC =C ⊕ AB, B ⊕ A, DA = A’ Fundamentals of Logic Design, 7th


    If U=0 D=1: DC =C ⊕ A’B’, B ⊕ A’, DA = A’ Edition, Roth/Kinney
    15

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Loadable Counter
    • When Ld=1, the binary data is loaded into the counter on the
    rising clock edge.

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney
    16

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Counters for other Sequences


    • User-defined states:
    • Use T-F/F to implement:
    C B A C+ B+ A+ TC TB TA
    0 0 0 1 0 0 1 0 0
    0 0 1 - - - - - -
    0 1 0 0 1 1 0 0 1
    0 1 1 0 0 0 0 1 1
    1 0 0 1 1 1 0 1 1
    1 0 1 - - - - - -
    1 1 0 - - - - - -
    Fundamentals of Logic Design, 7th
    Edition, Roth/Kinney 1 1 1 0 1 0 1 0 1
    Unspecific state: Do not care

    17

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Counters for other Sequences


    • Use T-F/F to implement:

    C B A C+ B+ A+ TC TB TA
    0 0 0 1 0 0 1 0 0
    0 0 1 - - - - - -
    0 1 0 0 1 1 0 0 1
    0 1 1 0 0 0 0 1 1
    1 0 0 1 1 1 0 1 1
    1 0 1 - - - - - -
    1 1 0 - - - - - -
    1 1 1 0 1 0 1 0 1

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney
    18

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151


    National Central University 111 Spring Fundamentals of Electronics II
    PH Wang

    Implementation with T-F/F


    • TC=C’B’+CB
    • TB=C’A+CB’
    • TA=C+B

    • Timing scheme:

    Error state 0->1 ->(CBA)+=111


    1
    1
    0

    Fundamentals of Logic Design, 7th


    Edition, Roth/Kinney
    19

    E-MAIL : phwang@dop.ncu.edu.tw FAX : 03-4252897 TEL : 03-4227151

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