1 2 3 4 5 6 7 8

00 M
A

0
RD 17 SI PCI-EXPRESS EDGE CONNECTOR A

(C 96 C
+3.3V_BUS

)2 7 ON
+3.3V_BUS

17 16 15 14 11 9 8 1 +3.3V_BUS +3.3V_BUS +12V_BUS +12V_BUS +0.95V

2
+3.3V_BUS +3.3V_BUS 16 15 14 13 R1022
14 11 9 8 1 1 +12V_BUS 16 15 14 13 12 9 1 +0.95V_PG
+3.3V_BUS
+3.3V_BUS +3.3V_BUS 17 16 15 12 9
17 16 15 14 11 9 8 1 +3.3V_BUS 17

3
+3.3V_BUS 10K
+3.3V_BUS 11 9 8 1 +3.3V_BUS

1
1
16 15 14
17 16 15 14 11 9 8 +3.3V_BUS
1 R1021 1 Q1004 17 16

1
F
1K UNNAMED_1_NPN_I129_C MMBT3904 9 8 1 +3.3V_BUS

0
1

3
MPCIE1 RES1005 15 14 11
R1002 2 3
Q1002

1 2

5
45.3K BSH111 B1 A1 PRESENCE 1
R1001 1% +12V PRSNT1_A1 1 Q1003
45.3K B2 A2 UNNAMED_1_CAP_I127_A MMBT3904
+12V +12V

2
1%

1
+12V_BUS RES1005 SOT23_3PIN

吳 14 jo ID
DNI B3 +12V +12V A3 C1021

2
B4 A4 0.1uF
SOT23_3PIN GND GND 6.3V C1011

2
6,17
SMBCLK RES1005 1 2
R1004
SMCLK B5 SMCLK JTAG2 A5 0.1uF
U4B
IN

2
6.3V
6,17
SMBDATA RES1005 0R 1 2
R1003
SMDAT B6 SMDAT JTAG3 A6 JTDIO_LOOP CAP1005_0_55H
SOT23_3PIN C1012 R1005 NC7SZ08P5X_NL
BI

3
RES1005 0R B7 A7 0.1uF 10K CAP1005_0_55H
GND JTAG4 6.3V
DNI
RES1005 B8 +3.3V JTAG5 A8 U4A

1
+3.3V_BUS B9 JTAG1 +3.3V A9 CAP1005_0_55H 1 SOT353_1_1H
2 3
Q1001 B10 3.3Vaux +3.3V A10 4 PERST#_BUF
2,16
BSH111 RES1005
OUT
17 16 15 14 11 9 8 1 +3.3V_BUS B11 A11 2

積 01 ne EN
WAKE_ PERST_
Mechanical Key
B12 RSVD_B12 GND A12 NC7SZ08P5X_NL

1
B13 GND REFCLK+ A13 PCIE_REFCLKP
2 PERST# SOT353_1_1H
SOT23_3PIN OUT
2
PETP0_GFXRP0 B14 PETp0 REFCLK- A14 PCIE_REFCLKN
2
OUT OUT
2
PETN0_GFXRN0 B15 PETn0 GND A15
OUT DNI
B B16 GND PERp0 A16 PERP0
IN 2 B
B17 A17 PERN0 1 2 0R
PRSNT2_B17 PERn0 IN 2 R1007
B18 GND GND A18

源 23 pe TI
2
PETP1_GFXRP1 B19 PETp1 RSVD_A19 A19 RES1005
Place R61 in U100
OUT
2
PETN1_GFXRN1 B20 PETn1 GND A20
OUT
B21 GND PERp1 A21 PERP1
2
IN
B22 GND PERn1 A22 PERN1
2
IN
2
PETP2_GFXRP2 B23 PETp2 GND A23
OUT
2
PETN2_GFXRN2 B24 PETn2 GND A24
OUT
B25 GND PERp2 A25 PERP2
2
IN
Place these caps as close to the PCIE B26 GND PERn2 A26 PERN2
2
IN

01 i( AL
CAP CER 10UF 20% 16V X5R 2
PETP3_GFXRP3 B27 PETp3 GND A27
OUT
connector as possible
2
PETN3_GFXRN3 B28 PETn3 GND A28
OUT
(1206)1.8MM H MAX B29 GND PERp3 A29 PERP3
2
IN
B30 RSVD_B30 PERn3 A30 PERN3
2
IN
B31 PRSNT2_B31 GND A31
B32 GND RSVD_A32 A32
16 PETP4_GFXRP4 B33 A33
+12V_BUS 2 OUT PETp4 RSVD_A33
14
12 2
PETN4_GFXRN4 B34 PETn4 GND A34
OUT
1 +12V_BUS B35 GND PERp4 A35 PERP4
2
IN

(0
9
B36 GND PERn4 A36 PERN4
2
13 IN
1

PETP5_GFXRP5 B37 A37

裴
15 2 PETp5 GND
OUT
C1001 2
PETN5_GFXRN5 B38 PETn5 GND A38
10uF OUT
B39 GND PERp5 A39 PERP5
2
16V IN
B40 GND PERn5 A40 PERN5
2
IN
2

C0805_67 2
PETP6_GFXRP6 B41 PETp6 GND A41
OUT
2
PETN6_GFXRN6 B42 PETn6 GND A42
OUT
+12V_BUS B43 GND PERp6 A43 PERP6
2
IN

00 RM 亮
B44 GND PERn6 A44 PERN6
2
IN
16 15 14 13 12 9 1 +12V_BUS 2
PETP7_GFXRP7 B45 PETp7 GND A45
OUT
2
PETN7_GFXRN7 B46 PETn7 GND A46
OUT
1

B47 GND PERp7 A47 PERP7

2
IN
C1002 C1003 1
PRESENCE B48 PRSNT2_B48 PERn7 A48 PERN7
2
0.15uF 0.15uF IN
16V 16V
B49 GND GND A49
B50 PETp8 RSVD_A50 A50
2

CAP1608 CAP1608 B51 PETn8 GND A51

11 A工 樂
B52 GND PERp8 A52
C +3.3V_BUS B53 GND PERn8 A53 C
B54 PETp9 GND A54
17 16 15 14 11 9 8 1 +3.3V_BUS CAP CER 10UF 10% 6.3V X5R B55 PETn9 GND A55
(0805)1.4MM MAX THICK B56 GND PERp9 A56
1

B57 GND PERn9 A57

C1004 B58 PETp10 GND A58
10uF B59 A59
6.3V PETn10 GND
B60 A60

60
GND PERp10 SYMBOL LEGEND
2

CAP1608_2012_1_53H B61 GND PERn10 A61

)
B62 PETp11 GND A62
+3.3V_BUS B63 PETn11 GND A63 DNI DO NOT
B64 A64

程
GND PERp11 INSTALL
17 16 15 14 11 9 8 1 +3.3V_BUS B65 GND PERn11 A65
B66 PETp12 GND A66 # ACTIVE
1

B67 PETn12 GND A67 LOW

C1005 C1006 C1007 B68 GND PERp12 A68

1)
0.1uF 1uF 0.01uF B69 A69
GND PERn12 DIGITAL
6.3V 6.3V 10V
B70 PETp13 GND A70 GROUND
2

CAP1005_0_55H CAP1005_0_55H CAP1005 B71 PETn13 GND A71

B72 A72

課
GND PERp13 ANALOG
B73 GND PERn13 A73 GROUND
B74 PETp14 GND A74
B75 PETn14 GND A75 BUO BRING UP

+12V_BUS B76 GND PERp14 A76 ONLY

B77 GND PERn14 A77

16 15 14 13 12 9 1 +12V_BUS B78 PETp15 GND A78
B79 PETn15 GND A79
B80 GND PERp15 A80
1

B81 PRSNT2_B81 PERn15 A81

C1008 C1009 C1010 B82 RSVD_B82 GND A82
0.1uF 0.1uF 0.1uF
16V 16V 16V
2

x16 PCIe
CAP1005 CAP1005 CAP1005

EDGECON_PCI_EXPRESS_16

D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.1

Date: Tuesday, August 06, 2013 Sheet 1 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
A
Oland XT M2 PCIe Interface
0
RD 17 SI A

(C 96 C NOTE: Some of the PCIE testpoints will

be available through vias on traces.

)2 7 ON
U1A
220nF for GEN3

TP105
1
PETP0_GFXRP0 AA38 PCIE_RX0P PCIE_TX0P Y33 PCIE_TX0P
C1101 2 10.22uF PERP0
1
IN OUT
1 TP055PRI PETN0_GFXRN0 Y37 PCIE_RX0N PCIE_TX0N Y32 PCIE_TX0N C1102 2 1
0.22uF PERN0
1
IN 6.3V OUT
TP106
CAP1005
PETP1_GFXRP1 Y35 W33 PCIE_TX1P C1103 2 6.3V 1
0.22uF PERP1

1
1 IN PCIE_RX1P PCIE_TX1P OUT 1
CAP1005

F
1 TP055PRI PETN1_GFXRN1 W36 PCIE_RX1N PCIE_TX1N W32 PCIE_TX1N
C1104 2 10.22uF PERN1

0
IN 6.3V OUT
CAP1005
1
PETP2_GFXRP2 W38 PCIE_RX2P PCIE_TX2P U33 PCIE_TX2P C1105 2 6.3V 1
0.22uF PERP2
1
IN CAP1005 OUT
1
PETN2_GFXRN2 V37 PCIE_RX2N PCIE_TX2N U32 PCIE_TX2N C1106 2 10.22uF PERN2
1
IN 6.3V OUT

吳 14 jo ID
CAP1005
1
PETP3_GFXRP3 V35 PCIE_RX3P PCIE_TX3P U30 PCIE_TX3P C1107 2 6.3V 1
0.22uF PERP3
1
IN OUT
1
PETN3_GFXRN3 U36 PCIE_RX3N PCIE_TX3N U29 PCIE_TX3N C1108 2 CAP1005 1
0.22uF PERN3
1
IN 6.3V OUT
CAP1005
1
PETP4_GFXRP4 U38 PCIE_RX4P PCIE_TX4P T33 PCIE_TX4P C1109 2 6.3V 10.22uF PERP4
1
IN CAP1005 OUT
1
PETN4_GFXRN4 T37 PCIE_RX4N PCIE_TX4N T32 PCIE_TX4N C1110 2 1
0.22uF PERN4
1
IN 6.3V OUT
CAP10050.22uF
6.3V
1
PETP5_GFXRP5 T35 PCIE_RX5P PCIE_TX5P T30 PCIE_TX5P C1111 1 2 PERP5
1
IN CAP1005
0.22uF OUT
PETN5_GFXRN5 R36 T29 PCIE_TX5N
C11122 1 PERN5

積 01 ne EN
1 IN PCIE_RX5N PCIE_TX5N OUT 1
6.3V
TP107
CAP1005
6.3V 0.22uF
1
PETP6_GFXRP6 R38 PCIE_RX6P PCIE_TX6P P33 PCIE_TX6P
C11132 1 PERP6
1
IN CAP1005
0.22uF OUT
1 TP055PRI PETN6_GFXRN6 P37 PCIE_RX6N PCIE_TX6N P32 PCIE_TX6N
C11142 1 PERN6
1
IN 6.3V OUT
TP108
P35 P30 CAP1005
6.3V 0.22uF
C11152 1
PETP7_GFXRP7 PCIE_TX7P PERP7
1 IN PCIE_RX7P PCIE_TX7P OUT 1
CAP1005
0.22uF
B 1 IN
TP055PRI PETN7_GFXRN7 N36 PCIE_RX7N PCIE_TX7N P29 PCIE_TX7N
C11162 1 PERN7
OUT 1 B
6.3V
CAP1005
6.3V
N38 NC#N38 NC#N33 N33

源 23 pe TI
M37 N32 CAP1005
NC#M37 NC#N32

M35 NC#M35 NC#N30 N30

L36 NC#L36 NC#N29 N29

L38 NC#L38 NC#L33 L33

K37 NC#K37 NC#L32 L32

01 i( AL
K35 NC#K35 NC#L30 L30
J36 NC#J36 NC#L29 L29

J38 NC#J38 NC#K33 K33

H37 NC#H37 NC#K32 K32

H35 NC#H35 NC#J33 J33

G36 NC#G36 NC#J32 J32

(0
G38 NC#G38 NC#K30 K30
F37 K29

裴
NC#F37 NC#K29

F35 NC#F35 NC#H33 H33 +0.95V

E37 NC#E37 NC#H32 H32
11 9 +0.95V

PCIE_CALR_TX 1.69k pull up for Oland

00 RM 亮
R1013
1
PCIE_REFCLKP AB35 PCIE_REFCLKP PCIE_CALR_TX Y30 PCIE_CALRP 1 21.69K
IN R1014
1
PCIE_REFCLKN AA36 PCIE_REFCLKN PCIE_CALR_RX Y29 PCIE_CALRN 1 2 2K
IN PCIE_CALR_RX 1k pull up for Oland
RES1005_BGA
PX_EN
15,16,17 RES1005_BGA
OUT
1 2 1K AL21 AB39
R1015 PX_EN VSS
DNI VSS E39
+1.8V RES1005 VSS F34

11 A工 樂
1,16
PERST#_BUF AA30 PERSTB VSS F39
IN
C VSS G33 C
VSS G34
16 14 10 9 +1.8V
VSS H31
B11
+PCIE_PVDD 1.8V 200mA VSS H34
1 2 AB37 PCIE_PVDD VSS H39
1

120R J31
VSS
C1143 C1189 C1173 C1175 VSS J34
SMIND1005_0_5H 10uF 1uF 1uF 0.1uF K31

60
6.3V 6.3V 6.3V 6.3V VSS
AA31 NC#33 VSS K34
2

)
CAP1608_0_95H
CAP1005_0_55H_BGA
CAP1005_0_55H_BGACAP1005_0_55H AA32 NC#34 VSS K39
AA33 NC#35 VSS L31
AA34 L34

程
NC#36 VSS
W30 NC#37 VSS M34
Y31 NC#38 VSS M39
VSS N31
V28 NC_BIF_VDDC VSS N34

1)
W29 NC_BIF_VDDC VSS P31
VSS P34
VSS P39
G30 R34

課
PCIE_VDDC VSS
G31 PCIE_VDDC VSS T31
+0.95V H29 PCIE_VDDC VSS T34
H30 PCIE_VDDC VSS T39
J29 PCIE_VDDC VSS U31
J30 PCIE_VDDC VSS U34
L28 PCIE_VDDC VSS V34
1

M28 PCIE_VDDC VSS Y39

C1161 C1160 C1159 C1158 C1150 C1151 C1152 C1153 C1154 C1155 N28 PCIE_VDDC VSS V39
1uF 10uF 10uF 10uF 1uF 1uF 1uF 1uF 1uF 1uF R28 W31
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V PCIE_VDDC VSS
T28 PCIE_VDDC VSS W34
2

CAP1005_0_55H
CAP1608_0_95H
CAP1608_0_95H
CAP1608_0_95H CAP1005_0_55H_BGACAP1005_0_55H_BGA
CAP1005_0_55H_BGA
CAP1005_0_55H_BGA
CAP1005_0_55H_BGA
CAP1005_0_55H U28 PCIE_VDDC VSS Y34

Oland M2 DDR3

BGA0_8X1_2MM29X29-962_OLAND_M2
D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom Oland PCIE Interface 1.1

Date: Tuesday, August 06, 2013 Sheet 2 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

(3)Oland XT MEM Interface Ch A&B

00 M
A

0
RD 17 SI A

(C 96 C
U1B U1C

0 DQA0_<0> C37 4 3 C18 DQA1_<0> 0 0 DQB0_<0> C5 5 3 AA4 DQB1_<0> 0

5 BI DQA0_0 DQA1_0 BI 5 5 BI DQB0_0 DQB1_0 BI 5
5 1 DQA0_<1> C35 DQA0_1 4 3 A18
DQA1_1
DQA1_<1> 1 5 5 1 DQB0_<1> C3 DQB0_1 5 3 AB6
DQB1_1
DQB1_<1> 1 5
BI BI BI BI
5 2 DQA0_<2> A35 DQA0_2 4 3 F18
DQA1_2
DQA1_<2> 2 5 5 2 DQB0_<2> E3 DQB0_2 5 3 AB1
DQB1_2
DQB1_<2> 2 5
BI BI BI BI
5 3 DQA0_<3> E34 DQA0_3 4 3 D17
DQA1_3
DQA1_<3> 3 5 5 3 DQB0_<3> E1 DQB0_3 5 3 AB3
DQB1_3
DQB1_<3> 3 5
BI BI BI BI

)2 7 ON
5 4 DQA0_<4> G32 DQA0_4 4 3 A16
DQA1_4
DQA1_<4> 4 5 5 4 DQB0_<4> F1 DQB0_4 5 3 AD6
DQB1_4
DQB1_<4> 4 5
BI BI BI BI
5 5 DQA0_<5> D33 DQA0_5 4 3 F16
DQA1_5
DQA1_<5> 5 5 5 5 DQB0_<5> F3 DQB0_5 5 3 AD1
DQB1_5
DQB1_<5> 5 5
BI BI BI BI
5 6 DQA0_<6> F32 DQA0_6 4 3 D15
DQA1_6
DQA1_<6> 6 5 5 6 DQB0_<6> F5 DQB0_6 5 3 AD3
DQB1_6
DQB1_<6> 6 5
BI BI BI BI
5 7 DQA0_<7> E32 DQA0_7 4 3 E14
DQA1_7
DQA1_<7> 7 5 5 7 DQB0_<7> G4 DQB0_7 5 3 AD5
DQB1_7
DQB1_<7> 7 5
BI BI BI BI
5 8 DQA0_<8> D31 DQA0_8 4 3 F14
DQA1_8
DQA1_<8> 8 5 5 8 DQB0_<8> H5 DQB0_8 5 3 AF1
DQB1_8
DQB1_<8> 8 5
BI BI BI BI
5 9 DQA0_<9> F30 DQA0_9 4 3 D13
DQA1_9
DQA1_<9> 9 5 5 9 DQB0_<9> H6 DQB0_9 5 3 AF3
DQB1_9
DQB1_<9> 9 5
BI BI BI BI
5 10 DQA0_<10> C30 DQA0_10 4 3 F12
DQA1_10
DQA1_<10> 10 5 5 10 DQB0_<10> J4 DQB0_10 5 3 AF6
DQB1_10
DQB1_<10> 10 5
BI BI BI BI
5 11 DQA0_<11> A30 DQA0_11 4 3 A12
DQA1_11
DQA1_<11> 11 5 5 11 DQB0_<11> K6 DQB0_11 5 3 AG4
DQB1_11
DQB1_<11> 11 5
BI BI BI BI

F
5 12 DQA0_<12> F28 DQA0_12 4 3 D11
DQA1_12
DQA1_<12> 12 5 5 12 DQB0_<12> K5 DQB0_12 5 3 AH5
DQB1_12
DQB1_<12> 12 5

0
BI BI BI BI
5 13 DQA0_<13> C28 DQA0_13 4 3 F10
DQA1_13
DQA1_<13> 13 5 5 13 DQB0_<13> L4 DQB0_13 5 3 AH6
DQB1_13
DQB1_<13> 13 5
BI BI BI BI
5 14 DQA0_<14> A28 DQA0_14 4 3 A10
DQA1_14
DQA1_<14> 14 5 5 14 DQB0_<14> M6 DQB0_14 5 3 AJ4
DQB1_14
DQB1_<14> 14 5
BI BI BI BI
5 15 DQA0_<15> E28 DQA0_15 4 3 C10
DQA1_15
DQA1_<15> 15 5 5 15 DQB0_<15> M1 DQB0_15 5 3 AK3
DQB1_15
DQB1_<15> 15 5
BI BI BI BI

吳 14 jo ID
5 16 DQA0_<16> D27 DQA0_16 4 3 G13
DQA1_16
DQA1_<16> 16 5 5 16 DQB0_<16> M3 DQB0_16 5 3 AF8
DQB1_16
DQB1_<16> 16 5
BI BI BI BI
5 17 DQA0_<17> F26 DQA0_17 4 3 H13
DQA1_17
DQA1_<17> 17 5 5 17 DQB0_<17> M5 DQB0_17 5 3 AF9
DQB1_17
DQB1_<17> 17 5
BI BI BI BI
5 18 DQA0_<18> C26 DQA0_18 4 3 J13
DQA1_18
DQA1_<18> 18 5 5 18 DQB0_<18> N4 DQB0_18 5 3 AG8
DQB1_18
DQB1_<18> 18 5
BI BI BI BI
5 19 DQA0_<19> A26 DQA0_19 4 3 H11
DQA1_19
DQA1_<19> 19 5 5 19 DQB0_<19> P6 DQB0_19 5 3 AG7
DQB1_19
DQB1_<19> 19 5
BI BI BI BI
5 20 DQA0_<20> F24 DQA0_20 4 3 G10
DQA1_20
DQA1_<20> 20 5 5 20 DQB0_<20> P5 DQB0_20 5 3 AK9
DQB1_20
DQB1_<20> 20 5
BI BI BI BI
5 21 DQA0_<21> C24 DQA0_21 DQA1_21 G8 DQA1_<21> 21 5 5 21 DQB0_<21> R4 DQB0_21 5 3 AL7
DQB1_21
DQB1_<21> 21 5
BI BI BI BI
5 22 DQA0_<22> A24 DQA0_22 DQA1_22 K9 DQA1_<22> 22 5 5 22 DQB0_<22> T6 DQB0_22 5 3 AM8
DQB1_22
DQB1_<22> 22 5
BI BI BI BI
5 23 DQA0_<23> E24 DQA0_23 4
DQA1_23 3 K10 DQA1_<23> 23 5 5 23 DQB0_<23> T1 DQB0_23 5 3 AM7
DQB1_23
DQB1_<23> 23 5
BI BI BI BI
24 DQA0_<24> C22 G9 DQA1_<24> 24 24 DQB0_<24> U4 5 3 AK1 DQB1_<24> 24

積 01 ne EN
5 BI DQA0_24 DQA1_24 BI 5 5 BI DQB0_24 DQB1_24 BI 5
5 25 DQA0_<25> A22 DQA0_25 DQA1_25 A8 DQA1_<25> 25 5 5 25 DQB0_<25> V6 DQB0_25 5 3 AL4
DQB1_25
DQB1_<25> 25 5
BI BI BI BI
5 26 DQA0_<26> F22 DQA0_26 DQA1_26 C8 DQA1_<26> 26 5 5 26 DQB0_<26> V1 DQB0_26 5 3 AM6
DQB1_26
DQB1_<26> 26 5
BI BI BI BI
5 27 DQA0_<27> D21 DQA0_27 DQA1_27 E8 DQA1_<27> 27 5 5 27 DQB0_<27> V3 DQB0_27 5 3 AM1
DQB1_27
DQB1_<27> 27 5
BI BI BI BI
5 28 DQA0_<28> A20 DQA0_28 DQA1_28 A6 DQA1_<28> 28 5 5 28 DQB0_<28> Y6 DQB0_28 5 3 AN4
DQB1_28
DQB1_<28> 28 5
BI BI BI BI
5 29 DQA0_<29> F20 DQA0_29 DQA1_29 C6 DQA1_<29> 29 5 5 29 DQB0_<29> Y1 DQB0_29 5 3 AP3
DQB1_29
DQB1_<29> 29 5
BI BI BI BI
B 5 BI
30 DQA0_<30> D19 DQA0_30 DQA1_30 E6 DQA1_<30> 30
BI 5 5 BI
30 DQB0_<30> Y3 DQB0_30 5 3 AP1
DQB1_30
DQB1_<30> 30
BI 5 B
5 31 DQA0_<31> E18 DQA0_31 DQA1_31 A5 DQA1_<31> 31 5 5 31 DQB0_<31> Y5 DQB0_31 5 3 AP5
DQB1_31
DQB1_<31> 31 5
BI BI BI BI

源 23 pe TI
5
MAA_<0> G24 MAA0_0 MAA_8 H19 MAA_<8>
4 5
MAB_<0> P8 MAB0_0 MAB_8 Y9 MAB_<8>
5
BI BI BI BI
5
MAA_<1> J23 MAA0_1 MAA_9 H20 MAA_<9>
4 5
MAB_<1> T9 MAB0_1 MAB_9 W9 MAB_<9>
5
BI BI BI BI
5
MAA_<2> H24 MAA0_2 MAA_10 L13 MAA_<10>
4 5
MAB_<2> P9 MAB0_2 MAB_10 AC8 MAB_<10>
5
BI BI BI BI
5
MAA_<3> J24 MAA0_3 MAA_11 G16 MAA_<11>
4 5
MAB_<3> N7 MAB0_3 MAB_11 AC9 MAB_<11>
5
BI BI BI BI
5
MAA_<4> H26 MAA0_4 MAA_12 J16 MAA_<12>
4 5
MAB_<4> N8 MAB0_4 MAB_12 AA7 MAB_<12>
5
BI BI BI BI
5
MAA_<5> J26 MAA0_5 MAA_BA2 H16 MAA_BA_<2> 4 5
MAB_<5> N9 MAB0_5 MAB_BA2 AA8 MAB_BA_<2>
5
BI BI BI BI
5
MAA_<6> H21 MAA0_6 MAA_BA0 J17 MAA_BA_<0> 4 5
MAB_<6> U9 MAB0_6 MAB_BA0 Y8 MAB_BA_<0>
5
BI BI BI BI

01 i( AL
5
MAA_<7> G21 MAA0_7 MAA_BA1 H17 MAA_BA_<1> 4 5
MAB_<7> U8 MAB0_7 MAB_BA1 AA9 MAB_BA_<1>
5
BI BI BI BI
5
MAA_<13> H23 MAA_13 MAA_14 J19 MAA_<14>
4 5
MAB_<13> T8 MAB_13 MAB_14 W8 MAB_<14>
5
BI BI BI BI
5
MAA_<15> M21 MAA_15 RSVD#M20 M20 5
MAB_<15> U12 MAB_15 RSVD#V12 V12
BI BI

4
DQMA_0 A32 DQMA0_0 DQMA1_0 C14 DQMA_4
4 5
DQMB_0 H3 DQMB0_0 DQMB1_0 AE4 DQMB_4
5
BI BI BI BI
4
DQMA_1 C32 DQMA0_1 DQMA1_1 A14 DQMA_5
4 5
DQMB_1 H1 DQMB0_1 DQMB1_1 AF5 DQMB_5
5
BI BI BI BI

4
DQMA_2 D23 DQMA0_2 DQMA1_2 E10 DQMA_6
4 5
DQMB_2 T3 DQMB0_2 DQMB1_2 AK6 DQMB_6
5
BI BI BI BI
4
DQMA_3 E22 DQMA0_3 DQMA1_3 D9 DQMA_7
4 5
DQMB_3 T5 DQMB0_3 DQMB1_3 AK5 DQMB_7
5
BI BI BI BI

(0 裴
4
QSA_0 C34 QSA0_0 QSA1_0 E16 QSA_4
4 5
QSB_0 F6 QSB0_0 QSB1_0 AB5 QSB_4
5
BI BI BI BI
4
QSA_1 D29 QSA0_1 QSA1_1 E12 QSA_5
4 5
QSB_1 K3 QSB0_1 QSB1_1 AH1 QSB_5
5
BI BI BI BI
4
QSA_2 D25 QSA0_2 QSA1_2 J10 QSA_6
4 5
QSB_2 P3 QSB0_2 QSB1_2 AJ9 QSB_6
5
BI BI BI BI
4
QSA_3 E20 QSA0_3 QSA1_3 D7 QSA_7
4 5
QSB_3 V5 QSB0_3 QSB1_3 AM5 QSB_7
5
BI BI BI BI

4
QSA_0B A34 QSA0_0B QSA1_0B C16 QSA_4B
4 5
QSB_0B G7 QSB0_0B QSB1_0B AC4 QSB_4B
5
BI BI BI BI

00 RM 亮
4
QSA_1B E30 QSA0_1B QSA1_1B C12 QSA_5B
4 5
QSB_1B K1 QSB0_1B QSB1_1B AH3 QSB_5B
5
BI BI BI BI
4
QSA_2B E26 QSA0_2B QSA1_2B J11 QSA_6B
4 5
QSB_2B P1 QSB0_2B QSB1_2B AJ8 QSB_6B
5
BI BI BI BI
4
QSA_3B C20 QSA0_3B QSA1_3B F8 QSA_7B
4 5
QSB_3B W4 QSB0_3B QSB1_3B AM3 QSB_7B
5
BI BI BI BI

4
ODTA0 J21 ODTA0 ODTA1 G19 ODTA1
4 5
ODTB0 T7 ADBIB0 ADBIB1 W7 ODTB1
5
BI BI BI BI

4
CSA0B_0 K24 CSA0B_0 CSA1B_0 M13 CSA1B_0
4 5
CSB0B_0 P10 CSB0B_0 CSB1B_0 AD10 CSB1B_0
5
OUT OUT OUT OUT

11 A工 樂
K27 CSA0B_1 CSA1B_1 K16 L10 CSB0B_1 CSB1B_1 AC10
C C
4
CASA0B K20 CASA0B CASA1B K17 CASA1B
4 5
CASB0B W10 CASB0B CASB1B AA10 CASB1B
5
OUT OUT OUT OUT
4
RASA0B K23 RASA0B RASA1B K19 RASA1B
4 5
RASB0B T10 RASB0B RASB1B Y10 RASB1B
5
OUT OUT OUT OUT
4
WEA0B K26 WEA0B WEA1B L15 WEA1B
4 5
WEB0B N10 WEB0B WEB1B AB11 WEB1B
5
OUT OUT OUT OUT

4
CKEA0 K21 CKEA0 CKEA1 J20 CKEA1
4 5
CKEB0 U10 CKEB0 CKEB1 AA11 CKEB1
5
OUT OUT OUT OUT
CLKA0 H27 J14 CLKA1 CLKB0 L9 AD8 CLKB1

60
4 OUT CLKA0 CLKA1 OUT 4 5 OUT CLKB0 CLKB1 OUT 5
4
CLKA0B G27 CLKA0B CLKA1B H14 CLKA1B
4 5
CLKB0B L8 CLKB0B CLKB1B AD7 CLKB1B
5
OUT OUT OUT OUT

)
+MVDD MVREFD/S =0.7* +MVDD
MVREFD/S =0.7* VDDR1
(GDDR3/4/5)

程
VDDR1
(GDDR3/4/5)
1

1
R3605 R3606
40.2R 40.2R
1% 1%

1)
R3625 use 50ohm for Hynix memory
2

2
MVREFDA L18 MVREFD_A
MVREFDB Y12 MVREFD_B

1
1

1
課
C3602
1uF
C3603 R3608 6.3V R3607
1uF 100R 2 1 MEM_CALRP0 M27 100R
R3603 MEM_CALRP0 1%

2
6.3V
1% 243R
2

2
4,5
DRAM_RST 1 2
R3625 1 2
R3615
DRST AH11 DRAM_RST MVREFSA L20 MVREFSB AA12
OUT 56R 680R
NOT FOR PRODUCTION - FOR BACKUP ONLY;
1

UNNAMED_3_CAP_I248_A

C3608 R3600 Oland M2 DDR3 Oland M2 DDR3

68pF 10K
50V
2

D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom Oland MEMORY INTERFACE 1.1

Date: Tuesday, August 06, 2013 Sheet 3 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
0
(4) DDR3 Memory Channel A

A
U2000

RD 17 SI U2001 U2200

VREF_U2200 M8
U2201

4 3E3 DQA1_<10>
A

(C 96 C
4 VREFCA DQL0 BI 5
4
VREF_U2000 M8 VREFCA 4 3E3
DQL0
DQA0_<15>
BI 5 4
VREF_U2200 M8 VREFCA 4
DQL0 3E3 DQA1_<20>
BI 5 4
VREF_U2200 H1 VREFDQ 4
DQL1 3F7 DQA1_<12>
BI 5
4
VREF_U2000 M8 VREFCA 4
DQL0 3E3 DQA0_<19>
BI 5 4
VREF_U2000 H1 VREFDQ 4 3F7
DQL1
DQA0_<11>
BI 5 4
VREF_U2200 H1 VREFDQ 4
DQL1 3F7 DQA1_<18>
BI 5 4
DQL2 3F2 DQA1_<11>
BI 5
4
VREF_U2000 H1 VREFDQ 4
DQL1 3F7 DQA0_<23>
BI 5 4 3F2
DQL2
DQA0_<14>
BI 5 4
DQL2 3F2 DQA1_<23>
BI 5 5 BI
MAA_<0> N3 A0 4
DQL3 3F8 DQA1_<13>
BI 5
4
DQL2 3F2 DQA0_<18>
5 5
MAA_<0> N3 A0 4 3F8
DQL3
DQA0_<10>
5 5
MAA_<0> N3 A0 4
DQL3 3F8 DQA1_<19>
5 5
MAA_<1> P7 A1 4
DQL4 3H3 DQA1_<8>
5
BI BI BI BI BI BI BI
5 BI
MAA_<0> N3 A0 4
DQL3 3F8 DQA0_<22>
BI 5 5 BI
MAA_<1> P7 A1 4 3H3
DQL4
DQA0_<12>
BI 5 5 BI
MAA_<1> P7 A1 4
DQL4 3H3 DQA1_<21>
BI 5 5 BI
MAA_<2> P3 A2 4
DQL5 3H8 DQA1_<14>
BI 5
5 BI
MAA_<1> P7 A1 4
DQL4 3H3 DQA0_<16>
BI 5 5 BI
MAA_<2> P3 A2 4 3H8
DQL5
DQA0_<8>
BI 5 5 BI
MAA_<2> P3 A2 4
DQL5 3H8 DQA1_<17>
BI 5 5 BI
MAA_<3> N2 A3 4
DQL6 3G2 DQA1_<9>
BI 5
5 BI
MAA_<2> P3 A2 4
DQL5 3H8 DQA0_<20>
BI 5 5 BI
MAA_<3> N2 A3 4 3G2
DQL6
DQA0_<13>
BI 5 5 BI
MAA_<3> N2 A3 4
DQL6 3G2 DQA1_<22>
BI 5 5 BI
MAA_<4> P8 A4 4
DQL7 3H7 DQA1_<15>
BI 5
5 BI
MAA_<3> N2 A3 4
DQL6 3G2 DQA0_<17>
BI 5 5 BI
MAA_<4> P8 A4 4 3H7
DQL7
DQA0_<9>
BI 5 5 BI
MAA_<4> P8 A4 4
DQL7 3H7 DQA1_<16>
BI 5 5 BI
MAA_<5> P2 A5

)2 7 ON
5
BI
MAA_<4> P8 A4 4
DQL7 3H7 DQA0_<21>
BI 5 5
BI
MAA_<5> P2 A5 5
BI
MAA_<5> P2 A5 5
BI
MAA_<6> R8 A6
5 BI
MAA_<5> P2 A5 5 BI
MAA_<6> R8 A6 5 BI
MAA_<6> R8 A6 5 BI
MAA_<7> R2 A7 4
DQU0 3D7 DQA1_<28>
BI 5
5 BI
MAA_<6> R8 A6 5 BI
MAA_<7> R2 A7 4 3D7
DQU0
DQA0_<2>
BI 5 5 BI
MAA_<7> R2 A7 4
DQU0 3D7 DQA1_<2>
BI 5 5 BI
MAA_<8> T8 A8 4
DQU1 3C3 DQA1_<26>
BI 5
5 BI
MAA_<7> R2 A7 4
DQU0 3D7 DQA0_<29>
BI 5 5 BI
MAA_<8> T8 A8 4 3C3
DQU1
DQA0_<6>
BI 5 5 BI
MAA_<8> T8 A8 4
DQU1 3C3 DQA1_<5>
BI 5 5 BI
MAA_<9> R3 A9 4
DQU2 3C8 DQA1_<31>
BI 5
5 BI
MAA_<8> T8 A8 4
DQU1 3C3 DQA0_<27>
BI 5 5 BI
MAA_<9> R3 A9 4 3C8
DQU2
DQA0_<0>
BI 5 5 BI
MAA_<9> R3 A9 4
DQU2 3C8 DQA1_<0>
BI 5 5 BI
MAA_<10> L7 A10/AP 4
DQU3 3C2 DQA1_<24>
BI 5
5
MAA_<9> R3 A9 4
DQU2 3C8 DQA0_<31>
5 5
MAA_<10> L7 A10/AP 4 3C2
DQU3
DQA0_<4>
5 5
MAA_<10> L7 A10/AP 4
DQU3 3C2 DQA1_<7>
5 5
MAA_<11> R7 A11 4
DQU4 3A7 DQA1_<29>
5
BI BI BI BI BI BI BI BI
5 BI
MAA_<10> L7 A10/AP 4
DQU3 3C2 DQA0_<24>
BI 5 5 BI
MAA_<11> R7 A11 4 3A7
DQU4
DQA0_<3>
BI 5 5 BI
MAA_<11> R7 A11 4
DQU4 3A7 DQA1_<3>
BI 5 5 BI
MAA_<12> N7 A12/BC 4
DQU5 3A2 DQA1_<25>
BI 5
5 BI
MAA_<11> R7 A11 4
DQU4 3A7 DQA0_<28>
BI 5 5 BI
MAA_<12> N7 A12/BC 4 3A2
DQU5
DQA0_<5>
BI 5 5 BI
MAA_<12> N7 A12/BC 4
DQU5 3A2 DQA1_<6>
BI 5 5 BI
MAA_<13> T3 A13 4
DQU6 3B8 DQA1_<30>
BI 5
5 BI
MAA_<12> N7 A12/BC 4
DQU5 3A2 DQA0_<25>
BI 5 5 BI
MAA_<13> T3 A13 4 3B8
DQU6
DQA0_<1>
BI 5 5 BI
MAA_<13> T3 A13 4
DQU6 3B8 DQA1_<1>
BI 5 5 BI
MAA_<14> T7 A14 4
DQU7 3A3 DQA1_<27>
BI 5
MAA_<13> T3 4 3B8 DQA0_<30> MAA_<14> T7 4 3A3 DQA0_<7> MAA_<14> T7 4 3A3 DQA1_<4> MAA_<15> M7

F
5 BI A13 DQU6 BI 5 5 BI A14 DQU7 BI 5 5 BI A14 DQU7 BI 5 5 BI A15

0
5
BI
MAA_<14> T7 A14 4
DQU7 3A3 DQA0_<26>
BI 5 5
BI
MAA_<15> M7 A15 5
BI
MAA_<15> M7 A15
5 BI
MAA_<15> M7 A15 +MVDD
+MVDD +MVDD 5 BI
MAA_BA_<0> M2 BA0 VDD B2
+MVDD 5 BI
MAA_BA_<0> M2 BA0 VDD B2 5 BI
MAA_BA_<0> M2 BA0 VDD B2 5 BI
MAA_BA_<1> N8 BA1 VDD D9

吳 14 jo ID
5
MAA_BA_<0> M2 BA0 VDD B2 5
MAA_BA_<1> N8 BA1 VDD D9 5
MAA_BA_<1> N8 BA1 VDD D9 5
MAA_BA_<2> M3 BA2 VDD G7
BI BI BI BI
5
BI
MAA_BA_<1> N8 BA1 VDD D9 5
BI
MAA_BA_<2> M3 BA2 VDD G7 5
BI
MAA_BA_<2> M3 BA2 VDD G7 VDD K2
5 BI
MAA_BA_<2> M3 BA2 VDD G7 VDD K2 VDD K2 VDD K8
VDD K2 VDD K8 VDD K8 VDD N1
VDD K8 VDD N1 VDD N1 4 3
CLKA1 J7 CK VDD N9
VDD N1 4 3
CLKA0 J7 CK VDD N9 4 3
CLKA1 J7 CK VDD N9 4 3
CLKA1B K7 CK VDD R1
4 3
CLKA0 J7 CK VDD N9 4 3
CLKA0B K7 CK VDD R1 4 3
CLKA1B K7 CK VDD R1 3,4
IN
CKEA1 K9 CKE VDD R9
4 3
CLKA0B K7 CK VDD R1 3,4 IN
CKEA0 K9 CKE VDD R9 3,4 IN
CKEA1 K9 CKE VDD R9
3,4 IN
CKEA0 K9 CKE VDD R9
ODTA1 K1 A1

積 01 ne EN
4 3 ODT VDDQ
4 3
ODTA0 K1 ODT VDDQ A1 4 3
ODTA1 K1 ODT VDDQ A1 3,4 IN
CSA1B_0 L2 CS VDDQ A8
4 3
ODTA0 K1 ODT VDDQ A1 3,4
IN
CSA0B_0 L2 CS VDDQ A8 3,4
IN
CSA1B_0 L2 CS VDDQ A8 3,4
IN
RASA1B J3 RAS VDDQ C1
3,4 IN
CSA0B_0 L2 CS VDDQ A8 3,4 IN
RASA0B J3 RAS VDDQ C1 3,4 IN
RASA1B J3 RAS VDDQ C1 3,4 IN
CASA1B K3 CAS VDDQ C9
3,4 IN
RASA0B J3 RAS VDDQ C1 3,4 IN
CASA0B K3 CAS VDDQ C9 3,4 IN
CASA1B K3 CAS VDDQ C9 3,4 IN
WEA1B L3 WE VDDQ D2
3,4 IN
CASA0B K3 CAS VDDQ C9 3,4 IN
WEA0B L3 WE VDDQ D2 3,4 IN
WEA1B L3 WE VDDQ D2 VDDQ E9
3,4 IN
WEA0B L3 WE VDDQ D2 VDDQ E9 VDDQ E9 VDDQ F1
VDDQ E9 VDDQ F1 VDDQ F1 3
QSA_5 F3 DQSL VDDQ H2
BI
VDDQ F1 3 BI
QSA_1 F3 DQSL VDDQ H2 3 BI
QSA_6 F3 DQSL VDDQ H2 3 BI
QSA_7 C7 DQSU VDDQ H9
3
QSA_2 F3 DQSL VDDQ H2 3
QSA_0 C7 DQSU VDDQ H9 3
QSA_4 C7 DQSU VDDQ H9
B BI BI BI B

源 23 pe TI
3 BI
QSA_3 C7 DQSU VDDQ H9
3 BI
DQMA_5 E7 DML VSS A9
3
BI
DQMA_1 E7 DML VSS A9 3
BI
DQMA_6 E7 DML VSS A9 3
BI
DQMA_7 D3 DMU VSS B3
3 BI
DQMA_2 E7 DML VSS A9 3 BI
DQMA_0 D3 DMU VSS B3 3 BI
DQMA_4 D3 DMU VSS B3 VSS E1
3 BI
DQMA_3 D3 DMU VSS B3 VSS E1 VSS E1 VSS G8
VSS E1 VSS G8 VSS G8 3 BI
QSA_5B G3 DQSL VSS J2
VSS G8 3
QSA_1B G3 DQSL VSS J2 3
QSA_6B G3 DQSL VSS J2 3
QSA_7B B7 DQSU VSS J8
BI BI BI
3
BI
QSA_2B G3 DQSL VSS J2 3
BI
QSA_0B B7 DQSU VSS J8 3
BI
QSA_4B B7 DQSU VSS J8 VSS M1
3 BI
QSA_3B B7 DQSU VSS J8 VSS M1 VSS M1 VSS M9

01 i( AL
VSS M1 VSS M9 VSS M9 VSS P1
VSS M9 VSS P1 VSS P1 3,4,5 IN
DRAM_RST T2 RESET VSS P9
VSS P1 3,4,5 IN
DRAM_RST T2 RESET VSS P9 3,4,5 IN
DRAM_RST T2 RESET VSS P9 VSS T1
3,4,5
IN
DRAM_RST T2 RESET VSS P9 VSS T1 VSS T1 L8 27_DDR332MX_I314_ZQ
ZQ VSS T9

1
VSS T1 L8 27_DDR332MX_I91_ZQ
ZQ VSS T9 L8 27_DDR332MX_I210_ZQ
ZQ VSS T9

1
L8 27_DDR332MX_I61_ZQ
ZQ VSS T9 Should be 240 R2201
1

Should be 240 R2001 R2200 Ohms +-1%

243R
VSSQ B1
243R Should be 240 243R
R2000 Ohms +-1%
VSSQ B1 VSSQ B1 VSSQ B9

2
Should be 240 243R
VSSQ B1 VSSQ B9 Ohms +-1% VSSQ B9 VSSQ D1

2
Ohms +-1%
VSSQ B9 VSSQ D1 VSSQ D1 VSSQ D8
2

D1 D8 D8 E2

(0
VSSQ VSSQ VSSQ VSSQ
VSSQ D8 VSSQ E2 VSSQ E2 J1 NC VSSQ E8

裴
VSSQ E2 J1 NC VSSQ E8 J1 NC VSSQ E8 L1 NC VSSQ F9
J1 NC VSSQ E8 L1 NC VSSQ F9 L1 NC VSSQ F9 J9 NC VSSQ G1
L1 NC VSSQ F9 J9 NC VSSQ G1 J9 NC VSSQ G1 L9 NC VSSQ G9
J9 NC VSSQ G1 L9 NC VSSQ G9 L9 NC VSSQ G9
INFINEON 96-BALL
L9 NC VSSQ G9 3,4 IN
ODTA1
INFINEON 96-BALL INFINEON 96-BALL SDRAM 512MB DDR3
INFINEON 96-BALL SDRAM 512MB DDR3 SDRAM 512MB DDR3
IDGH51-04A1F1C-14X
SDRAM 512MB DDR3

00 RM 亮
IDGH51-04A1F1C-14X IDGH51-04A1F1C-14X
IDGH51-04A1F1C-14X

+MVDD
+MVDD

1
CLKA0
3,4 IN
1

R2205

11 A工 樂
1
4.99K
R2007
4.99K
R2011

2
56R VREF_U2200
4
2

VREF_U2000
4

1
402
1 2
UNNAMED_27_CAP_I188_A
C2000
1

0.01uF
10V R2206 C2207 C2201 C2208 C2202

1
C R2008 C2002 C2007 C2001 C2008 3,4
ODTA0 402 4.99K 0.1uF 0.1uF 0.1uF 0.1uF C
4.99K 0.1uF 0.1uF 0.1uF 0.1uF
IN 10V 10V 10V 10V
10V 10V 10V 10V R2012

2
402
56R
2

60 2
CLKA0B
3,4 IN

)
CLKA1
3,4 IN

程 1
R2211
56R
402
C2200

2
1 2
UNNAMED_27_CAP_I169_A

1)
402

1
0.01uF
R2212 10V
402
56R

課
3,4
IN
CLKA1B 2 +MVDD

RN2001A 1 8 120R
MAA_BA_<1>
RN2000D 4 5 120R
+MVDD +MVDD RN2001B 2 7 120R
MAA_BA_<0>
RN2000C 3 6 120R
RN2001C 3 6 120R MAA_<8> RN2000B 2 7 120R
RN2001D 4 5 120R
MAA_<14>
RN2000A 1 8 120R
RN2003D 5 4 120R
MAA_<2>
RN2002D 4 5 120R
RN2003C 6 3 120R
MAA_<5>
RN2002C 3 6 120R
7 2 MAA_<4> 2 7
C2010

C2011

C2012

C2013

C2014

C2015

C2016

C2017

C2018

C2019

C2020

C2021

C2022

C2023

C2024

C2025

C2026

C2027

C2028

C2032

C2033

C2210

C2211

C2212

C2213

C2214

C2215

C2216

C2217

C2218

C2219

C2220

C2221

C2222

C2223

C2224

C2225

C2226

C2227

C2228

C2229

C2230

C2231
RN2003B 120R RN2002B 120R
1

1
RN2003A 8 1 120R RN2002A 1 8 120R
RN2005A 1 8 120R
MAA_<1>
RN2004D 4 5 120R

6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V RN2005B 2 7 120R
MAA_<13>
RN2004C 3 6 120R
RN2005C 3 6 120R
MAA_<3>
RN2004B 2 7 120R
2

2
RN2005D 4 5 120R
MAA_<0>
RN2004A 1 8 120R
1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
RN2007A 1 8 120R
MAA_<9>
RN2006D 4 5 120R
RN2007B 2 7 120R
MAA_<15>
RN2006C 3 6 120R
RN2007C 3 6 120R
MAA_<7>
RN2006B 2 7 120R
+MVDD +MVDD +MVDD RN2007D 4 5 120R
MAA_<6>
RN2006A 1 8 120R
RN2009A 1 8 120R
MAA_<10>
RN2008D 4 5 120R
RN2009B 2 7 120R
MAA_<11>
RN2008C 3 6 120R
RN2009C 3 6 120R
MAA_BA_<2>
RN2008B 2 7 120R
RN2009D 4 5 120R
MAA_<12>
RN2008A 1 8 120R
D D
C2060

C2061

C2062

C2063

C2064

C2065

C2066

C2067

C2068

C2069

C2070

C2071

C2080

C2081

C2082

C2083

C2280

C2281

C2282

C2283
1

1
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2

2
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF
DNI DNI

DNI DNI

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom DDR3 CHA 1.1

Date: Tuesday, August 06, 2013 Sheet 4 of 20

1 2 3 4 5 6 7 8
(5) DDR3 Memory Channel B

00 M
5
VREF_U2400 M8 VREFCA
U2400

5 DQL0
3 E3 DQB0_<12> 0
RD 17 SI 5 5
VREF_U2400 M8 VREFCA
U2401

5
DQL0 3E3 DQB0_<19>
5
5
5
VREF_U2600
VREF_U2600
M8
H1
VREFCA
VREFDQ
U2600

5
DQL0
5
DQL1
3E3
3F7
DQB1_<27>
DQB1_<28>
BI 5
5
5
5
VREF_U2600
VREF_U2600
M8
H1
VREFCA
VREFDQ
U2601

5
DQL0
5
DQL1
3E3
3F7
DQB1_<20>
DQB1_<19>
BI 5
5

(C 96 C
BI BI BI BI
5
VREF_U2400 H1 VREFDQ 5 DQL1
3 F7 DQB0_<11>
5 5
VREF_U2400 H1 VREFDQ 5
DQL1 3F7 DQB0_<23>
5 5
DQL2 3F2 DQB1_<26>
5 5
DQL2 3F2 DQB1_<21>
5
BI BI BI BI
5 DQL2
3 F2 DQB0_<13>
BI 5 5
DQL2 3F2 DQB0_<18>
BI 5 5 BI
MAB_<0> N3 A0 5
DQL3 3F8 DQB1_<30>
BI 5 5 BI
MAB_<0> N3 A0 5
DQL3 3F8 DQB1_<17>
BI 5
5
BI
MAB_<0> N3 A0 5 DQL3
3 F8 DQB0_<10>
BI 5 5
BI
MAB_<0> N3 A0 5
DQL3 3F8 DQB0_<22>
BI 5 5
BI
MAB_<1> P7 A1 5
DQL4 3H3 DQB1_<24>
BI 5 5
BI
MAB_<1> P7 A1 5
DQL4 3H3 DQB1_<23>
BI 5
5
BI
MAB_<1> P7 A1 5 DQL4
3 H3 DQB0_<15>
BI 5 5
BI
MAB_<1> P7 A1 5
DQL4 3H3 DQB0_<16>
BI 5 5
BI
MAB_<2> P3 A2 5
DQL5 3H8 DQB1_<31>
BI 5 5
BI
MAB_<2> P3 A2 5
DQL5 3H8 DQB1_<18>
BI 5
5
MAB_<2> P3 A2 5 DQL5
3 H8 DQB0_<9>
5 5
MAB_<2> P3 A2 5
DQL5 3H8 DQB0_<20>
5 5
MAB_<3> N2 A3 5
DQL6 3G2 DQB1_<25>
5 5
MAB_<3> N2 A3 5
DQL6 3G2 DQB1_<22>
5
BI BI BI BI BI BI BI BI
5
MAB_<3> N2 A3 5 DQL6
3 G2 DQB0_<14>
5 5
MAB_<3> N2 A3 5
DQL6 3G2 DQB0_<17>
5 5
MAB_<4> P8 A4 5
DQL7 3H7 DQB1_<29>
5 5
MAB_<4> P8 A4 5
DQL7 3H7 DQB1_<16>
5
BI BI BI BI BI BI BI BI
5
BI
MAB_<4> P8 A4 5 DQL7
3 H7 DQB0_<8>
BI 5 5
BI
MAB_<4> P8 A4 5
DQL7 3H7 DQB0_<21>
BI 5 5
BI
MAB_<5> P2 A5 5
BI
MAB_<5> P2 A5
5
MAB_<5> P2 A5 5
MAB_<5> P2 A5 5
MAB_<6> R8 A6 5
MAB_<6> R8 A6
BI BI BI BI
MAB_<6> R8 MAB_<6> R8 MAB_<7> R2 5 3D7 DQB1_<13> MAB_<7> R2 5 3D7 DQB1_<2>

)2 7 ON
5 A6 5 A6 5 A7 DQU0 5 5 A7 DQU0 5
BI BI BI BI BI BI
5 BI
MAB_<7> R2 A7 5 DQU0
3 D7 DQB0_<2>
BI 5 5 BI
MAB_<7> R2 A7 5
DQU0 3D7 DQB0_<29>
BI 5 5 BI
MAB_<8> T8 A8 5
DQU1 3C3 DQB1_<10>
BI 5 5 BI
MAB_<8> T8 A8 5
DQU1 3C3 DQB1_<5>
BI 5
5
MAB_<8> T8 A8 5 DQU1
3 C3 DQB0_<6>
5 5
MAB_<8> T8 A8 5
DQU1 3C3 DQB0_<27>
5 5
MAB_<9> R3 A9 5
DQU2 3C8 DQB1_<15>
5 5
MAB_<9> R3 A9 5
DQU2 3C8 DQB1_<0>
5
BI BI BI BI BI BI BI BI
5
MAB_<9> R3 A9 5 DQU2
3 C8 DQB0_<0>
5 5
MAB_<9> R3 A9 5
DQU2 3C8 DQB0_<31>
5 5
MAB_<10> L7 A10/AP 5
DQU3 3C2 DQB1_<8>
5 5
MAB_<10> L7 A10/AP 5
DQU3 3C2 DQB1_<7>
5
BI BI BI BI BI BI BI BI
5 BI
MAB_<10> L7 A10/AP 5 DQU3
3 C2 DQB0_<4>
BI 5 5 BI
MAB_<10> L7 A10/AP 5
DQU3 3C2 DQB0_<24>
BI 5 5 BI
MAB_<11> R7 A11 5
DQU4 3A7 DQB1_<12>
BI 5 5 BI
MAB_<11> R7 A11 5
DQU4 3A7 DQB1_<3>
BI 5
5 BI
MAB_<11> R7 A11 5 DQU4
3 A7 DQB0_<3>
BI 5 5 BI
MAB_<11> R7 A11 5
DQU4 3A7 DQB0_<28>
BI 5 5 BI
MAB_<12> N7 A12/BC 5
DQU5 3A2 DQB1_<9>
BI 5 5 BI
MAB_<12> N7 A12/BC 5
DQU5 3A2 DQB1_<6>
BI 5
5
BI
MAB_<12> N7 A12/BC 5 DQU5
3 A2 DQB0_<5>
BI 5 5
BI
MAB_<12> N7 A12/BC 5
DQU5 3A2 DQB0_<25>
BI 5 5
BI
MAB_<13> T3 A13 5
DQU6 3B8 DQB1_<14>
BI 5 5
BI
MAB_<13> T3 A13 5
DQU6 3B8 DQB1_<1>
BI 5
5
MAB_<13> T3 A13 5 DQU6
3 B8 DQB0_<1>
5 5
MAB_<13> T3 A13 5
DQU6 3B8 DQB0_<30>
5 5
MAB_<14> T7 A14 5
DQU7 3A3 DQB1_<11>
5 5
MAB_<14> T7 A14 5
DQU7 3A3 DQB1_<4>
5
BI BI BI BI BI BI BI BI
5
BI
MAB_<14> T7 A14 5 DQU7
3 A3 DQB0_<7>
BI 5 5
BI
MAB_<14> T7 A14 5
DQU7 3A3 DQB0_<26>
BI 5 5
BI
MAB_<15> M7 A15 5
BI
MAB_<15> M7 A15
5
BI
MAB_<15> M7 A15 5
BI
MAB_<15> M7 A15

F
+MVDD +MVDD

0
+MVDD +MVDD 5
BI
MAB_BA_<0> M2 BA0 VDD B2 5
BI
MAB_BA_<0> M2 BA0 VDD B2
5
MAB_BA_<0> M2 BA0 VDD B2 5
MAB_BA_<0> M2 BA0 VDD B2 5
MAB_BA_<1> N8 BA1 VDD D9 5
MAB_BA_<1> N8 BA1 VDD D9
BI BI BI BI
5
MAB_BA_<1> N8 BA1 VDD D9 5
MAB_BA_<1> N8 BA1 VDD D9 5
MAB_BA_<2> M3 BA2 VDD G7 5
MAB_BA_<2> M3 BA2 VDD G7
BI BI BI BI
5
BI
MAB_BA_<2> M3 BA2 VDD G7 5
BI
MAB_BA_<2> M3 BA2 VDD G7 VDD K2 VDD K2

吳 14 jo ID
VDD K2 VDD K2 VDD K8 VDD K8
VDD K8 VDD K8 VDD N1 VDD N1
VDD N1 VDD N1 5 3
CLKB1 J7 CK VDD N9 5 3
CLKB1 J7 CK VDD N9
5 3
CLKB0 J7 CK VDD N9 5 3
CLKB0 J7 CK VDD N9 5 3
CLKB1B K7 CK VDD R1 5 3
CLKB1B K7 CK VDD R1
5 3
CLKB0B K7 CK VDD R1 5 3
CLKB0B K7 CK VDD R1 3,5
CKEB1 K9 CKE VDD R9 3,5
CKEB1 K9 CKE VDD R9
IN IN
3,5
IN
CKEB0 K9 CKE VDD R9 3,5
IN
CKEB0 K9 CKE VDD R9

5 3
ODTB1 K1 ODT VDDQ A1 5 3
ODTB1 K1 ODT VDDQ A1
5 3
ODTB0 K1 ODT VDDQ A1 5 3
ODTB0 K1 ODT VDDQ A1 3,5
CSB1B_0 L2 CS VDDQ A8 3,5
CSB1B_0 L2 CS VDDQ A8
IN IN
CSB0B_0 L2 A8 CSB0B_0 L2 A8 RASB1B J3 C1 RASB1B J3 C1

積 01 ne EN
3,5 CS VDDQ 3,5 CS VDDQ 3,5 RAS VDDQ 3,5 RAS VDDQ
IN IN IN IN
3,5
IN
RASB0B J3 RAS VDDQ C1 3,5
IN
RASB0B J3 RAS VDDQ C1 3,5
IN
CASB1B K3 CAS VDDQ C9 3,5
IN
CASB1B K3 CAS VDDQ C9
3,5 IN
CASB0B K3 CAS VDDQ C9 3,5 IN
CASB0B K3 CAS VDDQ C9 3,5 IN
WEB1B L3 WE VDDQ D2 3,5 IN
WEB1B L3 WE VDDQ D2
3,5
WEB0B L3 WE VDDQ D2 3,5
WEB0B L3 WE VDDQ D2 VDDQ E9 VDDQ E9
IN IN
VDDQ E9 VDDQ E9 VDDQ F1 VDDQ F1
VDDQ F1 VDDQ F1 3
QSB_7 F3 DQSL VDDQ H2 3
QSB_6 F3 DQSL VDDQ H2
BI BI
3
BI
QSB_1 F3 DQSL VDDQ H2 3
BI
QSB_2 F3 DQSL VDDQ H2 3
BI
QSB_5 C7 DQSU VDDQ H9 3
BI
QSB_4 C7 DQSU VDDQ H9
3 BI
QSB_0 C7 DQSU VDDQ H9 3 BI
QSB_3 C7 DQSU VDDQ H9

3
BI
DQMB_7 E7 DML VSS A9 3
BI
DQMB_6 E7 DML VSS A9

源 23 pe TI
3
BI
DQMB_1 E7 DML VSS A9 3
BI
DQMB_2 E7 DML VSS A9 3
BI
DQMB_5 D3 DMU VSS B3 3
BI
DQMB_4 D3 DMU VSS B3
3
DQMB_0 D3 DMU VSS B3 3
DQMB_3 D3 DMU VSS B3 VSS E1 VSS E1
BI BI
VSS E1 VSS E1 VSS G8 VSS G8
VSS G8 VSS G8 3
QSB_7B G3 DQSL VSS J2 3
QSB_6B G3 DQSL VSS J2
BI BI
3
QSB_1B G3 DQSL VSS J2 3
QSB_2B G3 DQSL VSS J2 3
QSB_5B B7 DQSU VSS J8 3
QSB_4B B7 DQSU VSS J8
BI BI BI BI
3
BI
QSB_0B B7 DQSU VSS J8 3
BI
QSB_3B B7 DQSU VSS J8 VSS M1 VSS M1
VSS M1 VSS M1 VSS M9 VSS M9
VSS M9 VSS M9 VSS P1 VSS P1
VSS P1 VSS P1 3,4,5
DRAM_RST T2 RESET VSS P9 3,4,5
DRAM_RST T2 RESET VSS P9
IN IN
DRAM_RST T2 P9 DRAM_RST T2 P9 T1 T1

01 i( AL
3,4,5 RESET VSS 3,4,5 RESET VSS VSS VSS
IN IN
VSS T1 VSS T1 L8 4_DDR332MX_I151_ZQ
ZQ VSS T9 L8 4_DDR332MX_I228_ZQ
ZQ VSS T9

1
L8 4_DDR332MX4_I21_ZQ
ZQ VSS T9 L8 4_DDR332MX_I118_ZQ
ZQ VSS T9
1

1
Should be 240
R2600 Should be 240 R2601
243R B1 243R B1
R2400 Should be 240 R2401 VSSQ VSSQ
Should be 240 Ohms +-1% Ohms +-1%
243R B1 243R B1 B9 B9
VSSQ VSSQ VSSQ VSSQ

2
Ohms +-1%
Ohms +-1%
VSSQ B9 VSSQ B9 VSSQ D1 VSSQ D1
2

2
VSSQ D1 VSSQ D1 VSSQ D8 VSSQ D8
VSSQ D8 VSSQ D8 VSSQ E2 VSSQ E2
VSSQ E2 VSSQ E2 J1 NC VSSQ E8 J1 NC VSSQ E8
J1 NC VSSQ E8 J1 NC VSSQ E8 L1 NC VSSQ F9 L1 NC VSSQ F9

(0
L1 NC VSSQ F9 L1 NC VSSQ F9 J9 NC VSSQ G1 J9 NC VSSQ G1
J9 NC VSSQ G1 J9 NC VSSQ G1 L9 NC VSSQ G9 L9 NC VSSQ G9

裴
L9 NC VSSQ G9 L9 NC VSSQ G9
INFINEON 96-BALL INFINEON 96-BALL
INFINEON 96-BALL INFINEON 96-BALL SDRAM 512MB DDR3 SDRAM 512MB DDR3
SDRAM 512MB DDR3 SDRAM 512MB DDR3
IDGH51-04A1F1C-14X IDGH51-04A1F1C-14X
IDGH51-04A1F1C-14X IDGH51-04A1F1C-14X
+MVDD +MVDD

00 RM 亮
1

1
R2403 R2609
4.99K 4.99K
2

2
VREF_U2400 VREF_U2600
5 5
CLKB0
3,5 OUT
1

1
R2404 C2401 C2403 C2404 C2402 R2411 R2610 C2604 C2602 C2603 C2601
4.99K 0.1uF 0.1uF 0.1uF 0.1uF 56R 4.99K 0.1uF 0.1uF 0.1uF 0.1uF

11 A工 樂
10V 10V 10V 10V 402 10V 10V 10V 10V
1 2
C2400
2

12

2
0.01uF
10V
402
R2412
56R
402
CLKB0B
3,5
OUT
2
ODTB0 ODTB1
3,5 IN 3,5 IN
CLKB1
3,5 OUT
1

R2611

60
56R
402
1 2

)
C2600
12

0.01uF
10V
402
R2612

程
56R
402
CLKB1B
3,5 OUT
2

+MVDD

1) 課
+MVDD

120R 8
7
1
2
RN2201A MAB_<12> RN2200A 1
2
8
7
120R
+MVDD
C2410

C2411

C2412

C2413

C2414

C2416

C2418

C2419

C2420

C2421

C2422

C2423

C2424

C2425

C2428

C2429

C2430

C2433

C2434

C2435

C2610

C2611

C2612

C2613

C2615

C2616

C2617

C2618

C2619

C2620

C2621

C2622

C2623

C2625

C2626

C2627

C2628

C2629

C2630

C2631

C2632

C2633
120R RN2201B MAB_BA_<2> RN2200B 120R
1

1
120R 6 3 RN2201C MAB_<10> RN2200C 3 6 120R
120R 5 4 RN2201D MAB_<11> RN2200D 4 5 120R
120R 8 1 RN2203A MAB_<14> 1 8
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V RN2202A 120R
120R 7 2 RN2203B MAB_<8> 2 7
RN2202B 120R
2

2
120R 6 3 RN2203C MAB_BA_<0> 3 6
RN2202C 120R
1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
120R 5 4 RN2203D MAB_BA_<1> 4 5
RN2202D 120R
120R 8 1 RN2205A MAB_<7> RN2204A 1 8 120R
120R 7 2 RN2205B MAB_<6> RN2204B 2 7 120R
+MVDD +MVDD +MVDD 120R 6 3 RN2205C MAB_<15> RN2204C 3 6 120R
120R 5 4 RN2205D MAB_<9> RN2204D 4 5 120R
120R 8 1 RN2207A MAB_<0> RN2206A 1 8 120R
120R 7 2 RN2207B MAB_<2> RN2206B 2 7 120R
120R 6 3 RN2207C MAB_<13> RN2206C 3 6 120R
5 4 4 5
C2460

C2461

C2462

C2463

C2464

C2465

C2466

C2467

C2468

C2469

C2470

C2471

C2480

C2481

C2482

C2483

C2680

C2681

C2682

C2683
120R RN2207D MAB_<1> RN2206D 120R
1

1
120R 7 2 RN2209B MAB_<4> RN2208B 2 7 120R
120R 6 3 RN2209C MAB_<3> RN2208C 3 6 120R

6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 120R 5 4 RN2209D MAB_<5> RN2208D 4 5 120R
120R 8 1 RN2209A RN2208A 1 8 120R
2

2
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF

DNI DNI DNI DNI

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom DDR3 CHB 1.1

Date: Tuesday, August 06, 2013 Sheet 5 of 20

 1 2 3 4 5 6 7 8

U1E
PN 2280007900G for 1Mbit (PM25LV010A-100SCE)

00
BIOS1
+3.3V_BUS 60mA +3.3V_BUS VIDEO BIOS
AF23 VDDR3 GPIO_0 AH20 GPIO_0
6 FIRMWARE
OUT

1
Oland XT M2 GPIOs Strap CF XTAL OSC AF24 VDDR3 GPIO_1 AH18 GPIO_1
6 BIOS
OUT
C1 AG23 VDDR3 GPIO_2 AN16 GPIO_2
6
OUT

1
1uF R14
6.3V
AG24 VDDR3

M
2
BIOS(113?)
GPIO_5_AC_BATT AH17 GPIO_5
6 +3.3V_BUS
4.7K U11
GPIO_6_TACH AJ17 GPIO_6
16

0
OUT

2
15,17
SCL AK26 SCL GPIO_7_BLON AK17 GPIO_22_R 1 CE VDD 8
OUT

1
SDA AJ26 AJ13 GPIO_8 3 6 6 GPIO_8_R 2 7

RD 17 SI
15,17 BI SDA GPIO_8_ROMSO RP2C SO HOLD
33R
33R
GPIO_9_ROMSI AH15 GPIO_9 3 6
RP1C 3 WP SCK 6 C4
AJ16 GPIO_10 2 7 4 5 0.1uF
GPIO_10_ROMSCK RP1B GND SI GPIO_9_R
6.3V
AK16 33R
GPIO_11 6

2
GPIO_12 AL16 6 PM25LD010C-SCE
1,17
SMBCLK AJ23 SMBCLK GPIO_13 AM16 6 6 GPIO_9_R
A OUT A
1,17
SMBDATA AH23 SMBDATA GPIO_14_HPD2 AM14 GPIO_14_HPD2
9
GPIO_10_R
BI IN
GPIO_15_PWRCNTL_0 AM13 GPIO_15_VDDC_VID0
15
OUT
GPIO_16 AK14 GPIO_16
6
PIN BASED STRAPS
AG30

(C 96 C
GPIO_17_THERMAL_INT
GPIO_18_HPD3 AN14 +3.3V_BUS STRAP_TX_CFG_DRV_FULL_SWING
GPIO_19_CTF AM17 GPIO_19_CTF
16 Strap to control Transmitter Full/Half Swing for Mode
OUT 4.7K
AF35 NC#75 GPIO_20_PWRCNTL_1 AL13 GPIO_20_VDDC_VID1
15 DNI 1
R1 2 GPIO_0
6 0=Transmitter Half Swing Enabled.
OUT 4.7K
AG36 NC#74 GPIO_21 AJ14 GPIO_21_MVDD_VID
15 MR1 1 2 1=Transmitter Full Swing Enabled.
OUT
AJ27 RSVD#AJ27 GPIO_22_ROMCSB AK13 GPIO_22 4 5
RP2D
AK27 AG32 GPIO_29_VDDC_VID2 33R
RSVD#AK27 GPIO_29 15 STRAP_TX_DEEMPH_EN
OUT 4.7K
GPIO_30 AG33 GPIO_30_VDDC_VID3
15 DNI 1
R2 2 GPIO_1
GPIO_1 6 PCI Express Interface Transmitter De-emphasis Enable
OUT

)2 7 ON
4.7K
AN36 NC#73 CLKREQB AN13 6 MR2 1 2 0: Tx de-emphasis disabled
AP37 NC#72 GENERICA AJ19 1: Tx de-emphasis enabled
GENERICB AK19 DNI PCIe Gen3 capability
4.7K
+1.8V GENERICC AJ20 DNI 1
R3 2 GPIO_2
GPIO_2 6 1 = PCIe Gen3 is supported Cape Verde default 0
4.7K
GENERICD AK20 MR3 1 2 0 = PCIe Gen3 is not supported
GENERICE_HPD4 AJ24

1
GENERICF_HPD5 AH26 DNI VGA DISABLE : 1 for disable (set to 0 for normal operation)
4.7K
R98 GENERICG_HPD6 AH24 DNI 1
R5 2 GPIO_9_R
GPIO_9_R 6
4.7K

F
1K
MR5 1 2

0
HPD1 AK24 HPD1
8
IN
1 2
TEST_PG AH16 TEST_PG GPIO(13,12,11) - CONFIG[2..0]
4.7K
DNI 1
R6 2 GPIO_13
GPIO_13 6 100 - 512Kbit M25P05A (ST)
4.7K

吳 14 jo ID
R33 MR6 1 2 DNI CONFIG[2] 101 - 1Mbit M25P10A (ST)
1K 4.7K 101 - 2Mbit M25P20 (ST)
DNI 1
R7 2 GPIO_12
GPIO_12 6
4.7K 101 - 4Mbit M25P40 (ST)
MR7 1 2 CONFIG[1]
2

101 - 8Mbit M25P80 (ST)

4.7K
Oland M2 DDR3 DNI 1
R8 2 GPIO_11GPIO_11
6 100 - 512Kbit Pm25LV512 (Chingis)
4.7K
MR8 1 2 CONFIG[0] 101 - 1Mbit Pm25LV010 (Chingis)

積 01 ne EN
VIP_DEVICE_STRAP_DIS
V2SYNC H2SYNC ? RESERVED:
Internal use only. Other logic must not affect these signals
1R4 2 10K CLKREQB
6 during RESET.

B B
AUD[1:0]:
4.7K
DNI R10 1 2 V1SYNC
7 AUD[1] HSYNC 00 - No audio function;

源 23 pe TI
4.7K OUT
MR101 2 AUD[0] VSYNC 01 - Audio for DisplayPort only;
10 - Audio for DisplayPort and HDMI if dongle is detected;
DNI 11 - Audio for both DisplayPort and HDMI.
U1D 4.7K
DNI 1
R11 2 H1SYNC
7 HDMI must only be enabled on systems that are legally entitled
4.7K OUT
+1.8V 1
MR11 2 . It is the responsibility of the system designer to
ensure that the system is entitled to support this feature
180mA 10mA/bit AF15 VDDR4 DBG_DATA0 AU1
AG11 VDDR4 DBG_DATA1 AU3

01 i( AL
1

4.7K
AG13 VDDR4 DBG_DATA2 AW3 R13 1 2 GPIO_8_R
GPIO_8_R
6 Internal use only. Other logic must not

C6 AD12 VDDR4 DBG_DATA3 AP6 affect these signals

1uF 4.7K during RESET.
6.3V
AF11 VDDR4 DBG_DATA4 AW5 1
MR13 2
AG15 VDDR4 DBG_DATA5 AU5
2

AF12 VDDR4 DBG_DATA6 AR6

AF13 VDDR4 DBG_DATA7 AW6
DBG_DATA8 AU6
DBG_DATA9 AT7 DNI
4.7K
DBG_DATA10 AV7 DNI R95 1 2 GENLK_VSYNC
7 CEC_DIS
IN

(0
DBG_DATA11 AN7
4.7K
MR951 2

裴
DBG_DATA12 AV9 DNI
AR1 NC#1 DBG_DATA13 AT9 SMS_EN_HARD
4.7K
DBG_DATA14 AR10 R96 1 2 GENLK_CLK
7
IN
AP8 DBG_CNTL0 DBG_DATA15 AW10
AW8 NC#2 DBG_DATA16 AU10 DNI
4.7K
AR3 NC#3 DBG_DATA17 AP10 MR961 2

00 RM 亮
DBG_DATA18 AV11
AR8 NC#4 DBG_DATA19 AT11
R15 4.7K
AU8 NC#5 DBG_DATA20 AR12 1 2 GPIO_5
6
DBG_DATA21 AW12 MEMORY VENDOR SELECTION
MR15 4.7K
+1.8V DBG_DATA22 AU12 1 2
1 221R
2 VREFG AH13 AP12
R17 DBG_VREFG DBG_DATA23 [GPIO_5 : GPIO_16]
110R
R18 1 2 Hynix [1:1]
R16 4.7K Samsung [1:0]
1C8 20.1uF 1 2 GPIO_16
6

11 A工 樂
6.3V Oland M2 DDR3 MR16 4.7K
C 1 2 C

Place the crossfire

testpoints near the ASIC and
not the connector

Please pay attention to the grounding

60 程 )
1)
strategies for these filter capacitors to

maintain a close loop for current.

課
U1F

+1.8V 75mA
AM32 DP_VDDR NC_XTAL_PVDD AF30
1

C13 C14 C15 NC_XTAL_PVSS AF31

10uF 1uF 0.1uF AN32
6.3V 6.3V 6.3V DP_VSSR
2

R22

+0.95V
4.7K
140mA XO_IN2 AW35
21_OLANDM2DDR3_I263_XOIN2
1 2
AN31 DP_VDDC
1

DNI
R26

C31 C16 C17

C45
4.7uF 1uF 0.1uF 4.7K
6.3V 6.3V 6.3V XO_IN AW34
21_OLANDM2DDR3_I263_XOIN
1 2
2 1
2

12pF
+1.8V 50V
1 B52 75mA
+SPV18 AM10 SPLL_PVDD
1

1
120R
D D
R37
C18 C19 C20

1M

3
4
27.000MHz
4.7uF 1uF 0.1uF AN10 AV33 XTALIN
6.3V 6.3V 6.3V SPLL_PVSS XTALIN

Y2
2

1
2

C44
+0.95V
1 B62
+SPV10
150mA AN9 SPLL_VDDC XTALOUT AU34 XTALOUT 2 R36 1 2 1
UNNAMED_21_CAP_I204_B
1

120R 0R 12pF
50V
C21 C22 route 50ohms single-ended/100ohms diff
1uF 0.1uF and keep short
6.3V 6.3V
+1.8V
MICRO-STAR INT'L CO.,LTD
1 2

1 2

1 B72
UNNAMED_21_BEAD_I209_B
200mA CLKTESTA AK10 CLKTESTA 1 C232 CLKTESTA_C 1 R24 2
1

120R H7 0.1uF 51.1R

C24 C34 C35 C26 C27 H8

MPLL_PVDD
MPLL_PVDD CLKTESTB AL10 CLKTESTB 1
6.3V
C282 CLKTESTB_C 1 R25 2 MS-V30114ci203
MS-V301
10uF
6.3V
4.7uF
6.3V
4.7uF
6.3V
1uF
6.3V
0.1uF
6.3V
0.1uF
6.3V
51.1R
MSI
Size Document Description Rev
2

Oland M2 DDR3
Custom Oland GPIO STRAP PLL 1.1

Date: Tuesday, August 06, 2013 Sheet 6 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
0
RD 17 SI
OPTIONAL ESD PROTECTION DIODES

A A

(C 96 C
See BOM for qualified filters

Pseudo differential RGB should be routed from the ASIC to the display

connector without switching reference plane or running over split plane.

U1G

+1.8V B1700

)2 7 ON
2 1 +VDD1DI AC33 VDD1DI R AD39 R_DAC1

1
120R AVSSN AD37

1
C1700 C1701
1uF 0.1uF AC34
6.3V 6.3V VSS1DI R1711 MR1731
150R

2
0R
G AE36 R_VGA

2
+1.8V AVSSN AD35 7
B1701

F
2 1 +AVDD_DAC1 AD34 AVDD
G_DAC1

0
1

1
120R

1
C1702 C1703 B AF37 B_DAC1
1uF 0.1uF AE34 AE38
6.3V 6.3V AVSSQ AVSSN R1712 MR1732
150R

吳 14 jo ID
2

2
0R

2
G_VGA
7
HSYNC AC36 +5V_VESA
R1700
1 2 RSET AB34 RSET VSYNC AC38
499R

1
DDCVGACLK AJ30 R1713 MR1733
AJ31 150R

積 01 ne EN
DDCVGADATA
0R

1
B_VGA
7 R1744 R1745
Oland M2 DDR3 2.2K
2.2K

2
B B
DDCVGACLK
7
R1746
2 1 DDCCLK_VGA
7

源 23 pe TI
33R
R1747
DDCVGADATA
7 2 1 DDCDATA_VGA
7
33R
+5V_VESA

C1999
100nF_6.3V
VVVV301-01S_me

01 i( AL
C11-1047512-S02 MR1708

R1012 0R XXXV301-01S_me 1
HSYNC_DAC1_B 2 HSYNC_VGA 7

1
DNI R11-0000012-W08
U4502A

14

24R
C1741
74VHCT125 12pF
50V +5V_VESA

2
6 H1SYNC 2 3 7
OUT
VVVV301-01S_me

(0
T34-7412502-N47

7
1
裴
4
U4502B
74VHCT125 MR1709

2
6 V1SYNC 5 6 1
VSYNC_DAC1_B 2 VSYNC_VGA
OUT

1
C1760
VVVV301-01S_me

24R
C1740

00 RM 亮

10V
1uF
T34-7412502-N47 12pF

1
50V

2
R1016 0R XXXV301-01S_me
R11-0000012-W08
J1501
TOWS_TIN_VGAF_1
16 SHIELD COMMON

L1730

L1720
11 A工 樂
U4502C 6 GND-R
6
74VHCT125 R_VGA 1 2 1 2 7 R_VGA_R 1 R 11 ID0
C 7 C

1
1 11
9 8 UNNAMED_28_CAP_I416_A 7 G_VGA_R 7 GND-G
0.047uH 0.047uH
R1734 C1731 7 2 G 12SDA
C1734
VVVV301-01S_me 150R 8pF 12pF B_VGA_R GND_B
50V 50V
8
T34-7412502-N47 402 402
3 B HSYNC
13

13 10

2
9 5V
4 ID2 VSYNC
14

L1731

L1721
U4502D 10 GND

60
10
74VHCT125 7
G_VGA 1 2 1 2 5 GND 15SCL

1
5 15

)
12 11 0.047uH
UNNAMED_28_CAP_I414_A
0.047uH
R1735 C1732 C1735
VVVV301-01S_me 150R 8pF 12pF 17 SHIELD

程
402 50V 50V
T34-7412502-N47 402

2
L1732

L1722
U1H

1)
MLPS 7
B_VGA 1 2 1 2

1
R1051 1 2 5.1K PS_0 UNNAMED_28_CAP_I411_A 0.047uH
+1.8V 7 0.047uH
R1052 1 2 5.1K R1736 C1733 C1736
DDCDATA_VGA
C1052 1 2 0.1uF 16V PS_0 AM34 150R 8pF 12pF DDCCLK_VGA

課
7 PS_0 50V 50V
402 402
VSYNC_VGA

2
7
PS_1 AD31 PS_1 CEC_1 AC30 HSYNC_VGA

D2015
MLPS 7
PS_2 AG31 PS_2
+1.8V R1053 1 2 5.1K PS_1
7 2 1 R_VGA_R 7
R1054 1 2 5.1K 7
PS_3 AD33 PS_3 D2016
C1054 1 2 0.1uF 16V GENLK_CLK AD29 GENLK_CLK
6 2 1 G_VGA_R 7
OUT D2017
GENLK_VSYNC AC29 GENLK_VSYNC
6
OUT ESD-MLVG04025R0QV05BP
B_VGA_R
2 1 7
D2018 VVVV301-01S_me
2 1 ESD-MLVG04025R0QV05BPDDCDATA_VGA
MLPS 7
D2019 VVVV301-01S_me
+1.8V R1055 1 2 5.1K PS_2
7
R1056 1 2 5.1K AF32 AJ21 2 1 ESD-MLVG04025R0QV05BP DDCCLK_VGA
NC#25 SWAPLOCKA 7
D2020 VVVV301-01S_me
C1056 1 2 0.1uF 16V V13 NC#28 SWAPLOCKB AK21
U13 2 1 ESD-MLVG04025R0QV05BP VSYNC_VGA
NC#27 7
D2021 VVVV301-01S_me
AG21 NC#26
AC32 2 1 ESD-MLVG04025R0QV05BP HSYNC_VGA
NC#24 7
MLPS AA29 NC#23
VVVV301-01S_me
D R1057 1 2 5.1K PS_3 AC31 ESD-MLVG04025R0QV05BP D
+1.8V 7 NC_SVI2
R1058 1 2 5.1K AD30 NC_SVI2
VVVV301-01S_me
C1058 1 2 0.1uF 16V AD32 AF33 ESD-MLVG04025R0QV05BP
NC_SVI2 NC#39
VVVV301-01S_me

Oland M2 DDR3

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom Oland DAC and MLPS 1.1

Date: Tuesday, August 06, 2013 Sheet 7 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
0
RD 17 SI
OPTIONAL ESD protection diodes
U104
DPA_3N 1 NC 10
DPA_3N

DPA_3P 2 NC 9
DPA_3P

A DPA_2N 4 7 DPA_2N A
U1I NC
DPA_2P 5 NC 6
DPA_2P

ESD-ESD3V3U4ULC-RH

(C 96 C

8
NC#6 AH12
NC#7 AP13 VVVV301-01S_me
NC#8 AP14 D0G-05A0300-I14
NC#9 AP15 ESD_2_5X1
AT13 COMMON
NC#10
NC#11 AN24
AN17 DP_VSS NC#12 AP20 DPA_1N
U105

)2 7 ON
AN19 DP_VSS NC#13 AP21 1 NC 10
DPA_1N

AN27 DP_VSS NC#14 AP22 DPA_1P 2 NC 9

DPA_1P

AN29 DP_VSS NC#15 AP23

AP16 DP_VSS NC#16 AP24 DPA_0N 4 7 DPA_0N
NC
AP17 DP_VSS NC#17 AP25 DPA_0P 5 NC 6
DPA_0P

AP18 DP_VSS NC#18 AP26

AP19 DP_VSS NC#19 AU18 ESD-ESD3V3U4ULC-RH

8
AP27 DP_VSS NC#20 AU28

F
AP28 DP_VSS NC#21 AV19 VVVV301-01S_me

0
AP29 DP_VSS NC#22 AV29 D0G-05A0300-I14
AP30 DP_VSS NC#29 L27 ESD_2_5X1
AR18 N12 COMMON
DP_VSS NC#30

吳 14 jo ID
AR28 DP_VSS NC#31 AG12
AV17 DP_VSS NC#32 M12
AV27 DP_VSS NC#40 AR24
AW14 DP_VSS NC#41 AR14
AW16 DP_VSS NC#42 AT25
AW20 DP_VSS NC#43 AT15
AW22 DP_VSS NC#44 AV25
AW24 DP_VSS NC#45 AV15
AW26 AU26

積 01 ne EN
DP_VSS NC#46
AW30 DP_VSS NC#47 AU16
AW32 DP_VSS NC#48 AR26
NC#49 AR16
NC#50 AT27
AL30 NC#AL30 NC#51 AT17
B AL29 NC#AL29 NC#52 AU30 9 IN
DPA_A0P 1 2
C3530 8 DPA_0P B
0.1uF
AN21 NC#AN21 NC#53 AR20
AK30 NC#AK30 NC#54 AV31 9
DPA_A0N 1 2
C3531 8 DPA_0N

源 23 pe TI
IN 0.1uF
AM30 NC#AM30 NC#55 AT21
AM29 NC#AM29 NC#56 AT31 9
DPA_A1P 1 2
C3532 8 DPA_1P
IN 0.1uF
AM21 NC#AM21 NC#57 AV21
AK29 NC#AK29 NC#58 AR32 9
DPA_A1N 1 2
C3533 8 DPA_1N
IN 0.1uF
NC#59 AU22
AW28 NC#AW28 NC#60 AU32 9
DPA_A2P 1 2
C3534 8 DPA_2P
IN 0.1uF
AW18 NC#AW18 NC#61 AR22
NC#62 AT33 9
DPA_A2N 1 2
C3536 8 DPA_2N
IN

01 i( AL
0.1uF
NC#63 AT23
NC#64 AV23 9
DPA_A3P 1 2
C3537 8 DPA_3P
IN 0.1uF
NC#65 AU24
NC#66 AT29 9
DPA_A3N 1 2
C3538 8 DPA_3N
IN 0.1uF
NC#67 AR30
NC#68 AV13 +5V_VESA
NC#69 AU14
NC#70 AT19
NC#71 AU20

(0
VVVV301-01S_me R2703 R2701 VVVV301-01S_me

裴
R11-0222012-W08 2.2K 2.2K R11-0222012-W08

9 DDC2CLK
IN
Oland M2 DDR3
9 DDC2DATA R2528
BI
100K

00 RM 亮
XXXV301-01S_me R2529
R11-0104042-W08 100K
XXXV301-01S_me
R11-0104042-W08 +5V_VESA
+3.3V_BUS

15 14 11 9 8 1 +3.3V_BUS

11 A工 樂
8

3
C C

1
Q2513 1 1 UNNAMED_7_NPN_I268_B
R2527 2 HPD_DPA
8 HPD_DPA
MMBT3904 10K
C2722
1uF

2
HPD1
6
OUT

2
1
MJ2501

60
R2530
10K
14 9 8 19
HP_DET

)
18

2
GND 17 +5V
GND X1

程
16 SHELL1
15 SDA X2
SCL SHELL2
8
DPA_0P 14 MEC1

1)
DPA_0N 13 NC MEC1
8
CE Remote
8
DPA_1P 12
DPA_1N 11 CK-

課
8
10 CK_Shield
8
DPA_2P
CK+
8 DPA_2N 9
8 D0-
8
DPA_3P 7 D0_Shield
DPA_3N
D0+ MEC2
8
6 MEC2
5 D1- X3
D1_Shield SHELL3
DPA_0N

DPA_1N

DPA_2N

DPA_3N
DPA_0P

DPA_1P

DPA_2P

DPA_3P
8 DDC2CLK 4
D1+
1

1
8 X4
R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720 DDC2DATA 3 SHELL4
D2-

1
499R 499R 499R 499R 499R 499R 499R 499R
D2006 2
1 D2_Shield
ESD-MLVG04025R0QV05BP
2

2
DPA_GND D2+

1
D2007VVVV301-01S_me HDMI19PSM_BLACK-RH-5
ESD-MLVG04025R0QV05BP GND

2
3

VVVV301-01S_me
D D

2
GND
Q2701
TMDP_EN 1 2N7002E
9 IN
2

GND
OVERLAP HDMI WITH DP D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom Oland Connector HDMI/DP 1.1

Date: Tuesday, August 06, 2013 Sheet 8 of 20

1 2 3 4 5 6 7 8
 00
U1J
+0.95V
TXCAP_DPA3P AP34 DPA_A3P 8
OUT

M
11 2 +0.95V TXCAM_DPA3N AR34 DPA_A3N 8
OUT
AK33 DP_VDDC TX0P_DPA2P AW37 DPA_A2P 8
OUT
AK34 AU35

0
DP_VDDC TX0M_DPA2N DPA_A2N OUT 8

1
10V AL33 DP_VDDC TX1P_DPA1P AR37 DPA_A1P 8
OUT

RD 17 SI
C1523 C1524 C1525 AM33 DP_VDDC TX1M_DPA1N AU39 DPA_A1N 8
4.7uF 1uF OUT
AN33 DP_VDDC TX2P_DPA0P AP35 DPA_A0P 8
6.3V 6.3V 0.1uF OUT
AP31 DP_VDDC TX2M_DPA0N AR35 DPA_A0N 8
OUT

2
AP32 DP_VDDC
AP33 DP_VDDC TXCBP_DPB3P AK35 DPB_TXCAP
9
+1.8V TXCBM_DPB3N AL36 DPB_TXCAN
9
TX3P_DPB2P AJ38 DPB_TX0P
9
16 14 10 2 +1.8V AF34 DP_VDDR TX3M_DPB2N AK37 DPB_TX0N
9
AG34 DP_VDDR TX4P_DPB1P AH35 DPB_TX1P
9

(C 96 C
1

1
10V AH34 DP_VDDR TX4M_DPB1N AJ36 DPB_TX1N
9
C1520 C1521 C1522 AJ34 DP_VDDR TX5P_DPB0P AG38 DPB_TX2P
9
4.7uF 1uF 0.1uF
6.3V 6.3V
AL38 DP_VDDR TX5M_DPB0N AH37 DPB_TX2N
9 +5V_VESA
AM37 DP_VDDR

1
)2 7 ON
R1704 R1705
2.2K 2.2K

2
AF39 DP_VSSR
AH39 DP_VSSR
AK39 DP_VSSR
AL34 DP_VSSR
AM35 DP_VSSR
R1707
AN34 DP_VSSR
DDC1DATA 2 1 DDCDATA_DAC1_R

F
AUX1N AL27

0
AN38 DP_VSSR 33R
AUX1P AM27 R1706
AP39 DP_VSSR
DDC1CLK 2 1 DDCCLK_DAC1_R
AR39 DP_VSSR DDC1CLK AM26 DDC1CLK
33R
AU37 DP_VSSR DDC1DATA AN26 DDC1DATA

吳 14 jo ID
AUX2N AM20
AUX2P AN20 DPB_GND
1BTX2P 2
R1501
AM19 DDC2CLK DPB_TX2P 1 2 499R BTX2P
DDC2CLK OUT 8 9 C1501 9
2 1 DPEF_CALR AM39 AL19 DDC2DATA 0.1uF
R1500 DP_CALR DDC2DATA BI 8 6.3V

積 01 ne EN
150R DPB_TX2N 1 2 BTX2M
9 C1502 9
0.1uF 2 1 1 2
6.3V
BTX1P
R1503 BTX2M
R1502
DPB_TX1P 1 2 499R 499R BTX1P
Oland M2 DDR3 9 C1503 9
0.1uF
6.3V
9
DPB_TX1N 1 2
C1504
BTX1M
9
0.1uF 2 1 2 1
6.3V R1505 BTX1M R1504
DPB_TX0P 1 2 499R 499R BTX0P
9 C1505 9
0.1uF
6.3V

源 23 pe TI
9
DPB_TX0N 1 2
C1506
BTX0M
9
0.1uF 2 1 2 1
6.3V
BTXCP R1507 BTX0M R1506
DPB_TXCAP 1 2 499R 499R BTXCP
9 C1507 9
0.1uF
6.3V
9
DPB_TXCAN 1 2
C1508 BTXCM
BTXCM
9
0.1uF 2 1
6.3V R1508
499R
+12V_BUS

+12V_BUS

01 i( AL
16 15 14 13 12 1

3
R1544
10K
Q1501
1 2N7002E
+5V_VESA

2
14 8

TMDP_EN J1500
8
OUT

2
(0

1
X1 SHIELD1

裴
C1543 X2 SHIELD2
0.1uF
16V
MEC1 SHIELD3
+5V_VESA
MEC2 SHIELD4

2
BTX0M 17 TX0-
OPTIONAL ESD PROTECTION DIODES
BTX0P 18 TX0+
BTX1M 9 TX1-

00 RM 亮
17 9 1
BTX1P 10 TX1+
BTX2M 1 TX2-
BTX2P 2 TX2+
U102 3 SHLD24
1 SHLD13
NC 10 11
BTX2P BTX2P
9
2 SHLD05
NC 9 19
BTX2M BTX2M
9
12 TX3-
BTX1P 4 7 BTX1P 13 TX3+

11 A工 樂
9
NC TX4-
9
BTX1M 5 NC 6
BTX1M 4
5 TX4+
ESD-ESD3V3U4ULC-RH 20 TX5-
3

21 TX5+
VVVV301-01S_me DDCCLK_DAC1_R 6 DDCC
D0G-05A0300-I14 9 DDCDATA_DAC1_R 7 DDCD
ESD_2_5X1 2 1
C1526 14 VDDC
COMMON 1uF 15 GND
10V

60
22 SHLDC
U103 BTXCM 24 TXC-

)
+3.3V_BUS

1
1 TXC+
NC 10 23
BTX0P BTX0P D2010 BTXCP
9
2 VSYNC
NC 9 8
BTX0M BTX0M 17 16 15 14 11 8 1 +3.3V_BUS
9 ESD-MLVG04025R0QV05BP

程
HPD_DVIB 16 HPD
24 16 8
9
BTXCP 4 7 BTXCP VVVV301-01S_me
NC
9
BTXCM 5 NC 6
BTXCM

2
3
Q1502
ESD-ESD3V3U4ULC-RH 1 HPD2_IN 1 2 HPD_DVIB

1)
R1518
3

MMBT3904 10K
VVVV301-01S_me

1
D0G-05A0300-I14 6
GPIO_14_HPD2
D2011
OUT

課
ESD_2_5X1
ESD-MLVG04025R0QV05BP

1
COMMON

R1517 VVVV301-01S_me
10K

2
2
DVI_24P-5_451

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom Oland TMDP sDVI 1.1

Date: Tuesday, August 06, 2013 Sheet 9 of 20

 1 2 3 4 5 6 7 8

00 M
0
RD 17 SI
+VDDC

A A

(C 96 C
Oland M2 Power & GND

1
C117 C118 C119 C88 C89 C106 C107 C108
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V

2
)2 7 ON

1
C109 C110 C111 C112 C113 C114 C115 C116
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
+MVDD 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
U1L

2
12
U1K

F
B9 VSS VSS A3

0
AC7 VDDR1 VDDC AA15 C1 VSS VSS A37

1
AD11 VDDR1 VDDC AA17 C39 VSS VSS AA16
AF7 VDDR1 VDDC AA20 C182 C168 C169 C170 C171 C172 C173 C85 E35 VSS VSS AA18
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF

吳 14 jo ID
AG10 VDDR1 VDDC AA22 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
E5 VSS VSS AA2
AJ7 VDDR1 VDDC AA24 F11 VSS VSS AA21

2
AK8 VDDR1 VDDC AA27 F13 VSS VSS AA23
AL9 VDDR1 VDDC AB16 F15 VSS VSS AA26

1
G11 VDDR1 VDDC AB18 F17 VSS VSS AA28
G14 VDDR1 VDDC AB21 C183 C184 C185 C186 C187 C188 C189 C190 C79 F19 VSS VSS AA6

1
G17 AB23 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF F21 AB12
VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
C141 G20 VDDR1 VDDC AB26 F23 VSS VSS AB15

2
0.1uF G23 AB28 F25 AB17

積 01 ne EN
10V VDDR1 VDDC VSS VSS
G26 VDDR1 VDDC AC17 F27 VSS VSS AB20

2
G29 VDDR1 VDDC AC20 F29 VSS VSS AB22
H10 VDDR1 VDDC AC22 F31 VSS VSS AB24
J7 VDDR1 VDDC AC24 F33 VSS VSS AB27
1

1
J9 VDDR1 VDDC AC27 F7 VSS VSS AC11

1
B C134 C135 C136 C137 C138 C139 C140 K11 VDDR1 VDDC AD18 C176 C177 C178 C192 C300 C301 C302 F9 VSS VSS AC13 B
1uF 1uF 1uF 1uF 1uF 1uF 1uF K13 AD21 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF G2 AC16
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDR1 VDDC 6.3V 6.3V 6.3V C191 6.3V 6.3V 6.3V 6.3V VSS VSS
K8 AD23 4.7uF G6 AC18
VDDR1 VDDC VSS VSS

源 23 pe TI
2

1 2

1 2

1 2

1 2

1 2

1 2

1 2
6.3V
L12 VDDR1 VDDC AD26 H9 VSS VSS AC2

12
L16 VDDR1 VDDC AF17 J2 VSS VSS AC21
L21 VDDR1 VDDC AF20 MC176 MC177 MC178 MC191 MC192 MC300 MC301 MC302 J27 VSS VSS AC23
L23 AF22 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF J6 AC26
VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
L26 VDDR1 VDDC AG16 J8 VSS VSS AC28

2
L7 VDDR1 VDDC AG18 Overlap cap pair foorprints (0805 with 0603) K14 VSS VSS AC6
M11 VDDR1 K7 VSS VSS AD15
N11 VDDR1 VDDC AH27 L11 VSS VSS AD17

01 i( AL
P7 VDDR1 VDDC Y23 L17 VSS VSS AD20
R11 VDDR1 VDDC Y26 L2 VSS VSS AD22
U11 VDDR1 L22 VSS VSS AD24
U7 VDDR1 VDDC AH22 L24 VSS VSS AD27
Y11 VDDR1 L6 VSS VSS AD9
Y7 VDDR1 VDDC AH28 M17 VSS VSS AE2
VDDC M26 M22 VSS VSS AE6
VDDC N24 M24 VSS VSS AF10
VDDC R18 N16 VSS VSS AF16

(0
VDDC R21 N18 VSS VSS AF18
R23 N2 AF21

裴
VDDC VSS VSS
VDDC R26 N21 VSS VSS AG17
VDDC T17 N23 VSS VSS AG2
N26 VSS VSS AG6
VDDC T20 N6 VSS VSS AG9
VDDC T22 R15 VSS VSS AJ10
VDDC T24 R17 VSS VSS AJ11

00 RM 亮
VDDC U16 R2 VSS VSS AJ2
VDDC U18 R20 VSS VSS AJ28
VDDC U21 R22 VSS VSS AJ6
VDDC U23 R24 VSS VSS AK11
VDDC U26 R27 VSS VSS AK31
VDDC V17 R6 VSS VSS AK7
VDDC V20 T11 VSS VSS AL11
VDDC V22 T13 VSS VSS AL14

11 A工 樂
VDDC V24 T16 VSS VSS AL17
C VDDC V27 T18 VSS VSS AL2 C
VDDC Y16 T21 VSS VSS AL20
VDDC Y18 T23 VSS VSS AL23
+1.8V VDDC Y21 T26 VSS VSS AL26
+1.8V VDDC Y28 U15 VSS VSS AL32
16 14 9 2
+0.95V U17 VSS
U2 VSS VSS AL6
AF26 AL8

60
250 mA VDD_CT VSS
AF27 VDD_CT U20 VSS VSS AM11
1

)
AG26 VDD_CT BIF_VDDC T27 U22 VSS VSS AM31
C161 C162 C163 AG27 VDD_CT U24 VSS VSS AM9
1uF 1uF 0.1uF N27 U27 AN11

程
6.3V 6.3V 6.3V BIF_VDDC VSS VSS

1
U6 VSS VSS AN2
2

R13 VDDCI C75 C77 C76 V11 VSS VSS AN30

AA13 4.7uF 1uF 1uF V16 AN6
VDDCI 6.3V 6.3V 6.3V VSS VSS
+VDDC AB13 VDDCI V18 VSS VSS AN8

1)
2

2
AC12 VDDCI V21 VSS VSS AP11
AC15 VDDCI V23 VSS VSS AP7
Overlap cap pair foorprints AD13 VDDCI V26 VSS VSS AP9
(0805 with 0603) T12 W2 AR5

課
VDDCI VSS VSS
AD16 VDDCI W6 VSS VSS B11
M15 VDDCI Y15 VSS VSS B13
1

M16 VDDCI Y17 VSS VSS B15

C196 MC196 C195 C194 C193 C87 C86 T15 VDDCI Y20 VSS
10uF 4.7uF 1uF 1uF 0.1uF 0.1uF 0.1uF M23 Y22 B17
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDCI VSS VSS
N13 VDDCI Y24 VSS VSS B19
2

N15 VDDCI Y27 VSS VSS B21

N17 VDDCI AH21 VSS VSS B23
V15 VDDCI TS_A AL31 AG20 VSS VSS B25
N20 VDDCI VSS B27
N22 VDDCI AG22 NC#AG22 VSS B29
Y13 VDDCI A39 VSS_MECH#1 VSS B31
AW1 VSS_MECH#2 VSS B33
R12 VDDCI FB_VDDC AF28 VDDC_ASIC_FB 13 AW39 VSS_MECH#3 VSS B7
OUT
1

R16 VDDCI
MC103 C90 C91 C92 M18 VDDCI AH29 FB_GND
4.7uF 0.1uF 0.1uF 0.1uF
6.3V 6.3V 6.3V 6.3V
AG28 FB_VDDCI
D Oland M2 DDR3 D
2

Oland M2 DDR3

MICRO-STAR INT'L CO.,LTD

MS-V30114ci203
MSI
Size Document Description Rev
Custom Oland Power&GND 1.1

Date: Tuesday, August 06, 2013 Sheet 10 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
A

0
RD 17 SI A

(C 96 C
)2 7 ON
0 F
+3.3V_BUS
+3.3V_BUS

吳 14 jo ID

1
C815 C816 C817 C818
22uF 22uF 4.7uF 0.15uF
6.3V 6.3V 16V 16V

2
積 01 ne EN
+0.95V
9 2 +0.95V

L04-22AB140-SG0
L801 VVVV301-01S_me
B U801 +0.95V_PHASE 2.2uH B

1
30A 1.24mOhm

6 3 UNNAMED_8_APW7153B_I36_LX CHK_S2_4_9X4_9
U801 PIN7 IS PVDD AND PIN8 IS VDD FOR RT8015A PVDD LX#1 11 C820 C821 C822 C823 C824

源 23 pe TI
OUT 10K 22uF 22uF 10uF 10uF 0.1uF
LX#2 4 6.3V 6.3V 6.3V 6.3V 10V

1
R813
1 2

2
0R
+3.3V_BUS
R805 7 VDD
17 16 15 14 11 9 8 1 +3.3V_BUS GND 16V FB 9 15 +0.95V_FB C832
0.1uF
1 2
UNNAMED_8_CAP_I42_B

2
2 1 8 UNNAMED_8_APW7153B_I36_POK
POK C819 22pF
R819
C805 COMP 10 1
UNNAMED_8_APW7153B_I36_COMP
21 2
UNNAMED_8_CAP_I39_A
50V 50V
1000pF NS800

01 i( AL
R809 13K
1 2 1 SHDN/RT 1 2

1
GND 2
324K NS_VIA
R820
1M
5 PGND TH#11 11
TH#12 12

2
TH#13 13
+0.95V_EN# GND
0.95V=Vref x (1+(R813/R830)
UP1706SDDA 0.953=0.8X(1+(10K/52.3K)
UNNAMED_8_MOSN_I64_D

(0 裴
Q848
+0.95V_EN 1 2N7002E
6,17
IN
2

00 RM 亮
11 A工 樂
C C

60 程 )
1) 課
D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom 0.95V 1.1

Date: Tuesday, August 06, 2013 Sheet 11 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
A

0
RD 17 SI A

MVDD (
C) 967 CO
20 NF
吳 14 jo ID
積 01 ne EN
+12V_BUS

1
B B

2
B702 R702

源 23 pe TI
60R 0R L702
0.47uH

2
+MVDD_VIN
+5V_VESA +5V

01 i( AL
R29
680K C10 C38 C33 C9 C730 C40 C39
270uF_16V

21

22

23

24

34
uP1741P U701 0.1uF 10uF 10uF 10uF 10uF 10uF
R32 R9

VIN-1

VIN-2

VIN-3

VIN-4

VIN-5
7 VVVV301-01S_me
2.2 2.2 TON R21 2R2 C71-27116A1-N07
27
9 BOOT
VCC

(0
26 C7 30mil
C2 NC 0.1uF

裴
R12 1uF 32 25
8.2K GND-5 PHASE-5
+MVDD
L04-68B8011-L65
20 L701 VVVV301-01S_me
10 PHASE-4 +MVDD_PHASE 0.68uH
CS 19 30A 1.24mOhm

00 RM 亮
R20 100K PHASE-3 C36 CHK_D2_10X10_1
C11 C12 C37 C30 C25 C32 C41 C42
8 18 NC
POK PHASE-2

1
6.3V/22uF 6.3V/22uF 6.3V/22uF
6.3V/22uF
17 + +
C726 C729
PHASE-1 R27 6.3V/22uF 6.3V/22uF 820uF 820uF
2.5V 2.5V
33 NC 6.3V/22uF 6.3V/22uF

2
IN MVDD_EN 6 PHASE-6
15,12 EN

11 A工 樂
5
GND-6 2 R23 0
C VOUT C
35
GND-8
3 R19
FB 750k

28 C3 150pF
GND-1 OUT 12
1

60
INTREF R235 NS801

)
C29 29 MVDD_VID_FB R28 10k 1 0 2 1 2
GND-2
0.1uF NS_VIA
4

程
GND-7 31
GND-3 R30 R31 C5
PGND-1

PGND-2

PGND-3

PGND-4

PGND-5

PGND-6
+5V NC 10k 0.1uF
30

1)
GND-4 NS802
1 R236 2 1 2
100
11

12

13

14

15

16

NS_VIA

課
remote sense power

D D

MICRO-STAR INT'L CO.,LTD

MS-V30114ci203
MSI
Size Document Description Rev
Custom MVDD 1.1

Date: Tuesday, August 06, 2013 Sheet 12 of 20

1 2 3 4 5 6 7 8
 00
+12V_BUS

16 15 14 13 12
9 1 +12V_BUS

2
0
L602
C609 R608 R609 0.5uH

RD 17 SI
10uF 0R 0R CHK_D2_7X7
0805 L04-05A7321-L65

1
VVVV301-01S_me
GND
8x8 TH
Overlap
+VDDC_Source +VDDC_Source

+VDDC_SOURCE 13 13 +VDDC_SOURCE

1
(C 96 C
+ +
C634 C635 C624 C625 C676 Input Bulk CAP C682 C627 C628 C629 C631
10uF 10uF 10uF 10uF 270uF 270uF 10uF 10uF 10uF 10uF
0805 0805 0805 0805 0805 0805 0805 0805

2
GND GND GND GND

GND
LFPAK D 5 LFPAK D 5
Q612 Q602

Mirrored on PCB Mirrored on PCB 6.3x7 TH 6.3x7 TH Mirrored on PCB Mirrored on PCB
4G SOT669_COLAY 4G SOT669_COLAY

)2 7 ON
COMMON COMMON
LFPAK D 5 LFPAK D 5 Input MLCC Input MLCC S 1 30V S 1 30V
10.8A@25C 10.8A@25C
Q601 Q611 2 0.018R@4.5V, 0.0106R@10V 2 0.018R@4.5V, 0.0106R@10V
85A 85A
3 2.1W@25C 3 2.1W@25C
+/-16V +/-16V
4G SOT669_COLAY 4G SOT669_COLAY
COMMON COMMON
S 1 30V S 1 30V
10.8A@25C 10.8A@25C
2 0.018R@4.5V, 0.0106R@10V 2 0.018R@4.5V, 0.0106R@10V
85A 85A
3 2.1W@25C 3 2.1W@25C
+/-16V +/-16V

0 F
603
QR602
VDDC_UGATE_2 1 2 VDDC_UGATE2_CTR
13
603

5%
13
VDDC_UGATE1_CTR 1 R601 2 VDDC_UGATE_1 L04-03A7171-L65 +VDDC L04-03A7171-L65 0R

吳 14 jo ID
L601 VVVV301-01S_me L612 VVVV301-01S_me

5%
0R 13
LFPAK D 5 LFPAK D 5 VDDC_PHASE_1 0.3uH 13 13 +VDDC 0.3uH VDDC_PHASE_2
Q603 Q604 30A 1.24mOhm 30A 1.24mOhm
CHK_D2_10X10_7 CHK_D2_10X10_7

2
4G SOT669_COLAY 4G SOT669_COLAY

1
COMMON COMMON
Pass transistor Circuit Q661 and R661 for 8V Gate Drive S 1 30V S 1 30V R606

1
10.8A@25C 10.8A@25C 2R2 2R2
2 0.018R@4.5V, 0.0106R@10V 2 0.018R@4.5V, 0.0106R@10V NS602 R616 LFPAK D 5 LFPAK D 5
85A 85A
3 2.1W@25C 3 2.1W@25C 805 NS601 NS_VIA
NS611 805 Q624 Q623

2 1

2 1
積 01 ne EN
+/-16V +/-16V
NS_VIA NS_VIA
This Circuit is only for 8V gate drive circuit application. NS612

2
Assume VCC consumes 200mA total including 5VCC providing
UNNAMED_24_CAP_I31_B NS_VIA UNNAMED_24_CAP_I82_B
4G 4G
SOT669_COLAY SOT669_COLAY

2
COMMON COMMON
buffered output source a minimum 20mA requirement C606 C616 S 1 30V S 1 30V
603 603 10.8A@25C 10.8A@25C
2 0.018R@4.5V, 0.0106R@10V 2 0.018R@4.5V, 0.0106R@10V

1
2.2nF 2.2nF 85A 85A
P(Q_8VCC)max=(12V-8V)*0.2A=800mW 3 2.1W@25C 3 2.1W@25C

1
GND

1
+/-16V +/-16V
R617
261R
R607 1%
261R

2
1%

源 23 pe TI
13
VDDC_LGATE1_CTR 1 R603 2 VDDC_LGATE_1 Place across Place across

2
0R
+12V_BUS LS MOSFET LS MOSFET
603 603
QR604

RC snubber values shown RC snubber values shown R623

VDDC_LGATE_21 2 VDDC_LGATE2_CTR
13

CCSN1

CCSN2
CCSP1

CCSP2
16 15

FB_S

FB_S
0R
13 1 2 VDDC_LGATE_1_1 are for reference only, are for reference only,
+12V_BUS 0R
9 1 13
12V Bus power for 12V Gate Drive

tuning is required tuning is required

12

R624
14
2

1% Route like differential pair Route like differential pair VDDC_LGATE_2_2 1 2

3

10K 0R

01 i( AL
R661

13

13

13

13

13
1

Q661 +VDDC
1

SI2304DS 1
R670
2R2

BAT54KFILM +VDDC
13
2

R699
Optional D611
2 1 1 2
Optional
5%

1
0R

(0
Rdroop
C649 C650 C646 C647 C658 C661 C648 C656 C659 C679
1

裴
0.1uF 0.015uF 10uF 10uF 0.1uF 0.015uF 10uF 10uF 10uF 10uF
2

402 402 402 402

C670 1% 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V 0805 6.3V

2
2

10uF 100K
16V R664
GND GND GND GND GND GND GND GND GND GND
R632 C694 OUT 15,13
2

1uF

15,13
15
0R

1
13

13
1

2R686 0R
1 VCCDRV

00 RM 亮
13
BOOT2
2
1uF 16V

OUT

GND
IN

UNNAMED_24_CAP_I13_B
Output MLCC Output MLCC
VDDC_EN 2R685 0R
1 SS_ICOMP
C612

15 13
VDDC_REF_IN
2

2R684 0R
1 15 13 +VDDC
1

D601
VDDC_PWR_GOOD

Optional
VDDC_LGATE2_CTR

VDDC_REF_IN
VCCDRV

VDDC_PHASE_2
VCC

VDDC PWM WHOLE CHIP ENABLE

VDDC_UGATE2_CTR

BAT54KFILM
VDDC_LGATE1_CTR 13 +VDDC
13 THE RESISTERS SHARE PAD
1

13

11 A工 樂
R698

C602 VDDC_PHASE_1
13 13
1 2 1 2
UNNAMED_24_CAP_I6_A

1
24

23

22

21

20

19
5%

0R 1uF 16V + + + +
C641 C642 C643 C644
820uF 820uF 820uF 820uF
PHASE1

PHASE2
LGATE1

LGATE2
VCC

VCCDRV

R634 2.5V 2.5V 2.5V 2.5V

10K 6.3 x 9 mm, TH 6.3 x 9 mm, TH 6.3 x 9 mm, TH 6.3 x 9 mm, TH

2
1%
R636
1%
PGD 2

1K

13
VDDC_UGATE1_CTR 1 UGATE1 U601 UGATE2 18 1 2 5VCC
13 14 GND GND GND

60
UP1610
BOOT1 2 17

)
BOOT1 BOOT2 Overlap the footprints for MR655 and C655
0R
C660 2 1
MR655
2 1 3 5VCC POK 16 C654

程
R654 5% Output Bulk CAPs
6.3V 1 2 2
UNNAMED_24_CAP_I150_B
0.0022uF 1
150R
1uF 4 AGND REFIN 15 50V
C655
0R
13,14
5VCC
1 2 UNNAMED_24_RES_I117_B
5 MODE 13
SS/EN 14 SS_ICOMP 1 2
0.022uF
OUT
MR610

1)
16V
1

R610
6 CSP1 FB 13 VDDC_FB
15
IN
SHARE PAD
2
0R

0R
PIN5 PH2 EN PGND1 25 50V 2 1 FB_S
13
220pF

課
R658
-HI, PH 2 DISABLE,PH1 ENABLED; PGND2 26 C607 C3
2

-LO, PH 1 AND PH 2 ENABLED. PGND3 27 1 R653 2 2 1

UNNAMED_24_CAP_I147_B
C653
300R 2.2NF
28
COMP
CSN1

CSN2

CSP2

PGND4 R3
IOUT

1
RT

GND R651
1K VDDC_ASIC_FB
1 2 1% VDDC_SV 2 R600 1 15 +VDDC
IN
7

10

11

12
1 CSN1
CSP1

0R
RFB1
1
CSN2

603
CSP2

R656
1

0R
UNNAMED_24_CAP_I135_A
2 1 Reserve for C601
Loop Measurement 0.1uF
R605 R615 R662 C638 6.3V
1
Rdroop

324R 324R 56K 1uF GND

C1 R652
2

1% 1% 1% 6.3V

2
10K
MR666 1 C652 2 2
UNNAMED_24_CAP_I138_B
1 2 R657 1 5%
2

10NF 0R 300R
C604 C614 R1 R696
0R

2 1 2 1
5VCC

R656, R657 SHARE PAD

2

1
16V

16V
1uF

1uF

UNNAMED_24_RES_I128_A
C651 1 2
UNNAMED_24_CAP_I136_A
UNNAMED_24_CAP_I136_B

1
1

33pF
R663 C2
100K
Close to U601 R666 Type III Compensation
1%
1

6.3V 33.2K
Rdroop option
2

1%
1

0.1uF
C605 C615
2

0.1uF
R604 6.3V R614 +VDDC LOAD
464R 464R
2

1% 1%
Choosing Different Gate Drive
2

CCSP2
13 5V Gate Drive
Populate R631,R632 and Do Not Populate R630,R670,C660,R661,Q661
CCSN2
13
8V Gate Drive
CCSN1
13 Populate R630, C660, R661,Q661, and Do Not Populate R631,R632,R670
MICRO-STAR INT'L CO.,LTD
CCSP1
13 12V Gate Drive
Popualte R630,C660,R670, and Do Not Populate R631,R632,R661,Q661 MS-V301
MSI
Size Document Description Rev
Custom VDDC 1.1

Date: Tuesday, August 06, 2013 Sheet 13 of 20

 1 2 3 4 5 6 7 8

00 M
A

0
RD 17 SI A

(C 96 C
Linear Regulators
LDO #1:

)2 7 ON
Vin = 3.00V to 3.60V (3.3V +/- 9%) Vout = +1.8V +/- 2%; Iout = 1.6A (TBV) RMS MAX

0 F
PCB: 50 to 70mm sq. copper area for cooling
Regulators for +5V, +5V_VESA and +5V_VESA2

吳 14 jo ID
積 01 ne EN
16 15 13 12 9 1 +12V_BUS

5V regulator change to SOT223 package

B 100mA B
+5V_VESA
Vout=1.25V* [1+(ER305/ER304) ]

源 23 pe TI
9 8 +5V_VESA

4
U400

4
F400

ADJ/GND
3 2 1 2
VIN VOUT

1
200mA
24V
C411

1
1.8V WORST-CASE REQUIREMENT 1uF
ER304

1
6.3V

01 i( AL
+3.3V_BUS C410 RC1117S_SOT223 121 EC135 EC134

2
17 16 15 14 11 9 8 1 +3.3V_BUS 1uF 10uF 10uF
Est. Current 16V
Display Config 0603

2
16V

DVI+HDMI+DP 1330mA

ER305
1/4W@1206 365

(0
17 +3.3V_BUS
9 8 1 +3.3V_BUS

裴
11
1

16 15 14
+1.8V
+5V C866 16 10 9 2 +1.8V
10uF
6.3V
1

+5V
2

R862 R863
10K 10K
DNI

00 RM 亮
1

1
U861
2

3 VIN VOUT 6 R865 C865 C862 C861 C864

13K 33pF 10uF 10uF 0.1uF
R5
1% 50V 6.3V 6.3V 16V
4 VDD FB 7 LDO1_FB DNI +12V_BUS +5V
2

2
1

15
+1.8V_EN 2 EN NC 5 LDO1_REFIN R4
IN
1

1
THMPAD

C868
1uF +1.8V_LDO_POK 1 8
15 POK GND R864 R450
6.3V OUT

11 A工 樂
1%
10K 360R
2

C GS7133SO-R VOUT = Vref x (1 + R5/R4) C

9

2
MR451
1 2 UNNAMED_13_RES_I99_B

0R
R451
1 R8662 1 2 5VCC
13
0R
0R

1
BZT52C5V1
D450
60

2
程 )
1) 課
D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom Linear Regulators 1.1

Date: Tuesday, August 06, 2013 Sheet 14 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
+3.3V_BUS

0
+3.3V_BUS
VDDC Low Side Divider
Power Management - Power Gating and Dynamic Voltage Control

RD 17 SI
12V_BUS & 3V3_BUS POWER SEQUENCING +3.3V_BUS

1
17
+3.3V_BUS +12V_BUS +12V_BUS

1
14 VDDC_FB
9 R1006 R1008 13 IN
1 +3.3V_BUS 15 14 13 12 9 1 +12V_BUS 13 12 9 1 45.3K 45.3K
1% 1% C681

1
A 8 16 16 15 14 0.1uF A

2
11 10V

1
16 R688 +3.3V_BUS R671 R672

2
2
+1.8V_EN U680 25.5K 20K 20K
R857 Node 1 14,15 R678 R676
OUT RES1005 RES1005
1%
20K 20K
1 8 GPIO_15_VDDC_VID0

(C 96 C
VCC VID0 6 15

2
2
10K

R689
2 GND VID1 7 GPIO_20_VDDC_VID1
6 15
VDD_FB_IN1

2
1

1
R839
R852 6,17 3 SCL VREF 6 VDDC_REF 1 2 VDDC_REF_IN
13 R673 VDDC_FB_IN2
IN OUT

3
PSEQ_N1 2 1 1 SDA 4 5 0R 20K
R850 Q852 6,17
BI SDA R1 R650

1
2.32K 11.3K 5.1K 20K
UNNAMED_14_CAP_I10_A
MMBT3904 UNNAMED_14_RES_I251_A

1
3

1
RFB2
PSEQ_N3 C846 Place close uP1801AMT8 C680 Q606
2

2
15 0.1uF 0.033uF 2N7002E 402
1 Q850 to its CTLR
R687 6,15
GPIO_15_VDDC_VID0 1
10V 16V
22.1K
IN
Node 3 MMBT3904 +3.3V_BUS

2
1%

2
)2 7 ON
UNNAMED_14_NPN_I18_E

2
MR673

2
20K

3
R674

1
PSEQ_N2 1 20K
Q851
Node 2 MMBT3904 Q607

1
1

GPIO_20_VDDC_VID1 1 2N7002E
6,15 IN
GPIO_20_VDDC_VID1

2
1

R851

F
1K UNNAMED_14_RES_I399_A
R853

2
2

1
1K
2

MR674 R679
2

20K 20K

吳 14 jo ID
UNNAMED_14_RES_I393_A
+12V_BUS

2
1
+3.3V_BUS
R680
20K

2
UNNAMED_14_MOSN_I385_D
R675

3
20K

1
+12V_BUS

1
R833

積 01 ne EN
Q608
5.1K GPIO_29_VDDC_VID2 1 2N7002E
6 IN

2
1

2
+1.8V

2
+0.95V_EN
R832 MR675
OUT 11 20K
5.1K
B +3.3V_BUS B
2

1
3

1
1
R831
1 2 1 UNNAMED_14_NPN_I304_B
Q838

源 23 pe TI
1

5.1K MMBT3904 R888

C898 R677

2
0.1uF UNNAMED_14_MOSN_I381_D
R885 5.1K

2
10V

3
1K

2
2
20K
2

Q609

1
+1.8V_LDO_POK R845 2N7002E
14 2 1 1 Q839 6
GPIO_30_VDDC_VID3 1
IN 5.1K IN
MMBT3904
VDDC_EN
VDDC_EN

OUT 15,13
2

2
01 i( AL
1

2
R876
16
CTF_PWROFF_B 1 2 UNNAMED_14_CAP_I165_A
MR677
IN
3

0R C848
1

0.1uF R838 20K

10V
2 1 1 UNNAMED_14_NPN_I174_B
Q1
5.1K MVDD_EN
R886 MMBT3904 12
OUT
2

1
1

1K UNNAMED_14_CAP_I170_A
2

C839
2

0.1uF
10V
PSEQ_N3
2

R875
1 2 15
3

(0
0R
R874
1 2 +1.8V_EN 1

裴
15 14 +12V_BUS Q842
0R MMBT3904 +12V_BUS
16 15 14 13 12 9 1 +12V_BUS
2

MVDD_VID_FB
OUT 12

+3.3V_BUS
2

+VDDC 1

00 RM 亮
R843 R834 +3.3V_BUS
5.1K
9.1K
1

1
PSEQ_MVDD_EN
12
R846 OUT
DNI
PWR_ENABLE# 2 1 R751
2

1
5.1K 10.5K +0.95V_FB
R841 R842 R752 11
OUT
R835 R710

2
3

5.1K 5.1K 10K 10.5K

1
3.3K

11 A工 樂
402
1

2
3

RFB2
C Q840
UNNAMED_14_MOSN_I414_D
R830 C

3
VDDC_PWR_GOOD 1 2 1 UNNAMED_14_MOSN_I190_G 2N7002E Q1601 52.3K
13 R1693
IN 1K 402
3160169200G 0.955V

2
RFB2
1 Q755 3160174200G 0.945V
2

GPIO_21_MVDD_VID 2N7002E
VVVV301-01S_me 6 1
IN
1

D03-7002E49-O05
2

C841

2
2
1uF

60
6.3V MR752
2

)
10K

1
1) 程
課 BACO
VDDC_EN
OUT 15,13

D D
3 VDDC_EN

R1027 10K
2,16,17
PX_EN 1 UNNAMED_14_NPN_I216_B
Q1014
IN MMBT3904
1

C1031 R1030
1uF 10K
6.3V
DNI
2

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom PWR MGMT & SEQ 1.1

Date: Tuesday, August 06, 2013 Sheet 15 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

Fan Control (New)

Mechanical and Thermal Management

00 M
2-WIRE FAN
4-WIRE FAN +3.3V_BUS
+3.3V_BUS

1
+1.8V

0
R237
2K
1.風扇直接灌12V
14 10 9 2 +1.8V 上件(R253 B201 )

RD 17 SI
U1M +12V_BUS

1
R250 不上件(R249 R4510)
<BOMOPTION>

2
AJ32 TSVDD DPLUS AF29 GPU_DPLUS
17
VVVV301-01S_me R206 RES1005 1 2 2.用公版PWM線路
OUT 5.1K

1
R11-0512012-W08 VVVV301-01S_me
XXXV301-01S_me 上件( R250 B201 R253 Q4507)
不上件(R249 R4510 B200 R251 U203)

3
C4020 C4004 R4102 RES1005 0OHM
AJ33 AG29

2
1uF TSVSS DMINUS 0.0022uF 1K 1 R234 21K 1 N36370229
Q201 3.用NVT3943線路
A 6.3V 50V
GPU_DMINUS VVVV301-01S_me 上件(R249 R251 B200) A
+3.3V_BUS 17 MMBT3904
AK32 OUT 不上件(R250 R253 B201 R4510 )

2
GPIO_28_FDO R11-0102032-W08
15 +3.3V_BUS SOT23_3PIN

2
9 8 1 +3.3V_BUS 9 8 1 +3.3V_BUS RES1005 VVVV301-01S_me
14 11 17 16 15 14 11 D02-0390429-D07
Oland M2 DDR3

(C 96 C
17 16
PWM_B

1
DNI
R4104 R4100
2.61K 20K

3
2

2
TS_FDO01 R4101
2 1 Q4100 VOUT_FAN
1.2K

1
)2 7 ON
MMBT3904
DNI

2
1
R4409
20K
MR4104
10K
Q4510

3
2

1
1 UNNAMED_15_RES_I299_A
R4500 20K 2 1 UNNAMED_15_NPN_I301_B
1 UNNAMED_15_NPN_I317_B R249
DNI DNI +12V_BUS
5% Q4500 U203 3943_VOUT1 2
DNI MMBT3904 MMBT3904
1,2,16
PERST#_BUF 3 D1720 XXXV301-01S_me
IN

2
DNI

F
1 PX_EN 2 8 1 0OHM

0
BAT54S R4514
5% 20K
VIN Vout
If Critical Temperature is reached this will force the fan to run at full 16
speed while power is removed from GPU & rest of the board. 7 2

2
FON# FB

1
R4517 J4001
This is an open collector signal. Active level is hard pull down to ground.
1 2
20K PWMOUT_J 1
DNI

吳 14 jo ID
5% C236 FANOUT_P 6 3 GPIO_6_J 2
10uF_16V SD# PWMOUT

1
MALE
PX_EN
2 15 16 17 16V R232 10uF 3 2.0MM
VVVV301-01S_me 5 4 0OHM C238 4 N/A

2
0805 DCIN PWMIN 13.3K 5% TOWS_TIN_con_wafer232
DCIN 16V

GND
3
DNI
Critial Temperature Fault R208 VVVV301-01S_meVVVV301-01S_me

2
2R4057 1K 1 PWM_ENB 1 Q4011 1 2 R11-0000013-Y01
0805
MMBT3904 100K NCT3943S VVVV301-01S_me 0603 _

9
1

1
DNI C4402 1 R207 2 R11-1332T13-W08

2
1 2 VVVV301-01S_me C237 0603 1 R215 2 5%
N32-1040801-H06

積 01 ne EN
R4062 R4063
0R 0.1uF 100K R11-0104043-R01
16V 16V 0.1uF 4.99K
Critial Temperature Fault 0603 VVVV301-01S_me 0603

2
0603 PSOP8_T118X87 VVVV301-01S_me
R11-4991T13-Y01
+3.3V_BUS
B 17 16 15 14 11 9 8 1 +3.3V_BUS PWMIN B
1

源 23 pe TI
R4411 R4407
10K 20K +12V_BUS
Place close to its CTLR +3.3V_BUS
2

DNI
BACO
2

MMBT3906
Q4400 1 CTF2_GAT

CTF2: R4051=20K, R4053 DNI, C4401=0.1UF;

CTF_PWROFF_B
OUT 15

1
3

3
B201 B200
220R 220R
CTF_BYPASS 16 17 CTF_BYPASS 2 1
R4051
CTF_PWROFF 1 Q4010

01 i( AL
1K MMBT3904

2
1

1
VVVV301-01S_me VVVV301-01S_me

2
R4404 R4405 C4401 R4053
L02-2218024-M09 L02-2218024-M09
2

20K 20K 0.1uF 100K RES1608_2012_1_1H RES1608_2012_1_1H

16V
R4408
2

2
1K

C4009
1

UNNAMED_15_NPN_I128_C 1uF
16V
3

CTF2_RESET

2
(0
6
GPIO_19_CTF 1 R4400 47K
2 47K
2 R4402
1 1 Q4401
_
IN R4508 20K
1

裴
MMBT3904 R4510
AO3415L 0R
Q4507
2
1

5%
UNNAMED_15_CAP_I127_A
use NCT3943 baco
_
R4403 C4400
3 100K 0.01uF
D4400

3
10V
X
2

BAT54S R251

00 RM 亮
_ 1 2 FANOUT_P
2

VVVV301-01S_me
R4507 0OHM
PERST#_BUF 20K R253
16 2 1 5%
1 2 VOUT_FAN
XXXV301-01S_me
0OHM
_

11 A工 樂
+12V_BUS
C C

3
CTF_BYPASS R4506 1
20K
Q4506
5% R4004
MMBT3904 10K
_

2
_
BACO

3
60
+3.3V_BUS +3.3V_BUS Q4505
R4505 20K 1
OUT

1
MMBT3904 6

)
5% DNI
_ +
C4505

2
1
100uF _ GPIO_6 GPIO_6_J

程
10V R4005
1

8
7
1K
For HDMI Connector DNI C4500

2
R4512 U4500
ASSY-SCREW203 2,15,16,17
PX_EN 1 2 R4502 0.1uF X
IN 1K 100K 2 5

PR
Vcc
D Q
2

5%

3
+12V_BUS
R4006

1)
2

R4504 Q4504 3.83K

20K 1
MMBT3904
1 3 1
R4509 2
1M 5%
SCREW

7020003300G C Q
1

CL
5%
R4516

G
DNI _

2
5%

課
Q4503
NC7SZ74K8X _
1 UNNAMED_15_NPN_I269_B
R4503 C4507
4
6

1
MMBT3904

33K
20K

UNNAMED_15_CAP_I277_A
For DVI Connector 0.1uF
2

5%
C4502
2

2
3

10uF
6.3V
R4515 100K
1,2,16
PERST#_BUF 1 2 1
IN

2
1

MMBT3904

ASSY-SCREW200 ASSY-SCREW201 UNNAMED_15_CAP_I344_A

C4506 Q4509
2

1uF
16V
3

Q4508
2

UNNAMED_15_MOSN_I312_G 1 2N7002E

7020000800G 7020000800G
2

Rectangular Heatsink 8W

Bracket Components

MT200

D D
ASSY-SCREW202
SCREW

1 8 SK1
8020051500G 80200515A0G
2
3
4
5
6
7

BK1 BK2
MOUNTING_8PINS_1 7020001700G
620NOPN029
BRACKET BRACKET

MICRO-STAR INT'L CO.,LTD

PCB1
AMD
PCB
MS-V301
Oland soclet 6090034500G MSI
PCB(109-C662xx-00A) Size Document Description Rev
Custom Mech/Thermal Management 1.1

Date: Tuesday, August 06, 2013 Sheet 16 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
A

0
RD 17 SI A

(C 96 C
(19) Debug Circuits

)2 7 ON
FM1 FM4
FM2 FM6
XXXV302-01S XXXV302-01S
+3.3V_BUS
APPLY APPLY XXXV302-01S XXXV302-01S
APPLY APPLY
JTAG
+3.3V_BUS
OPT OPT
U1N OPT OPT

0 F
FM5 FM8

1
TESTEN AD28 TESTEN
17 F_PAD_X F_PAD_X
AM23 JTAG_TRSTB FM7 FM9
JTAG_TRSTB 17 R436 F_PAD_X F_PAD_X
AK23 1K XXXV302-01S XXXV302-01S
JTAG_TCK 17
DNI

吳 14 jo ID
JTAG_TDI AN23 17
APPLY APPLY XXXV302-01S XXXV302-01S

2
JTAG_TDO AM24 17
TESTEN APPLY APPLY
JTAG_TMS AL24 17 OPT OPT

1
OPT OPT
Oland M2 DDR3 R437
1K
F_PAD_X F_PAD_X
F_PAD_X F_PAD_X

2
B

積 01 ne EN JTAG_TRSTB
2 R38 1
1K
+3.3V_BUS
B

源 23 pe TI
1
R39
1K
DNI
JTAG_TRSTB

2
engineering board pull high
production board pull down J11 J12 J13 J14
3 1 3 1

01 i( AL
4 2 4 2
X_PIN1*2 X_PIN1*2 impedence impedence

GND GND GND GND

GND GND
TOP BOT TOP BOT
LM96163 FOR BACKUP THERMAL CONTROL MEM DATA Signal end MEM ADD Signal end Diffenential_Memory Clock PEX_PCIE Signal
MEM to GPU :0.13mm/ 45ohm MEM to GPU :0.102mm/ 50ohm trace width=0.13mm / 80ohm trace width=0.11mm / 85ohm

(0
Air Gap：0.19mm Air Gap：0.14mm

裴
J15 J16

X_PIN1*2 X_PIN1*2
7121000100G

00 RM 亮
GND GND
7120781200G
VERDE_XT_FANSINK TOP TOP
VERDE_XT_FANSINK VERDE_XT_FANSINK VERDE_XT_FANSINK HS5D HS2A
HS1B HS2C HS3D HS3B HS5C HS4D RGB Signal end MEM ADD Signal end
D-SUB to GPU :0.179mm/ 37.5ohm MEM to GPU :0.2mm/ 35ohm

11 A工 樂
C C
25 32
9 16 17 24 25 32 9 17 16 25 24 32
26
27
28
29
30
31
10
11
12
13
14
15

18
19
20
21
22
23

26
27
28
29
30
31

10
11
12
13
14
15

18
19
20
21
22
23

26
27
28
29
30
31
1
2
3
4
5
6
7
8

60 程 )
LED GREEN "ON" shows PX_EN

1) 課
D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom Debug Circuit 1.1

Date: Tuesday, August 06, 2013 Sheet 17 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
A

0
RD 17 SI A

(C 96 C
MVDD SOURCE
1.5A
1.5V@10A

DVI-I HPD2 DDC/AUX1

)2 7 ON
HDMI/DP HPD1 DDC/AUX2
12V_BUS

5.5A

0
吳 14 jo ID F
B

積 01 ne EN VDDC PHASE1 SOURCE

2A
VDDC@20A
B

源 23 pe TI VDDC PHASE2 SOURCE

01 i( AL
2A VDDC@20A
GPIO15 VDDC_VID0

GPIO20 VDDC_VID1

GPIO29 VDDC_VID2

(0 裴
GPIO30 VDDC_VID3
FAN

0.5A
GPIO21 MVDD_VID

00 RM 亮
11 A工 樂
C C

0.95V SOURCE 0.95V@2A

1.5A

60 程 )
1) 課
3.3V_BUS

3A
1.8V_LDO

0.5A 1.8V@0.5A

3.3V@60mA

D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom GPIO DDC HPD map 1.1

Date: Tuesday, August 06, 2013 Sheet 18 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
0
MEMORY CHANNEL A & B

RD 17 SI
Debug
GDDR5 8pcs 128Mx16 (2GB)

A A

(C 96 C
)2 7 ON CH A&B

POWER REGULATORS

From +12V
0
吳 14 jo ID F JTAG/I2C
GPIO

積 01 ne EN
OPTIONAL
+VDDC RGB Filters

+MVDD sVGA

FAN
DDC1

B From +12V LINEAR:

B
ROM

源 23 pe TI
Straps
+5V_VESA, +5V_VESA2

From +12V_BUS SL TMDS HDMI

TMDP-A AC Coupling Caps Connector

+5V BIOS

01 i( AL
From +3.3V_BUS converter(+0.95V):
5V_VESA
Thermal

PCIE_VDDC, DPLL_VDDC, DDC AUXDDC2

Speed control
DPx_VDD10, SPV10, MEM_VREF
DisplayPort
GPIO17
& temperature
INTERRUPT HPD2 Connector

OPTIONAL
From +3.3V Direct:

(0
sense D+/D-

FAN

裴
Temp. Sensing
VDDR3, AVDD

TS_FDO
Built-in PWM

From 3.3V Linear (1.8V)

Overlap

00 RM 亮
PCIE_PVDD, PCIE_VDDR, VDDR4,

Dynamic Power Management

DPLL_PVDD, SPV18, MPV18, DL TMDS

VDD1DI, VDD2DI, AVDD, AVDDQ, AC Coupling Caps

TMDPB sL DVI-I

DPx_PVDD, DPx_VDD18, VDD_CT,

POWER DELIVERY

11 A工 樂
TSVDD

C DACVGA Connector
C
RGB Filters

Oland AUXDDC1

HPD4 5V_VESA

60 )
100MHz

XO_IN2

程
27MHz

XO_IN Clock

Temperature Critical
CTF XTALIN

1)
PCI-Expressx8 27MHz Xtal
Power Sequencing

課
Circuit

Oland DDR3 2GB

+3.3V_BUS
HDMI/DP sLDVI-I/VGA
+12V_BUS

PCI-Express x8 Bus

D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom BLOCK DIAGRAM 1.1

Date: Tuesday, August 06, 2013 Sheet 19 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

TITLE

Oland xto DDR3 2GB SL_DVI-I+HDMI/DP+sVGA

00 M
SCHEMATIC NO.

105-C662XX-00
DATE

0
RD 17 SI
NOTE: REV
THIS SCHEMATIC REPRESENTS THE PCB, IT DOES NOT REPRESENT ANY SPECIFIC SKU.
REVISION HISTORY
FOR STUFFING OPTIONS (COMPONENT VALUES, DNI PLEASE CONSULT THE PRODUCT SPECIFIC BOM.

PLEASE CONTACT AMD REPRESENTATIVE TO OBTAIN LASTEST BOM CLOSEST TO THE APPLICATION DESIRED. P00

A A
SCH PCB
DATE REVISION DESCRIPTION
REV REV

(C 96 C
00 00A 2012/08/20

Initial Oland XT schematic based on C552 C550&C469

)2 7 ON
00 00 2013/03/27 Upgrade PCB to 00 without Schematic change

0 F
01

2013/07/02 1. Page 03~05 : Add <> in memory DQA_

2. Page 07: chagne connector to black type
3. Page 08: remove DP & add ESD
4. Page 09 : add ESD

吳 14 jo ID
5. Page 11 : U801 change to UP1706
6. Page 12 : U701 change to UP1741P
7. Page 13 : U601 change to UP1610
8. Page 15 : add MVDD_EN circuit , add SCL SDA pull high R
9. Page 16 : add NCT3943 in FAN control

積 01 ne EN B

源 23 pe TI
01 i( AL
(0 裴
00 RM 亮
11 A工 樂
C C

60 程 )
1) 課
D D

MICRO-STAR INT'L CO.,LTD

MS-V301
MSI
Size Document Description Rev
Custom History 1.1

Date: Tuesday, August 06, 2013 Sheet 20 of 20

1 2 3 4 5 6 7 8