Counter

module counter(

input clk,

input rst,

output reg [4:0] count

);

always@(posedge clk)

begin

if(rst)

count<=0;

else

count<=count+1;

end

endmodule

Counter test

module counter_test;

reg clk;

reg rst;

wire[4:0]count;

counter uut(

.clk(clk),

.rst(rst),

.count(count)

);
always #5 clk=~clk;

initial begin

clk<=0;

rst<=1;

#10 rst<=0;

#200 rst<=1;

#20 $finish;

end

endmodule

SR FLIP FLOP

module SR(

input s,

input r,

input c,

output reg q,

output reg qb

);

always@(posedge c)

begin

if(s==0&&r==0)

begin
 q=q;qb=qb;

end

else if(s==0&&r==1)

begin

q=0;qb=1;

end

else if(s==1&&r==0)

begin

q=1;qb=0;

end

else if(s==1&&r==1)

begin

q=1;qb=1;

end

end

endmodule

TEST

module SR_test;

reg s;

reg r;

reg c;

wire q;

wire qb;
SR uut(s,r,c,q,qb);

initial

begin

c=0;

forever #10 c=~c;

end

initial

begin

s=1;r=0;

#100 s=0;r=0;

#100 s=0;r=1;

#100 s=1;r=1;

#100 $finish;

end

endmodule

JK FF

module JK(

input J,

input K,

output reg Q,

output reg QB,

input C

);
always@(posedge C)

begin

if(J==0&&K==0)

begin

Q=Q;QB=QB;

end

else if(J==0&&K==1)

begin

Q=0;QB=1;

end

else if(J==1&&K==0)

begin

Q=1;QB=0;

end

else if(J==1&&K==1)

begin

Q=~Q;QB=~QB;

end

end

endmodule

TEST
module JK_test;

reg J;

reg K;

wire Q;

wire QB;

reg C;

JK uut(J,K,Q,QB,C);

initial

begin

C=0;

forever #10 C=~C;

end

initial

begin

J=1;K=0;

#100 J=0;K=0;

#100 J=0;K=1;

#100 J=1;K=1;

#100 $finish;

end

endmodule

D FF
module D(

input D,

input C,

output reg Q,

output reg QB

);

always@(posedge C)

begin

if(D==0)

begin

Q=0;QB=1;

end

else if(D==1)

begin

Q=1;QB=0;

end

end

endmodule

TEST

module D_test;

reg D;

reg C;

wire Q;

wire QB;
D uut(D,C,Q,QB);

initial

begin

C=0;

forever #10 C=~C;

end

initial

begin

D=1;

#100 D=0;

#100 $finish;

end

endmodule