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IRL640A
IRL640A
FEATURES
BVDSS = 200 V
♦ Logic-Level Gate Drive
♦ Avalanche Rugged Technology
RDS(on) = 0.18Ω
♦ Rugged Gate Oxide Technology ID = 18 A
♦ Lower Input Capacitance
♦ Improved Gate Charge
♦ Extended Safe Operating Area
TO-220
♦ Lower Leakage Current: 10µA (Max.) @ VDS = 200V
♦ Lower RDS(ON): 0.145Ω (Typ.) 1
2
3
Thermal Resistance
Symbol Characteristic Typ. Max. Units
RθJC Junction-to-Case -- 1.14
RθCS Case-to-Sink 0.5 -- °C/W
RθJA Junction-to-Ambient -- 62.5
Rev. B
1
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IRL640A 32:(5 026)(7
Notes;
(1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature
(2) L=0.3mH, IAS=18A, VDD=50V, RG=27Ω, Starting TJ =25°C
(3) ISD ≤ 18A, di/dt ≤ 260A/µs, VDD ≤ BV DSS , Starting TJ =25°C
(4) Pulse Test: Pulse Width = 250µs, Duty Cycle ≤ 2%
(5) Essentially Independent of Operating Temperature
2
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32:(5 026)(7 IRL640A
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
V
GS
Top : 7.0 V
6.0 V
5.5 V
5.0 V
4.5 V 101
1 4.0 V
10
3.5 V
150 oC
Bottom : 3.0 V
100
25 oC @ Notes :
1. VGS = 0 V
@ Notes : 2. VDS = 40 V
100 1. 250 µs Pulse Test - 55 oC 3. 250 µs Pulse Test
2. TC = 25 oC
10-1
10-1 100 101 0 2 4 6 8 10
VDS , Drain-Source Voltage [V] VGS , Gate-Source Voltage [V]
Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward Voltage
0.4
IDR , Reverse Drain Current [A]
Drain-Source On-Resistance
0.3 V =5V
GS 101
RDS(on) , [ Ω ]
0.2
100
0.1
VGS = 10 V @ Notes :
150 oC 1. VGS = 0 V
o 2. 250 µs Pulse Test
@ Note : TJ = 25 C 25 oC
0.0 10-1
0 20 40 60 80 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
I , Drain Current [A] VSD , Source-Drain Voltage [V]
D
Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage
2000
Ciss= Cgs+ Cgd ( Cds= shorted )
Coss= Cds+ Cgd 6
C iss
1600 Crss= Cgd VDS = 40 V
VGS , Gate-Source Voltage [V]
VDS = 100 V
Capacitance [pF]
800 C oss
@ Notes :
1. VGS = 0 V
2. f = 1 MHz 2
C rss
400
@ Notes : ID = 18 A
0 0
100 101 0 10 20 30 40
VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC]
3
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IRL640A 32:(5 026)(7
Drain-Source On-Resistance
RDS(on) , (Normalized)
1.1 1.5
BVDSS , (Normalized)
1.0 1.0
0.8 0.0
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
T , Junction Temperature [oC] TJ , Junction Temperature [oC]
J
Fig 9. Max. Safe Operating Area Fig 10. Max. Drain Current vs. Case Temperature
20
Operation in This Area
is Limited by R DS(on)
102
ID , Drain Current [A]
@ Notes :
100 1. T = 25 oC 5
C
2. TJ = 150 oC
3. Single Pulse
10-1 0 0
10 101 102 25 50 75 100 125 150
V , Drain-Source Voltage [V] T , Case Temperature [oC]
DS c
100
D=0.5
@ Notes :
0.2 1. Z J C (t)=1.14 o C/W Max.
θ
0.02 t1
0.01 t2
θJC
single pulse
10- 2 - 5
10 10- 4 10- 3 10- 2 10- 1 100 101
t , Square Wave Pulse Duration [sec]
1
4
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32:(5 026)(7 IRL640A
Fig 12. Gate Charge Test Circuit & Waveform
Current Regulator
VGS
Same Type
50kΩ as DUT Qg
12V 200nF
300nF 5V
VDS
VGS Qgs Qgd
DUT
3mA
R1 R2
RL
Vout Vout
90%
Vin VDD
( 0.5 rated VDS )
RG
DUT 10%
Vin
5V
td(on) tr td(off)
tf
t on t off
RG C VDD ID (t)
DUT
VDD VDS (t)
5V
tp tp Time
5
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Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT +
VDS
--
IS
L
Driver
VGS
RG Same Type
as DUT VDD
IRM
Vf VDD
Body Diode
Forward Voltage Drop
6
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Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
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