Integrating Aging Aware Timing Analysis into PrimeTime

Shushanik Karapetyan and Ulf Schlichtmann

Technische Universität München

Munich, Germany

www.tum.de

ABSTRACT

Continuous scaling of transistor sizes to achieve low dynamic power, less area, and more speed have
worsened the aging effects. Two dominant contributors affecting the transistor aging are Negative Bias
Temperature Instability (NBTI) and Hot-Carrier-Injection (HCI). Both of these mechanisms negatively
impact the timing behavior of circuits. Traditionally, aging analysis has not been a part of the established
circuit design flow. However, as the impact of aging effects increases, the necessity of their consideration
in the design flow grows.
Various device and gate level models have been developed to explore and study aging effects. However,
commercial tools do not yet support aging analysis at the gate level, therefore aging analysis is not
commonly available to industrial designers. This paper presents an automated methodology for fast and
accurate NBTI and HCI aware timing analysis. The approach utilizes the AgeGate aging aware gate
model and integrates it into a commercial static timing analysis (STA) tool (PrimeTime - Synopsys).
The paper presents results obtained from applying the method to various benchmark circuits. These
results demonstrate that aging is an important phenomenon which needs consideration in timing analysis
and can be easily analyzed using commercial tools.
Table of Contents
1. Introduction ........................................................................................................................... 3
2. Aging-aware STA flow ......................................................................................................... 4
3. Results ................................................................................................................................... 8
4. Conclusions ......................................................................................................................... 10
5. References ........................................................................................................................... 10

Table of Figures
Figure 2.a ASTA flow incorporated into PrimeTime ..................................................................... 4
Figure 2.b: 2-input NOR gate ......................................................................................................... 7
Figure 3.a Critical path of non-aged c5315 benchmark circuit ...................................................... 9
Figure 3.b: Changed critical path of aged c5315 benchmark circuit .............................................. 9

Table of Tables
Table 1: Critical path delay degradation of different ISCAS’85 benchmark circuits considering
NBTI, HCI or BOTH effects together. The run time of the analysis for both effects is given as
well .................................................................................................................................................. 8

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1. Introduction
With the continuous shrinking of transistor sizes, reliability issues have become a major concern in
current very large scale integrated (VLSI) circuits. Process variations combined with the aging effects
present a major challenge in ensuring correct functionality of modern circuit designs. These issues
increase the overall circuit cost and may also prohibit the further downscaling of transistor sizes.
Currently, two dominant aging effects are Negative Bias Temperature Instability (NBTI) and Hot Carrier
Injection (HCI) [1],[4],[9]. NBTI can be observed only in PMOS transistors. It occurs when the gate
terminal of the transistor is negatively biased with respect to the source and drain terminals. This causes
an increase in the threshold voltage (Vth) that can lead to a significant degradation in the circuit's
performance [2]. On the other hand, HCI affects both PMOS and NMOS transistors. The phenomenon
causes charge carriers (electrons and holes) to be trapped in the gate dielectric. In turn, the drain current
of both PMOS and NMOS can degrade and can negatively impact circuit's timing.

Multiple gate level models have been created to assess the impact of these aging effects on transistor
performance. However, the main drawback of these models is that the majority of them (e.g. [14], [16])
account for only single aging mechanism.

During the design of digital circuits one step that is repeated multiple times throughout the design
flow is timing analysis (TA). The main task of TA is to assess the timing characteristics of the design and
ensure that it meets the timing constraints. Historically, to account for aging effects and variations, the
common practice was to apply safety margins to the design. However, with the significant increase of the
impact of aging mechanisms on circuit performance this is no longer practical. If these guardbands are too
pessimistic, this will lead to wasted performance of the circuit. On the other hand, the underestimation of
the safety margins is even worse. It may lead to circuit failure before the end of the specified lifetime.
Commercially available reliability simulators (e.g. CustomSim -Synopsys [7]) are capable of analyzing
the impact of aging effects on device parameters. These transistor-level simulators can be very accurate,
however they are very time consuming and require realistic input vectors for simulations. There has also
work been done to account for NBTI and other aging effects in Statistical STA (SSTA) [11], [6], [3]. The
authors of [6] present a Statistical STA framework considering NBTI and process variations. The work is
based on a stochastic gate model which predicts the degraded gate delay distribution due to NBTI and
process variations. After updating mean and the variance of the gate delay distribution in the Statistical
Standard Cell Library, Statistical STA is performed.

The SSTA method used in [3] to evaluate NBTI impact on circuits is based on the linear sensitivity
analysis. The authors claim that due to the non-Gaussian behavior of the NBTI effects, for some circuit
topologies, the utilization of standard SSTA tools may lead to misleading results. The authors of [5] have
presented a framework to incorporate workload dependent runtime variations into the timing analysis.
The framework is built on top of commercial EDA tool and scales well with circuit sizes. However, it
considers only the impact of NBTI, but not HCI. The work is based on a Lookup Table (LUT) approach,
where the delay and the output slope of the gate are also functions of the Vth shift. Later in the flow the
netlist of the design is modified to map each cell to a newly generated library element to capture the
impact of process variation and NBTI.

In this paper, we propose a methodology to incorporate aging aware timing analysis considering
either a single aging mechanism (NBTI, HCI) or both together into a timing analysis engine (PT-
Synopsys).

The key differences in our approach as compared to the state of the art aging-aware timing methods
are:

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 1. For the calculation of aging induced performance degradation the proposed method does not
require information about the system-level workload, but can work with reasonable
assumptions about activity at the primary inputs if workload information is not available.
Workload is defined by the portion of the lifetime a device is under a particular operating
condition.
2. It considers impact of both NBTI and HCI effects.
3. The AgeGate model used in our work [12] is based on traditional two-dimensional LUTs,
therefore it can be used by an already existing analysis flow.
4. No modification of the design netlist is required.
5. The structure of the implemented algorithm is flexible, so in the future more aging effects can
easily be integrated into it.

The rest of the paper is organized as follows: in Section 2 the aging aware STA flow is presented.
Results of the analyses are presented in Section 3. Finally, the work is concluded in Section 3.

2. Aging-aware STA flow

In this section, we present our methodology to integrate aging aware static timing analysis (ASTA) of
digital circuits into the existing circuit design flow. The overview of the ASTA flow integrated into a
commercial framework is presented in Figure 2.a.

The proposed approach allows to accurately determine the impact of two dominant aging effects,
NBTI and HCI, at the gate-level. To capture the performance degradation during ASTA we utilize the
AgeGate model [12, 13]. AgeGate is a canonical gate model which provides the aged gate delay
considering the parameter drifts of each individual transistor. The model is reviewed in more detail in the
next subsection. As originally presented, the model however was not integrated into efficient commercial
STA tools, therefore it could not be used in industrial IC design so far. The main goal of this work is to
integrate the aging aware timing analysis into a commercially available STA tool.

Figure 2.a ASTA flow incorporated into PrimeTime

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 Not only does this allow us to fully integrate the aging analysis into an existing design flow, but it
also allows us to make use of the features provided by commercial EDA tools for further analysis at no
additional cost. To achieve an efficient and detailed integration into a commercial STA tool, the approach
described in [13] had to be enhanced. Specifically, the approach for processing each gate in the design for
aged performance calculation required principal changes for efficient integration into Synopsys
PrimeTime.

Here, we briefly review the AgeGate model and then introduce the proposed ASTA flow using
PrimeTime.

The AgeGate model used in this approach is an aging-aware gate model. It allows to calculate the
delay degradation of a logic gate caused by NBTI and/or HCI. The model consists of the following three
fundamental parts:

 A canonical gate model

 Degradation equations
 Structural information of the logic gate

The canonical gate model computes the degraded performance of the logic gate due to parameter
drifts of the individual transistors caused by a specific aging mechanism. The transistor parameter drifts
due to NBTI and HCI are calculated by technology specific degradation equations.

The canonical gate model corresponds to a first-order Taylor approximation at the nominal gate
performance

∑∑

The aged gate performance ( ) represents the sum of non-aged gate performance ( )
and the performance degradation. G is the set of all transistors in the gate and P is the set of all transistor
parameters that are affected by aging. and are the sensitivity coefficients and the drifts of
parameter p of transistor m, respectively.
For our case, the performance of interest is the delay of the logic gate. Transistor parameter drifts due
to NBTI and HCI will be and respectively.

Equation (1) can be rewritten in the following way:

Together with the non-aged delay of the cell, the sensitivity coefficients and are obtained
during library characterization. The sensitivities are dependent on input slope and output load of a logic
gate. Similar to the gate delay they are stored in Lookup Tables (LUT) for various combinations of input
slope and output load.

The advantage of this method is that it is the sensitivity of the performance with respect to the
parameter drift that is characterized during the library characterization and not the parameter drift itself.

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Since the parameter drift is strongly dependent on the use profile and the workload, it is calculated on the
fly during the ASTA. This eliminates the need for re-characterizing the library for every use profile and
workload combination.

Workload Determination

The ASTA flow is quite similar to the traditional STA flow. The difference is that during the ASTA
the delay of the aged gate is considered instead of the non-aged one. This is done by adding the increased
cell delay caused by aging mechanisms to the non-aged delay of the cell.

During the operation of the circuit the voltage levels at the nodes of the transistors change constantly.
Not all of these combinations contribute to aging of the transistors. For example, for a PMOS transistor to
degrade due to NBTI, the gate terminal shall be negatively biased with respect to the source and drain
[10]. The parameter drift of a transistor is strongly dependent on the time the transistor is under stress.
Hence, it is crucial to determine the fraction of time that the transistor will be stressed under a specific
aging effect during its lifetime. First, the workloads for all nets in the design have to be obtained. For this
purpose, a system-level workload profile, if available, can be utilized. Alternatively, Signal Probability
(SP) and Transition Density (TD) with reasonable assumptions can be applied to the primary inputs and
be propagated throughout the circuit to its primary outputs. SP defines the average number of clock
periods a signal is at logic "1", whereas TD is determined by the average number of the signal transitions
between low and high logic levels per clock cycle [15]. This information is later required for obtaining the
effective NBTI and HCI stress times.

The first step in the flow is to obtain SP and TD for all gate inputs in a circuit. For this purpose, it is
sufficient to have only SP and TD at the primary inputs of a circuit. The SP and TD are applied to the
primary inputs of the design with “set_switching_activity” command. To obtain signal probabilities for
all internal nets of a design the SP and TD are propagated with “propagate_switching_activity”
command. We used Synopsys Design Compiler [8] to propagate SP and TD throughout the circuit to its
primary outputs. Same information can be obtained from PrimeTime PX which supports switching
activity propagation.

Obtaining Effective Stress Time

After SP and TD have been obtained, the next step in the flow is to calculate the effective NBTI and
HCI stress times of all transistors in the circuit. The stress time ( ) is determined by the following
equation:

(3)

where is the defined lifetime of the circuit and is the probability that a transistor is
stressed due to a specific aging effect. To calculate the individual cell information has to be
extracted from Design Compiler. This information includes: cell type, SP and TD, transition time, and
output load. As mentioned above, shall PrimeTime be preferred the exact same information can be
obtained from PrimeTime PX. In order to accurately calculate the effective stress probability of a
particular aging effect, information about the internal structure of a logic gate is also required. The reason
for this is that depending on their position in a logic cell two transistors with equal signal probabilities
may have different stress probabilities.

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 To clarify this, let us consider the following example of a 2-input NOR cell in Figure 2.b. In order
for the transistor to degrade due to NBTI, input A has to be logic "0". Hence, the NBTI stress
probability will be

MP1)=1-SP(MP1) (4)

On the other hand, the transistor will degrade due to NBTI only when both input B and input A
are at logic "0". Thus, the effective NBTI stress probability of transistor will be calculated by the
following equation:
MP2)=(1-SP(MP1)) (1-SP(MP2) (5)

We have created a dictionary to calculate effective stress probabilities of individual transistors in a

logic gate. The dictionary contains equations to calculate and for each transistor
based on the type of the logic gate. The creation of such a dictionary is a one-time effort that eliminates
the necessity of internal structure analysis of a logic gate during each run of the ASTA. This significantly
decreases the runtime of the analysis. Moreover, the dictionary can always be enhanced by new types of
logic cells.

Parameter Drift Calculation

Figure 2.b: 2-input NOR gate

In this step, which is performed outside PrimeTime, the parameter drift of the individual transistors
due to a particular aging effect is calculated. The calculation is done by means of technology specific
degradation equations for NBTI and HCI. The output of the previous step, as well as the use profile
information (supply voltage, temperature, and lifetime) serves as an input to the degradation equations.
Once the parameter drifts are computed, the delay degradation is obtained from the AgeGate model by
combining the information about the parameter drift with the pre-characterized sensitivity coefficients.

Delay Annotation

Finally, in the last step of the ASTA flow the aged performance of the design is determined. The
portion of aging induced delay degradation obtained in the previous step is added to the individual gate
delays of the design. To do this, in PrimeTime the individual gate delays are annotated to consider the
portion of the aging induced delay degradation. The delay annotation is done by individually applying

SNUG 2015 7 Integrating Aging Aware TA into PrimeTime

timing derates to the logic cells in the design. Please note, that no modification of the original design
netlist is required for this task. Finally, these annotated gate delays enable PrimeTime to perform ASTA
considering one or more aging effects.

3. Results
Multiple ISCAS'85 benchmark circuits were used to perform ASTA PrimeTime. An industrial
standard cell library, characterized for the corner case, 27°C temperature (T), supply voltage (VDD) of
0.9V and nominal process ( ) was taken for our analyses. The use profile of the circuit with specified
10 years of lifetime, 125°C effective temperature and effective supply voltage ( ) of 1.32V was
chosen.

Design Non-aged NBTI [%] HCI [%] NBTI+HCI Runtime for Number
delay [ns] [%] both of logic
NBTI+HCI gates
[s]
c880 1.1212 6.12 2.86 8.92 6 383
c1355 1.385 7.33 2.77 10.10 7 546
C1908 1.996 5.75 2.88 8.64 9 880
C2670 2.164 8.80 2.73 11.46 14 1193
C3540 2.66 9.27 2.70 11.90 18 1669
C5315 2.266 8.05 2.91 10.96 29 2307
C6288 5.65 4.88 2.76 7.64 31 2406
C7552 1.736 7.30 2.88 10.18 35 3512

Table 1: Critical path delay degradation of different ISCAS’85 benchmark circuits considering NBTI, HCI
or BOTH effects together. The run time of the analysis for both effects is given as well

The ASTA was performed to analyze the performance degradation of the benchmark circuits caused
by NBTI, HCI or both aging effects together. The results presented in Table 1 show the critical path
delay degradation of different ISCAS'85 benchmark circuits. The critical path delay of the non-aged
circuit is given as a reference. The delay degradation due to NBTI, HCI or both effects together are
expressed in terms of percentage. The overall run time of the ASTA considering both NBTI and HCI
effects is presented as well. The results of the analyses show that NBTI is the dominant aging effect.
However, the impact of HCI on circuit degradation must not be neglected. Based on the analysis results,
the ( ) can reach up to 11.90%.

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 Figure 3.a Critical path of non-aged c5315 benchmark circuit

Figure 3.b: Changed critical path of aged c5315 benchmark circuit

Parameter drift of the transistor is strongly dependent on the workload. During the operating lifetime
of a circuit different signal paths have different workload and aging stress probability, which can cause
some paths in a circuit to age significantly faster than others. This can lead to a critical path change of a
design. Such a case is presented in Figure 3.a. It shows the critical paths of the c5315 benchmark circuit
before (Figure 3.a) and after (Figure 3.b) aging. Because of the integration of aging analysis into a

SNUG 2015 9 Integrating Aging Aware TA into PrimeTime

commercial framework, the corresponding paths are readily visualized to the designer in his regularly
used tools.

In addition to the advantages of ASTA integration into a commercial tool presented above, it is now
possible to utilize already available tool features for further design revision. For instance, information
with regards to the critical path changes after ASTA can be translated into a set of tighter timing
constraints and applied to these paths. Logic optimization, in consideration of these new timing
constraints will lead to an aging-robust design, thus increasing the lifetime of the circuit.

4. Conclusions
In this paper, we have presented a fully automated flow for integration of an aging aware timing
analysis into PrimeTime. This allows to quickly and accurately predict the combined impact of NBTI and
HCI aging mechanisms on the performance degradation of a design. The proposed work is based on the
aging aware logic gate model, AgeGate. Thanks to the full integration into a commercial EDA tool, the
methodology can scale well to real life large circuits. A major advantage of the work is that the flow is
not bound to a specific commercial STA tool. It also enables the usage of already available features of the
tool during the aging analysis. Moreover, the presented method does not require any modification of the
design netlist. Finally, the structure of the flow and the AgeGate model are flexible and can be enhanced
in the future to handle other aging effects, such as Time Dependent Dielectric Breakdown (TDDB).

5. References

[1] M. A. Alam and S. Mahapatra. A comprehensive model of pmos nbti degradation. In

Microelectronics Reliability, volume 45, pages 71–81, Jan 2005.
[2] S. Bhardwaj, Wenping Wang, R. Vattikonda, Yu Cao, and S. Vrudhula. Predictive modeling of
the nbti effect for reliable design. In CICC, pages 189–192, Sept 2006.
[3] Vinicius V. A. Camargo, Ben Kaczer, Gilson I. Wirth, Tibor Grasser, and Guido Groeseneken.
Use of ssta tools for evaluating bti impact on combinational circuits. TVLSI, 22(2):280–285, Feb 2014.
[4] Peng Fang, J. Tao, J.F. Chen, and Chenming Hu. Design in hot-carrier reliability for high
performance logic applications. In CICC, pages 525–531, May 1998.
[5] Farshad Firouzi, Saman Kiamehr, Mehdi Tahoori, and Sani Nassif. Incorporating the impacts
of workload-dependent runtime variations into timing analysis. In DATE, pages 1022–1025, March 2013.
[6] Sangwoo Han and Juho Kim. Nbti-aware statistical timing analysis framework. In SoCC,
pages 158–163, September 2010.
[7] http://www.synopsys.com. CustoSim.
[8] http://www.synopsys.com. Design compiler.
[9] V. Huard, C.R. Parthasarathy, A Bravaix, C. Guerin, and E. Pion. Cmos device design-in
reliability approach in advanced nodes. In IRPS, pages 624–633, April 2009.
[10] S.V. Kumar, C.H. Kim, and S.S. Sapatnekar. An analytical model for negative bias
temperature instability. In ICCAD, pages 493–496, Nov 2006.
[11] S.V. Kumar, C.H. Kim, and S.S. Sapatnekar. Nbti-aware synthesis of digital circuits. In DAC,
pages 370–375, June 2007.
[12] D. Lorenz, M. Barke, and U. Schlichtmann. Aging analysis at gate and macro cell level. In
ICCAD, pages 77–84, Nov 2010.

SNUG 2015 10 Integrating Aging Aware TA into PrimeTime

 [13] D. Lorenz, G. Georgakos, and U. Schlichtmann. Aging analysis of circuit timing considering
nbti and hci. In IOLTS, pages 3–8, June 2009.
[14] Yinghai Lu and Xuan Zeng. Statistical reliability analysis under process variation and aging
effects. In DAC, pages 514–519, 2009.
[15] F.N. Najm. A survey of power estimation techniques in vlsi circuits. TVLSI, 2(4):446–455,
Dec 1994.
[16] Wenping Wang, Shengqi Yang, S. Bhardwaj, S. Vrudhula, F. Liu, and Yu Cao. The impact of
nbti effect on combinational circuit: Modeling, simulation, and analysis. Very Large Scale Integration
(VLSI) Systems, IEEE Transactions on, 18(2):173–183, Feb 2010.
[10]

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