Premier University, Chittagong

EEE-311: Digital Electronics

Implementation of Basic Static Logic Gates in TTL, ECL and CMOS

Dr. Sampad Ghosh

Associate Professor
Department of Electrical and Electronic Engineering
Faculty of Electrical and Computer Engineering
Chittagong University of Engineering and Technology (CUET)

January 18, 2023

CHITTAGONG UNIVERSITY OF ENGINEERING AND TECHNOLOGY (CUET)
KYUSHU UNIVERSITY
 Topics Reference
Implementation of Basic Static Logic Gates in
TTL, ECL and CMOS

Transistor-Transistor Logic (TTL), Emitter-Coupled

Mano
Logic (ECL), Metal-Oxide Semiconductor (MOS),
Complementary MOS (CMOS)

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Logic Family
 Digital IC logic families are:
o RTL (Resistor-transistor logic)
o DTL (Diode-transistor logic)
o IIL/ I2L (Integrated-injection logic)
o TTL/ T2L (Transistor-transistor logic)
o ECL (Emitter-coupled logic)
o MOS (Metal-oxide semiconductor)
o CMOS (Complementary metal-oxide semiconductor)

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Logic Family…
 RTL and DTL have only historical significance
o Rarely used in new designs

 Common characteristics by which digital logic families compared-

1. Fan-out
o Specifies number of standard loads that output of a gate
can drive without degrading its normal operation.
o A standard load is usually defined as the amount of
current needed by an input of another gate in the same IC
family.
o Sometimes the term “loading” is used instead of fan-out.
IOH=400μA IIH=40μA
o Expressed by a number.
Fan-out = IOH/IIH = 10

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Logic Family…
2. Power dissipation
o Power consumed by the gate, which supplied from power supply. Supply VCC = 5V
o Expressed in milliwatts (mW). Avg. ICC = 2mA

o Represents actual power dissipated in the gate. PD=VCC*ICC=10mW

o Total power dissipation in a system = ∑(power dissipated in all ICs).

3. Noise margin
o Maximum noise voltage added to input signal of a
digital circuit that does not cause an undesirable
change in circuit output.
o Expressed in volts (V).
o Represents maximum noise signal that can be
tolerated by the gate.
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Logic Family…
4. Propagation delay
o Average transition delay time for a signal to propagate from input to output when
binary signals change in value.
o Expressed in nanoseconds (ns).
o It depends largely on two factors -
i. Storage time
 Reducing storage time decreases propagation delay.
ii. RC time constants
 Reducing resistors values in circuit reduces RC time constants and decreases
propagation delay.
 Trade-off between power dissipation and propagation delay.
• Lower resistances draw more current from power supply indicates higher power
dissipation. Speed of gate is inversely proportional to propagation delay.

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Transistor-Transistor Logic (TTL)
 TTL gates come in three different types of output configurations:
1. Open-collector output
2. Totem-pole output
3. Three-state or tri-state output

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Open-Collector Output Gate

 Two voltage levels of TTL gate

o Low level = 0.2V
o High level = 2.4V or 5V

Open-collector TTL gate

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Open-Collector Output Gate…

 If any input is low, base-emitter in Q1 forward biased.

 VB of Q1 = I/n voltage + VBE drop = 0.2+0.7=0.9V
 For Q3 to start conducting, path from Q1 to Q3 must
A OFF
OFF OFF Y overcome VBC drop of Q1, VBE drop in Q2 and VBE drop
+5V HIGH
OFF Output in Q3, or 3x0.7=2.1V.
B Q3
ON
+0.2V Q1  Since VB of Q1 is 0.9V, Q3 cannot conduct and is cutoff.
 Output is high if an external resistor is connected
between output and VCC.

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Open-Collector Output Gate…
 Since all inputs are high and greater than 2.4V,
base-emitter of Q1 is reverse-biased.
 If all inputs are high, both Q2 and Q3 conduct
and saturate.
 VB of Q1 = VBC in Q1 + VBE in Q2 + VBE in Q3
A ON = 3x0.7=2.1V.
+5V OFF ON Y  When Q3 saturates, output is low i.e., 0.2V.
ON
Q3 LOW
B Output
+5V OFF Q1

 Confirms NAND operation

 If single emitter use,
performs NOT gate.

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Open-Collector Output Gate…
 Major applications
o Driving a lamp or relay,
o Performing wired logic,
o Construction of common-bus system.

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Open-collector output gate…
 Wired-AND of two open collector gates:

o AND function formed by connecting together two

outputs is called wired-AND function.
o Wired-AND gate is not a physical state but only a
symbol to designate the function obtained from
the indicated connection.
o Boolean function obtained
Y = (AB)’.(CD)’
Physical connection for wired AND of Y = (AB+CD)’
two open collector gates
o Second expression is preferred since it shows
common AND-OR-NOT operation.

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Open-Collector Output Gate…
 Construction of common-bus line:

o Each of four inputs drives OC inverter, and outputs of

inverters tied together to form a single bus line.
o When 3 inputs (I1, I2, I3) are 0, it produces 1 or high
level on the bus.
o Forth input (I4) can now transmit information through
I1, I2, I3 = 0 common bas line into inverter-5.
I4 = 1 • If I4=1, output of OC-4 is 0 and wired-AND produces 0.
Y = I4 • If I4=0, output of OC-4 is 1 and wired-AND produces 1.
o Thus, if all other outputs are maintained at 1,
selected gate can transmit its value through the bus.
Open-collector gates forming
common-bus line

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Totem-pole output gate

Open-collector
TTL gate

 Same arrangement as open-collector

output gates except Q4 and D1.
 Called a totem-pole output because
transistor Q4 ‘sits’ upon Q3.
TTL gate with totem-pole output

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Totem-pole output gate…

 Circuit operation same as open-collector gate

o When all inputs are high, Q3 ON and output LOW
o When any input is low, Q3 OFF and output HIGH.
0.9V
Q4  VC of Q2 = VCE (Q2) + VBE (Q3) = 0.2V + 0.7V
OFF =0.9V
A ON  Output or VY = VCE (Q3) = 0.2V
+5V OFF ON
Y  For Q4 to start conducting, its base must
Q3 ON LOW
B overcome VBE and diode drop, or 2x0.7=1.4V.
Output
+5V  VB of Q4 = VC (Q2) = 0.9V, so Q4 is cutoff.
OFF
 Reason for placing diode (D1) is to provide a
diode drop in output path so that Q4 is cutoff
when Q3 is saturated.

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Totem-pole output gate…
 If any input is low, Q2 and Q3 goes into cutoff
and output changes to high state.
 However, output remains momentarily low
because voltages across load capacitance
ON Q4 cannot change instantaneously.
HIGH  As soon as Q2 turns OFF, Q4 conducts because
Output
A OFF its base is connected to VCC through 1.6kΩ.
+5V OFF OFF
Y  Current needed to charge load capacitance
OFF
B Q3 causes Q4 to momentarily saturate, and output
+0.2V voltage rises with a time constant RC.
ON
o R (R4+RQ4+RD) is much smaller (~150Ω),
transition from low to high level is much faster.
o Final value of output voltage = 5 - VBE (Q4) – VD
(D1) = 5-0.7-0.7 = 3.6V

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