Low Noise, 1 GHz

FastFET Op Amps
Data Sheet ADA4817-1/ADA4817-2
FEATURES CONNECTION DIAGRAMS
High speed ADA4817-1
TOP VIEW
−3 dB bandwidth (G = 1, RL = 100 Ω): 1050 MHz (Not to Scale)

Slew rate: 870 V/µs PD 1 8 +VS

0.1% settling time: 9 ns FB 2 7 OUT

Input bias current: 2 pA typical –IN 3 6 NIC

Input capacitance +IN 4 5 –VS

Common-mode capacitance: 1.3 pF typical

07756-001
NOTES
Differential mode capacitance: 0.1 pF typical 1. NIC = NO INTERNAL CONNECTION.

Low input noise Figure 1. 8-Lead LFCSP (CP-8-13)

Voltage noise: 4 nV/√Hz at 100 kHz ADA4817-1
Current noise: 2.5 fA/√Hz at 100 kHz TOP VIEW
(Not to Scale)
Low distortion: −90 dBc at 10 MHz (G = 1, RL = 1 kΩ)
Linear output current: 40 mA FB 1 8 PD
–IN 2 7 +VS
Supply quiescent current per amplifier: 19 mA typical +IN 3 6 OUT
Powered down supply quiescent current per amplifier: –VS 4 5 NIC
1.5 mA typical

07756-002
NOTES
APPLICATIONS 1. NIC = NO INTERNAL CONNECTION.

Photodiode amplifiers Figure 2. 8-Lead SOIC (RD-8-1)

Data acquisition front ends ADA4817-2
TOP VIEW
Instrumentation (Not to Scale)
Filters

13 OUT1
14 +VS1
15 PD1
16 FB1
ADC drivers
Output buffers
–IN1 1 12 –VS1
+IN1 2 11 NIC
NIC 3 10 +IN2
–VS2 4 9 –IN2
FB2 8
PD2 7
OUT2 5
+VS2 6

07756-003

NOTES
1. NIC = NO INTERNAL CONNECTION.

Figure 3. 16-Lead LFCSP (CP-16-20)

Rev. G Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADA4817-1/ADA4817-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 4
Specifications..................................................................................... 5
±5 V Operation ............................................................................. 5
5 V Operation................................................................................ 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
Maximum Safe Power Dissipation ............................................. 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Test Circuits ..................................................................................... 18
Theory of Operation ...................................................................... 19
Closed-Loop Frequency Response ........................................... 19
Noninverting Closed-Loop Frequency Response .................. 19
Inverting Closed-Loop Frequency Response ............................. 19
Wideband Operation ................................................................. 20
REVISION HISTORY
4/2019—Rev. F to Rev. G
Changes to Features Section............................................................ 1
Updated Outline Dimensions ....................................................... 32
6/2018—Rev. E to Rev. F
Changes to Input Common-Mode Voltage Range, Table 1 ........ 5
Changes to Input Common-Mode Voltage Range, Table 2 ........ 7
1/2018—Rev. D to Rev. E
Changes to Figure 57 ...................................................................... 21
10/2017—Rev. C to Rev. D
Changes to Features Section and Applications Section....................... 1
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 6
Changes to Thermal Resistance Section, Table 4, and Maximum
Safe Power Dissipation Section ....................................................... 8
Changes to Figure 5 .......................................................................... 9
Changes to Figure 7 ........................................................................ 10
Reorganized Typical Performance Characteristics Layout ....... 11
Added Figure 32 through Figure 37; Renumbered Sequentially .... 15
Added Figure 38 through Figure 43 ............................................. 16
Rev. G | Page 2 of 31
Data Sheet
Driving Capacitive Loads .......................................................... 20
Thermal Considerations............................................................ 20
Power-Down Operation ............................................................ 21
Capacitive Feedback................................................................... 21
Higher Frequency Attenuation ................................................. 22
Layout, Grounding, and Bypassing Considerations .................. 23
Signal Routing............................................................................. 23
Power Supply Bypassing ............................................................ 23
Grounding ................................................................................... 23
Exposed Pad ................................................................................ 23
Leakage Currents ........................................................................ 24
Input Capacitance ...................................................................... 24
Input-to-Input/Output Coupling ............................................. 24
Applications Information .............................................................. 25
Low Distortion Pinout ............................................................... 25
Wideband Photodiode Preamp ................................................ 25
High Speed JFET Input Instrumentation Amplifier .............. 27
Active Low-Pass Filter (LPF) .................................................... 28
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 31
Added Figure 44 and Figure 45 .................................................... 17
Changes to Noninverting Closed-Loop Frequency Response
Section, Inverting Closed-Loop Frequency Response Section,
and Figure 54 Caption ................................................................... 19
Changes to Thermal Considerations Section ............................. 20
Added Figure 57 and Figure 58 .................................................... 21
Changes to Power-Down Operation Section and Table 8......... 21
Changed Exposed Paddle Section to Exposed Pad Section...... 23
Changes to Wideband Photodiode Preamp Section.................. 25
Change to Table 9 ........................................................................... 26
Changes to Active Low Pass Filter (LPF) Section ...................... 28
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 31
5/2016—Rev. B to Rev. C
Changed CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 1, Figure 2, and Figure 3 ..................................1
Changes to Figure 5, Table 5, Figure 6, and Table 6 ......................6
Changes to Figure 7 and Table 7 ......................................................7
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
Data Sheet
5/2013—Rev. A to Rev. B
Changes to Figure 3........................................................................... 1
Changes to Figure 7........................................................................... 7
Updated Outline Dimensions ........................................................24
Changes to Ordering Guide ...........................................................25
3/2009—Rev. 0 to Rev. A
Added 8-Lead SOIC Package............................................ Universal
Changes to Features Section and General Description Section .. 1
Changes to Table 1............................................................................. 3
Changes to Table 2............................................................................. 4
Changes to Figure 4........................................................................... 5
Changes to Figure 9, Figure 11, and Figure 12 .............................. 8
Rev. G | Page 3 of 31
ADA4817-1/ADA4817-2
Changes to Figure 21, Figure 22, and Figure 24.......................... 10
Changes to Figure 33 ...................................................................... 12
Added Figure 34; Renumbered Sequentially ............................... 12
Changes to Thermal Considerations Section and Power-Down
Operation Section ........................................................................... 15
Changes to Capacitive Feedback Section and Figure 46............ 16
Added Higher Frequency Attenuation Section, Figure 47,
Figure 48, and Figure 49; Renumbered Sequentially ................. 16
Updated Outline Dimensions........................................................ 24
Changes to Ordering Guide ........................................................... 25
11/2008—Revision 0: Initial Version
ADA4817-1/ADA4817-2
GENERAL DESCRIPTION
The ADA4817-1 (single) and ADA4817-2 (dual) FastFET™ amplifiers
are unity-gain stable, ultrahigh speed, voltage feedback amplifiers
with FET inputs. These amplifiers were developed with the Analog
Devices, Inc., proprietary eXtra fast complementary bipolar
(XFCB) process, which allows the amplifiers to achieve ultralow
noise (4 nV/√Hz; 2.5 fA/√Hz) as well as very high input impedances.
With 1.3 pF of input capacitance, low noise (4 nV/√Hz), low offset
voltage (2 mV maximum), and 1050 MHz −3 dB bandwidth, the
ADA4817-1/ADA4817-2 are ideal for data acquisition front ends as
well as wideband transimpedance applications, such as photodiode
preamps.
Rev. G | Page 4 of 31
Data Sheet
With a wide supply voltage range from 5 V to 10 V and the ability
to operate on either single or dual supplies, the ADA4817-1/
ADA4817-2 are designed to work in a variety of applications inclu-
ding active filtering and analog-to-digital converter (ADC) driving.
The ADA4817-1 is available in a 3 mm × 3 mm, 8-lead LFCSP and
8-lead SOIC, and the ADA4817-2 is available in a 4 mm × 4 mm,
16-lead LFCSP. These packages feature a low distortion pinout
that improves second harmonic distortion and simplifies circuit
board layout. They also feature an exposed pad that provides a
low thermal resistance path to the printed circuit board (PCB).
The EPAD enables more efficient heat transfer and increases
reliability. These products are rated to work over the extended
industrial temperature range (−40°C to +105°C).
Data Sheet ADA4817-1/ADA4817-2

SPECIFICATIONS
±5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = −5 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT = 0.1 V p-p 1050 MHz
VOUT = 2 V p-p 200 MHz
VOUT = 0.1 V p-p, G = 2 390 MHz
Gain Bandwidth Product VOUT = 0.1 V p-p ≥410 MHz
Full Power Bandwidth VIN = 3.3 V p-p, G = 2 60 MHz
0.1 dB Flatness VOUT = 2 V p-p, RL = 100 Ω, G = 2 60 MHz
Slew Rate VOUT = 4 V step 870 V/µs
Settling Time to 0.1% VOUT = 2 V step, G = 2 9 ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion
f = 1 MHz VOUT = 2 V p-p, RL = 1 kΩ
HD2 −113 dBc
HD3 −117 dBc
f = 10 MHz VOUT = 2 V p-p, RL = 1 kΩ
HD2 −90 dBc
HD3 −94 dBc
f = 50 MHz VOUT = 2 V p-p, RL = 1 kΩ
HD2 −64 dBc
HD3 −66 dBc
Input Voltage Noise f = 100 kHz 4 nV/√Hz
Input Current Noise f = 100 kHz 2.5 fA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.4 2 mV
TMIN to TMAX, SOIC 6 mV
TMIN to TMAX, LFCSP 4 mV
Input Offset Voltage Drift TMIN to TMAX, SOIC 25 80 µV/°C
TMIN to TMAX, LFCSP 10 50 µV/°C
Input Bias Current 2 20 pA
TMIN to TMAX 75 135 pA
Input Bias Offset Current 1 10 pA
TMIN to TMAX 110 pA
Open-Loop Gain 62 65 dB
INPUT CHARACTERISTICS
Input Resistance Common mode 500 GΩ
Input Capacitance Common mode 1.3 pF
Differential mode 0.1 pF
Input Common-Mode Voltage Range −VS to (+VS − 2.8) V
Common-Mode Rejection VCM = ±0.5 V −77 −90 dB
VCM = ±0.5 V, TMIN to TMAX −73 dB
VCM = −4.2 V to 2.2 V, TMIN to TMAX −65 dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±2.5 V, G = 2 8 ns

Rev. G | Page 5 of 31
ADA4817-1/ADA4817-2 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
Output Voltage Swing
High RL = 100 Ω +VS − 1.5 +VS − 1.3 V
RL = 100 Ω, TMIN to TMAX +VS − 1.65 V
RL = 1 kΩ +VS − 1.1 +VS − 1 V
RL = 1 kΩ, TMIN to TMAX +VS − 1.4 V
Low RL = 100 Ω −VS + 1.4 −VS + 1.5 V
RL = 100 Ω, TMIN to TMAX −VS + 1.65 V
RL = 1 kΩ −VS + 1 −VS + 1.1 V
RL = 1 kΩ, TMIN to TMAX −VS + 1.2 V
Linear Output Current 1% output error 40 mA
Short-Circuit Current Sinking 100 mA
Sourcing 170 mA
POWER-DOWN
PD Pin Voltage Enabled, TMIN to TMAX >+VS − 0.9 V
Powered down, TMIN to TMAX <+VS − 3.5 V
Turn On Time 0.3 µs
Turn Off Time 1 µs
Input Leakage Current PD = +VS 0.3 3 µA
PD = −VS 34 61 µA
POWER SUPPLY
Operating Range 5 10 V
Quiescent Current per Amplifier 19 21 mA
Powered Down Quiescent Current 1.5 3 mA
Positive Power Supply Rejection +VS = 4.5 V to 5.5 V, −VS = −5 V −67 −72 dB
Negative Power Supply Rejection +VS = 5 V, −VS = −4.5 V to −5.5 V −67 −72 dB

5 V OPERATION
TA = 25°C, +VS = 3 V, −VS = −2 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted.

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth VOUT = 0.1 V p-p 500 MHz
VOUT = 1 V p-p 160 MHz
VOUT = 0.1 V p-p, G = 2 280 MHz
Full Power Bandwidth VIN = 1 V p-p, G = 2 95 MHz
0.1 dB Flatness VOUT = 1 V p-p, G = 2 32 MHz
Slew Rate VOUT = 2 V step 320 V/µs
Settling Time to 0.1% VOUT = 1 V step, G = 2 11 Ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion
f = 1 MHz VOUT = 1 V p-p, RL = 1 kΩ dBc
HD2 −87 dBc
HD3 −88
f = 10 MHz VOUT = 1 V p-p, RL = 1 kΩ
HD2 −68 dBc
HD3 −66 dBc
f = 50 MHz VOUT = 1 V p-p, RL = 1 kΩ
HD2 −57 dBc
HD3 −55 dBc
Rev. G | Page 6 of 31
Data Sheet ADA4817-1/ADA4817-2
Parameter Test Conditions/Comments Min Typ Max Unit
Input Voltage Noise f = 100 kHz 4 nV/√Hz
Input Current Noise f = 100 kHz 2.5 fA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.5 2.3 mV
TMIN to TMAX, SOIC 6.5 mV
TMIN to TMAX, LFCSP 5 mV
Input Offset Voltage Drift TMIN to TMAX, SOIC 25 75 µV/°C
TMIN to TMAX, LFCSP 10 45 µV/°C
Input Bias Current 2 20 pA
TMIN to TMAX 50 70 pA
Input Bias Offset Current 1 10 pA
TMIN to TMAX 65 pA
Open-Loop Gain 61 63 dB
INPUT CHARACTERISTICS
Input Resistance Common mode 500 GΩ
Input Capacitance Common mode 1.3 pF
Differential mode 0.1 pF
Input Common-Mode Voltage Range −VS to (+VS − 2.9) V
Common-Mode Rejection VCM = ±0.25 V −72 −83 dB
VCM = ±0.3 V, TMIN to TMAX −70 dB
VCM = ±0.8 V, TMIN to TMAX −59 dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±1.25 V, G = 2 13 ns
Output Voltage Swing
High RL = 100 Ω +VS − 1.3 +VS − 1.2 V
RL = 100 Ω, TMIN to TMAX +VS − 1.4 V
RL = 1 kΩ +VS − 1.1 +VS − 1 V
RL = 1 kΩ, TMIN to TMAX +VS − 1.2 V
Low RL = 100 Ω −VS + 1 −VS + 1.1 V
RL = 100 Ω, TMIN to TMAX −VS + 1.2 V
RL = 1 kΩ −VS + 0.9 −VS + 1 V
RL = 1 kΩ, TMIN to TMAX −VS + 1.1 V
Linear Output Current 1% output error 20 mA
Short-Circuit Current Sinking 40 mA
Sourcing 130 mA
POWER-DOWN
PD Pin Voltage Enabled, TMIN to TMAX >+VS − 0.9 V
Powered down, TMIN to TMAX <+VS − 3.5 V
Turn On Time 0.2 µs
Turn Off Time 0.7 µs
Input Leakage Current PD = +VS 0.2 3 µA
PD = −VS 31 53 µA
POWER SUPPLY
Operating Range 5 10 V
Quiescent Current per Amplifier 14 16 mA
Powered Down Quiescent Current 1.5 2.8 mA
Positive Power Supply Rejection +VS = 4.75 V to 5.25 V, −VS = 0 V −66 −71 dB
Negative Power Supply Rejection +VS = 5 V, −VS = −0.25 V to +0.25 V −63 −69 dB

Rev. G | Page 7 of 31
ADA4817-1/ADA4817-2 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3. V V  V 2
PD = (VS × I S ) +  S × OUT  – OUT (2)
Parameter Rating  2 RL  RL
Supply Voltage 10.6 V Consider root mean square (rms) output voltages. If RL is
Power Dissipation See Figure 4 referenced to −VS, as in single-supply operation, the total drive
Common-Mode Input Voltage Range −VS − 0.5 V to +VS + 0.5 V power is VS × IOUT. If the rms signal levels are indeterminate,
Differential Input Voltage ±VS consider the worst-case scenario, when VOUT = VS/4 for RL to
Storage Temperature Range −65°C to +125°C midsupply.
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
PD = (VS × I S ) +
(VS /4 )2 (3)
Junction Temperature 150°C RL
Stresses at or above those listed under Absolute Maximum In single-supply operation with RL referenced to −VS, the worst-
Ratings may cause permanent damage to the product. This is a case situation is VOUT = VS/2.
stress rating only; functional operation of the product at these Airflow increases heat dissipation, effectively reducing θJA. More
or any other conditions above those indicated in the operational metal directly in contact with the package leads and exposed
section of this specification is not implied. Operation beyond pad from metal traces, through holes, ground, and power
the maximum operating conditions for extended periods may planes also reduces θJA.
affect product reliability.
Figure 4 shows the maximum safe power dissipation in the
THERMAL RESISTANCE package vs. the ambient temperature for the exposed paddle
Thermal performance is directly linked to PCB design and 8-lead LFCSP (single 94°C/W), 8-lead SOIC (single 79°C/W),
operating environment. Careful attention to PCB thermal and 16-lead LFCSP (dual 64°C/W) packages on JEDEC
design is required. standard 4-layer boards. θJA values are approximations.
3.5
Table 4.
Package Type θJA θJC Unit 3.0
MAXIMUM POWER DISSIPATION (W)

ADA4817-2, LFCSP
CP-8-13 94 29 °C/W 2.5
RD-8-1 79 29 °C/W ADA4817-1, SOIC

CP-16-20 64 14 °C/W 2.0

MAXIMUM SAFE POWER DISSIPATION 1.5

ADA4817-1, LFCSP
The maximum safe power dissipation for the ADA4817-1/
1.0
ADA4817-2 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C (which is 0.5

the glass transition temperature), the properties of the plastic

0
change. Even temporarily exceeding this temperature limit may –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100
07756-008

change the stresses that the package exerts on the die, permanently AMBIENT TEMPERATURE (°C)

shifting the parametric performance of the ADA4817-1/ Figure 4. Maximum Safe Power Dissipation vs. Ambient Temperature for
ADA4817-2. Exceeding a junction temperature of 150°C for an a 4-Layer Board
extended period can result in changes in silicon devices, ESD CAUTION
potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the ADA4817-1/ADA4817-2 drive at the output.
The quiescent power is the voltage between the supply pins
(VS) multiplied by the quiescent current (IS).
PD = Quiescent Power + (Total Drive Power − Load Power) (1)

Rev. G | Page 8 of 31
Data Sheet ADA4817-1/ADA4817-2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADA4817-1
TOP VIEW
(Not to Scale)

PD 1 8 +VS
FB 2 7 OUT

–IN 3 6 NIC

+IN 4 5 –VS

NOTES
1. NIC = NO INTERNAL CONNECTION.

07756-005
2. EXPOSED PAD. CAN BE CONNECTED
TO GND, –VS PLANE, OR LEFT FLOATING.

Figure 5. ADA4817-1 Pin Configuration (8-Lead LFCSP)

Table 5. ADA4817-1 Pin Function Descriptions (8-Lead LFCSP)

Pin No. Mnemonic Description
1 PD Power-Down. Do not leave floating.
2 FB Feedback Pin.
3 −IN Inverting Input.
4 +IN Noninverting Input.
5 −VS Negative Supply.
6 NIC No Internal Connection.
7 OUT Output.
8 +VS Positive Supply.
EPAD Exposed Pad. Can be connected to GND, −VS plane, or left floating.
ADA4817-1
TOP VIEW
(Not to Scale)

FB 1 8 PD
–IN 2 7 +VS
+IN 3 6 OUT
–VS 4 5 NIC

NOTES
1. NIC = NO INTERNAL CONNECTION.
07756-006

2. EXPOSED PAD. CAN BE CONNECTED TO GND,

−VS PLANE, OR LEFT FLOATING.

Figure 6. ADA4817-1 Pin Configuration (8-Lead SOIC)

Table 6. ADA4817-1 Pin Function Descriptions (8-Lead SOIC)

Pin No. Mnemonic Description
1 FB Feedback Pin.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VS Negative Supply.
5 NIC No Internal Connection.
6 OUT Output.
7 +VS Positive Supply.
8 PD Power-Down. Do not leave floating.
EPAD Exposed Pad. Can be connected to GND, −VS plane, or left floating.

Rev. G | Page 9 of 31
ADA4817-1/ADA4817-2 Data Sheet
ADA4817-2
TOP VIEW
(Not to Scale)

13 OUT1
14 +VS1
15 PD1
16 FB1
–IN1 1 12 –VS1
+IN1 2 11 NIC
NIC 3 10 +IN2
–VS2 4 9 –IN2

FB2 8
PD2 7
OUT2 5
+VS2 6
NOTES
1. NIC = NO INTERNAL CONNECTION.

07756-107
2. EXPOSED PAD. CAN BE CONNECTED
TO GND, –VS PLANE, OR LEFT FLOATING.

Figure 7. ADA4817-2 Pin Configuration (16-Lead LFCSP)

Table 7. ADA4817-2 Pin Function Descriptions (16-Lead LFCSP)

Pin No. Mnemonic Description
1 −IN1 Inverting Input 1.
2 +IN1 Noninverting Input 1.
3, 11 NIC No Internal Connection.
4 −VS2 Negative Supply 2.
5 OUT2 Output 2.
6 +VS2 Positive Supply 2.
7 PD2 Power-Down 2. Do not leave floating.
8 FB2 Feedback Pin 2.
9 −IN2 Inverting Input 2.
10 +IN2 Noninverting Input 2.
12 −VS1 Negative Supply 1.
13 OUT1 Output 1.
14 +VS1 Positive Supply 1.
15 PD1 Power-Down 1. Do not leave floating.
16 FB1 Feedback Pin 1.
EPAD Exposed Pad. Can be connected to GND, −VS plane, or left floating.

Rev. G | Page 10 of 31
Data Sheet ADA4817-1/ADA4817-2

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±5 V, G = 1, (RF = 348 Ω for G > 1), RL = 100 Ω to ground, small signal VOUT = 100 mV p-p, large signal VOUT = 2 V p-p,
unless otherwise noted.
6 6
G = 1, DUAL G = 1, SINGLE
NORMALIZED CLOSED-LOOP GAIN (dB)

NORMALIZED CLOSED-LOOP GAIN (dB)

G =2
3 3 G = 1, SINGLE
G =2
G = 1, DUAL
0 0

G=5 G =5
–3 –3

–6 –6

–9 –9

–12 –12
07756-066

07756-009
100k 1M 10M 100M 1G 10G 100k 1M 10M 100M 1G 10G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 8. Small Signal Frequency Response for Various Gains (LFCSP) Figure 11. Large Signal Frequency Response for Various Gains

6 6
VS = 10V, SOIC
VS = 10V, LFCSP
3 3
VS = 5V, LFCSP
CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)

VS = 5V, SOIC VS = 10V

0 0

–3 –3
VS = 5V

–6 –6

–9 –9

VOUT = 1V p-p
–12 –12
07756-007

07756-010
100k 1M 10M 100M 1G 10G 100k 1M 10M 100M 1G 10G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 9. Small Signal Frequency Response for Various Supplies Figure 12. Large Signal Frequency Response for Various Supplies

9 9
CL = 6.6pF
CL = 2.2pF RF = 274Ω
CL = 4.4pF RF = 348Ω
6 6
CL = 0pF
CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)

RF = 200Ω
3 3

0 0

–3 –3

–6 –6
G=2
RF = 274Ω G=2
–9 –9
07756-068

07756-011

100k 1M 10M 100M 1G 10G 100k 1M 10M 100M 1G 10G

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 10. Small Signal Frequency Response for Various CL Figure 13. Small Signal Frequency Response for Various RF

Rev. G | Page 11 of 31
ADA4817-1/ADA4817-2 Data Sheet
0.5 6

0.4
NORMALIZED CLOSED-LOOP GAIN (dB)

G = 2, SS
3
0.3
G = 2, LS

CLOSED-LOOP GAIN (dB)

0.2
0
0.1 G = 1, SS

0 –3

–0.1 G = 1, LS
–6
–0.2 TA = +25°C, SINGLE
TA = +25°C, DUAL
–0.3 –9 TA = –40°C, SINGLE
TA = –40°C, DUAL

07756-036
–0.4 TA = +105°C, SINGLE
TA = +105°C, DUAL
–0.5 –12

07756-012
100k 1M 10M 100M 1G 10G 100k 1M 10M 100M 1G 10G
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 14. 0.1 dB Flatness Frequency Response vs. Gain and Output Voltage Figure 17. Small Signal Frequency Response vs. Temperature

–20 –20

–40 –40
DISTORTION (dBc)

–60
DISTORTION (dBc)

–60
HD2, VS = 5V

HD2, RL = 100Ω HD3, VS = 5V

–80 –80
HD2, RL = 1kΩ

–100 –100

HD3, RL = 100Ω
–120
–120 HD2, VS = 10V
HD3, RL = 1kΩ HD3, VS = 10V

–140

07756-013
–140 100k 1M 10M 100M
07756-014

100k 1M 10M 100M

FREQUENCY (Hz)
FREQUENCY (Hz)

Figure 15. Distortion vs. Frequency for Various Loads, VOUT = 2 V p-p Figure 18. Distortion vs. Frequency for Various Supplies, VOUT = 2 V p-p

–20 –20
fC = 1MHz

–40 –40

HD2, VS = 5V
DISTORTION (dBc)
DISTORTION (dBc)

–60 –60
HD2, VS = 10V

–80 –80
HD2, RL = 100Ω
HD2, RL = 1kΩ
–100 –100
HD3, VS = 5V

–120 HD3, VS = 10V –120

HD3, RL = 100Ω
HD3, RL = 1kΩ
–140 –140
07756-017
07756-016

100k 1M 10M 100M 0 1 2 3 4 5 6

FREQUENCY (Hz) OUTPUT VOLTAGE (V p-p)

Figure 16. Distortion vs. Frequency for Various Supplies, G = 2, VOUT = 2 V p-p Figure 19. Distortion vs. Output Voltage for Various Loads

Rev. G | Page 12 of 31
Data Sheet ADA4817-1/ADA4817-2
1.5
0.075

1.0
0.050

OUTPUT VOLTAGE (V)

0.5
OUTPUT VOLTAGE (V)

0.025

0
0

–0.5
–0.025 SINGLE,SOIC
DUAL, LFCSP RF = 0Ω DUAL, LFCSP
RF = 0Ω SINGLE, CSP –1.0 RL = 100Ω
–0.050 RL = 100Ω VS = ±5V

07756-024
VS = ±5V G = +1

07756-022
G = +1 SINGLE, CSP
SINGLE, SOIC –1.5
–0.075

TIME (5ns/DIV) TIME (5ns/DIV)

Figure 20. Small Signal Transient Response vs. Package Figure 23. Large Signal Transient Response vs. Package

6
0.5
2 × VIN SETTLING TIME
0.4
4
0.3
OUTPUT VOLTAGE (V)

2 0.2

SETTLING TIME (%) 0.1

0 0

–0.1
–2 VOUT
–0.2

–4 –0.3

07756-023
G=2 –0.4
07756-019

–6 –0.5
TIME (10ns/DIV)

TIME (5ns/DIV)

Figure 21. Output Overdrive Recovery Figure 24. 0.1% Short-Term Settling Time

0.15 0
DUAL, CF = 0.5pF
SINGLE, NO CF –10
0.10
–20
SINGLE
OUTPUT VOLTAGE (V)

–30
0.05
–40
PSRR (dB)

–PSRR
0 –50 +PSRR

–60
–0.05
–70
DUAL
–80
–0.10
07756-021

VS = 5V –90
G=2
–0.15 –100
07756-032

100k 1M 10M 100M 1G

TIME (5ns/DIV) FREQUENCY (Hz)

Figure 22. Small Signal Transient Response Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency

Rev. G | Page 13 of 31
ADA4817-1/ADA4817-2 Data Sheet
–20 24

–25
22
–30 VS = ±5V

QUIESCENT CURRENT (mA)

20
–35
CMRR (dB)

–40 18

–45
16
VS = +5V
–50
14
–55
12

07756-033
–60

–65 10

07756-029
10k 100k 10M 1G –40 –20 0 20 40 60 80 100
FREQUENCY (Hz) TEMPERATURE (°C)

Figure 26. Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 29. Quiescent Current vs. Temperature for Various Supply Voltages

100 1.6
VS = ±5V RL = 100Ω
1.5 –V-S + VOUT

OUTPUT SATURATION VOLTAGE (V)

10 1.4
OUTPUT IMPEDANCE (Ω)

1.3
+VS – VOUT
1 1.2 +VS – VOUT

1.1

0.1 1.0

0.9 VS = +5V

07756-034
–VS + VOUT
0.01 0.8
07756-030

100k 1M 10M 100M 1G –40 –20 0 20 40 60 80 100

FREQUENCY (Hz) TEMPERATURE (°C)

Figure 27. Output Impedance vs. Frequency Figure 30. Output Saturation Voltage vs. Temperature

1000
70 0

60
INPUT VOLTAGE NOISE (nV/ Hz)

GAIN
50 –45
OPEN-LOOP GAIN (dB)

100

PHASE (Degrees)
40
PHASE
30 –90

10 20

10 –135

0
1
07756-026

10 100 1k 10k 100k 1M 10M 100M

–10 –180
07756-015

FREQUENCY (Hz) 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 28. Input Voltage Noise vs. Frequency Figure 31. Open-Loop Gain and Phase vs. Frequency

Rev. G | Page 14 of 31
Data Sheet ADA4817-1/ADA4817-2
40 40
VS = ±5V VS = ±5V
35 35
PERCENT OF AMPLIFIERS

PERCENT OF AMPLIFIERS
30 30

25 25

20 20

15 15

10 10

5 5

07756-400

07756-401
0 0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0

0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–2.0
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2

–2.0
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
OFFSET VOLTAGE (mV) OFFSET VOLTAGE (mV)

Figure 32. Input Offset Voltage Histogram Figure 35. Input Offset Voltage Histogram
(VS = ±5 V), LFCSP Only (VS = ±5 V), SOIC Only

14 14
VS = ±5V VS = 5V

12 12
TA = –40°C TA = –40°C
TA = +105°C TA = +105°C
10 10
NUMBER OF HITS

8 NUMBER OF HITS 8

6 6

4 4

2 2
07756-335

07756-338
0 0
–4 –3 –2 –1 0 1 2 3 4 –4 –3 –2 –1 0 1 2 3 4
VOS (mV) VOS (mV)

Figure 33. Input Offset Voltage Histogram over Temperature Figure 36. Input Offset Voltage Histogram over Temperature
(VS = ±5 V), LFCSP Only (VS = 5 V), LFCSP Only

24 24
VS = ±5V VS = 5V
TA = –40°C
TA = –40°C
21 21
TA = +105°C TA = +105°C

18 18
NUMBER OF HITS

NUMBER OF HITS

15 15

12 12

9 9

6 6

3 3
07756-334

07756-337

0 0
–6 –4 –2 0 2 4 6 –6 –4 –2 0 2 4 6
VOS (mV) VOS (mV)

Figure 34. Input Offset Voltage Histogram over Temperature Figure 37. Input Offset Voltage Histogram over Temperature
(VS = ±5 V), SOIC Only (VS = 5 V), SOIC Only

Rev. G | Page 15 of 31
ADA4817-1/ADA4817-2 Data Sheet
5 5
VS = ±5V VS = 5V
4 4

3 3
OFFSET VOLTAGE (mV)

OFFSET VOLTAGE (mV)

2 2

1 SOIC 1
SOIC
0 0
LFCSP
–1 –1
LFCSP
–2 –2

–3 –3

07756-340

07756-343
–4 –4

–5 –5
–60 –40 –20 0 20 40 60 80 100 120 –60 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 38. Offset Voltage vs. Temperature Figure 41. Offset Voltage vs. Temperature
(VS = ±5 V) (VS = 5 V)

10 10
VS = ±5V VS = 5V
9 9
LFCSP SOIC LFCSP SOIC
8 8
NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS
7 7

6 6

5 5

4 4

3 3

2 2
07756-336

07756-339
1 1

0 0
0

0
10

20

30

40

50

60

70

10

20

30

40

50

60

70
–70

–60

–50

–40

–30

–20

–10

–70

–60

–50

–40

–30

–20

–10

INPUT OFFSET VOLTAGE DRIFT (µV/˚C) INPUT OFFSET VOLTAGE DRIFT (µV/˚C)

Figure 39. Input Offset Voltage Drift Histogram Figure 42. Input Offset Voltage Drift Histogram
(VS = ±5V) (VS = 5 V)

30 30
TA = 25°C VS = ±5V VS = 5V
TA = 105°C TA = 25°C
25 25
TA = 105°C
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

20 20

15 15

10 10

5 5
07556-344
07556-341

0 0
–80 –70 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –80 –70 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80
INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (pA)

Figure 40. Input Bias Current Histogram over Temperature Figure 43. Input Bias Current Histogram over Temperature
(VS = ±5 V) (VS = 5 V)

Rev. G | Page 16 of 31
Data Sheet ADA4817-1/ADA4817-2
500 1000
VS = ±5V VS = 5V

COMMON-MODE REJECTION RATIO (µV/V)

COMMON-MODE REJECTION RATIO (µV/V)

400 800

300 600

200 400

100 200

0 0

–100 –200

–200 –400

–300 –600

07756-345
07756-342
–400 –600

–500 –1000
0

0.5

1.0

1.5

2.0

2.5
–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)

Figure 44. Common-Mode Rejection vs. Common-Mode Voltage, Figure 45. Common-Mode Rejection vs. Common-Mode Voltage,
VS = ±5 V VS = 5 V

Rev. G | Page 17 of 31
ADA4817-1/ADA4817-2 Data Sheet

TEST CIRCUITS
The output feedback pins are used for ease of layout as shown in Figure 46 to Figure 51.
+VS
+VS 10µF
10µF

+
+

RG RF
0.1µF 0.1µF 0.1µF 0.1µF

VOUT VOUT
VIN VIN RL
RL
49.9Ω 49.9Ω
10µF 10µF

+
+

0.1µF 0.1µF

07756-141
–VS 07756-147 –VS

Figure 46. G = 1 Configuration Figure 49. Noninverting Gain Configuration

+VS +VS

10µF
AC 49.9Ω

+
0.1µF

VOUT VOUT
RL RL
49.9Ω
10µF
AC
+

0.1µF

07756-148
07756-145

–VS –VS

Figure 47. Positive Power Supply Rejection Figure 50. Negative Power Supply Rejection

+VS
+VS 10µF
10µF
+
+

RG RF 1kΩ

0.1µF 0.1µF 1kΩ 0.1µF 0.1µF

VIN 1kΩ VOUT

VOUT
VIN RSNUB RL
CL RL
49.9Ω 53.6Ω 1kΩ

10µF 10µF
+

0.1µF
+

0.1µF
07756-146
07756-142

–VS –VS

Figure 48. Capacitive Load Configuration Figure 51. Common-Mode Rejection

Rev. G | Page 18 of 31
Data Sheet ADA4817-1/ADA4817-2

THEORY OF OPERATION
The ADA4817-1/ADA4817-2 are voltage feedback operational At dc,
amplifiers that combine new architecture for FET input operational VO RF + RG
amplifiers with the eXFCB process from Analog Devices, = (5)
VI RG
resulting in an outstanding combination of speed and low noise.
The innovative high speed FET input stage handles common- The closed-loop −3 dB frequency is
mode signals from the negative supply to within 2.7 V of the RG
positive rail. This stage is combined with an H-bridge to attain an =
f −3dB fCROSSOVER × (6)
RF + RG
870 V/µs slew rate and low distortion, in addition to 4 nV/√Hz
input voltage noise. The amplifier features a high speed output INVERTING CLOSED-LOOP FREQUENCY RESPONSE
stage capable of driving heavy loads sourcing and sinking up to Solving for the transfer function,
40 mA of linear current. Supply current and offset current are −2π × fCROSSOVER × RF
VO
laser trimmed for optimum performance. These specifications = (7)
VI ( RF + RG ) S + 2π × fCROSSOVER × RG
make the ADA4817-1/ADA4817-2 a great choice for high speed
instrumentation and high resolution data acquisition systems. At dc
Their low noise, picoampere input current, precision offset, and VO R
high speed make them superb preamps for fast photo-diode = − F (8)
VI RG
applications.
Solve for closed-loop −3 dB frequency by
CLOSED-LOOP FREQUENCY RESPONSE
RG
The ADA4817-1/ADA4817-2 are classic voltage feedback =
f −3dB fCROSSOVER × (9)
RF + RG
amplifiers with an open-loop frequency response that can be
approximated as the integrator response shown in Figure 54. Basic 80 A = (2π × fCROSSOVER )/s
closed-loop frequency response for inverting and noninverting
configurations can be derived from the schematics shown in
Figure 52 and Figure 53.
OPEN-LOOP GAIN (A) (dB)

60
RF

RG 40
VOUT
VE A
VIN
07756-044

fCROSSOVER = 410MHz
20
Figure 52. Noninverting Configuration
RF
0

07756-046
0.1 1 10 100 1000
VIN RG FREQUENCY (MHz)
VOUT
VE A Figure 54. Open-Loop Gain vs. Frequency
07756-045

The closed-loop bandwidth is inversely proportional to the noise

Figure 53. Inverting Configuration gain of the op amp circuit, (RF + RG)/RG. This simple model is
accurate for noise gains above 2. The actual bandwidth of circuits
NONINVERTING CLOSED-LOOP FREQUENCY
with noise gains at or below 2 is higher than those predicted
RESPONSE
with this model due to the influence of other poles in the
Solving for the transfer function, frequency response of the real op amp.
VO 2π × fCROSSOVER ( RG + RF ) Figure 55 shows the dc errors of the voltage feedback amplifier.
= (4)
VI ( RF + RG ) S + 2π × fCROSSOVER × RG For both inverting and noninverting configurations,
where: VOUT (error) =
fCROSSOVER is the frequency where the open-loop gain of the
 R + RF   RG + RF 
amplifier equals 0 dB. Ib+ × RS  G  − Ib− × RF + VOS   (10)
VO is the output voltage.  RG   RG 
VI is the input voltage. where Ib is the bias current.

Rev. G | Page 19 of 31
ADA4817-1/ADA4817-2 Data Sheet
DRIVING CAPACITIVE LOADS
RF

RG
+VOS – In general, high speed amplifiers have a difficult time driving
capacitive loads. This is particularly true in low closed-loop
RS
Ib – A VOUT
gains, where the phase margin is the lowest.
VIN
The difficulty arises because the load capacitance, CL, forms a

07756-047
Ib+
pole with the output resistance, RO, of the amplifier. The pole can
be described by the following equation:
Figure 55. DC Errors of the Voltage Feedback Amplifier
1
The voltage error due to Ib+ and Ib− is minimized if RS = RF || RG fP = (12)
2πROCL
(though with the ADA4817-1/ADA4817-2 input currents in the
picoamp range, this is likely not a concern). To include common- If this pole occurs too close to the unity-gain crossover point,
mode effects and power supply rejection effects, total VOS can be the phase margin degrades. Degradation is due to the additional
modeled by phase loss associated with the pole.
Δ VS Δ VCM Note that such capacitance introduces significant peaking in the
VOS = VOSnom + + (11)
PSR CMR frequency response. Larger capacitance values can be driven but
must use a small series resistor, RSNUB, at the output of the amplifier,
where:
as shown in Figure 56. Adding RSNUB creates a zero that cancels
VOS is the offset voltage.
the pole introduced by the load capacitance. Typical values for
VOSnom is the offset voltage specified at nominal conditions. RSNUB can range from 10 Ω to 50 Ω. The value is typically based on
ΔVS is the change in power supply from nominal conditions. the circuit requirements. Figure 56 also shows another way to
PSR is the power supply rejection. reduce the effect of the pole created by the capacitive load (CL) by
ΔVCM is the change in common-mode voltage from nominal placing a capacitor (CF) in the feedback loop parallel to the
conditions. feedback resistor Typical capacitor values can range from 0.5 pF to
CMR is the common-mode rejection. 2 pF. Figure 59 shows the effect of adding a feedback capacitor to
the frequency response.
WIDEBAND OPERATION
+VS
The ADA4817-1/ADA4817-2 provides excellent performance as a 10µF

high speed buffer. Figure 52 shows the circuit used for wideband
+

CF
characterization for high gains. The impedance at the summing
junction (RF || RG) forms a pole in the loop response of the RG RF

amplifier with the input capacitance of the amplifier of 1.3 pF.

0.1µF 0.1µF

This pole can cause peaking and ringing if its frequency is too VIN RSNUB
VOUT
CL RL
low. Feedback resistances of 100 Ω to 400 Ω are recommended 49.9Ω

because they minimize the peaking and they do not degrade 10µF
+

0.1µF
the performance of the output stage. Peaking in the frequency
07756-143

response can also be compensated for with a small feedback –VS

capacitor (CF) in parallel with the feedback resistor, or a series
resistor in the noninverting input, as shown in Figure 56.
The distortion performance depends on the following variables:
• The closed-loop gain of the application
• Whether it is inverting or noninverting
• Amplifier loading
• Signal frequency and amplitude
• Board layout
The best performance is usually obtained in the G + 1
configuration with no feedback resistance, big output
load resistors, and small board parasitic capacitances.
Figure 56. RSNUB or CF Used to Reduce Peaking
THERMAL CONSIDERATIONS
With 10 V power supplies and 19 mA quiescent current, the
ADA4817-1/ADA4817-2 dissipate 190 mW with no load. This
implies that with the thermal resistances listed in Table 4, the
junction temperature is typically almost 25°C higher than the
ambient temperature. The ADA4817-1/ADA4817-2 can maintain
a constant bandwidth over temperature; therefore, an initial
ramp up of the current consumption during warm-up is
expected. VOS can change up to 0.3 mV due to warm-up effects
for an ADA4817-1/ADA4817-2 on ± 5 V. The input bias current
typically increases by a factor of 1.7 for every 10°C rise in
temperature.

Rev. G | Page 20 of 31
Data Sheet ADA4817-1/ADA4817-2
Heavy loads increase power dissipation and raise the chip
junction temperature as described in the Absolute Maximum
Ratings section. Take care not to exceed the rated power
IN
dissipation of the package. 1

POWER-DOWN OPERATION
The ADA4817-1/ADA4817-2 are equipped with separate power-
2
down pins (PD) for each amplifier that allow the user the ability PD

to reduce the quiescent supply current when an amplifier is OUT

inactive from 19 mA to below 2 mA. The power-down
3

threshold levels are referenced to the +VS pin. The amplifier is

07756-359
enabled when the PD pin voltage is within 0.9 V of the +VS
CH1 2.00V M400ms A CH1 2.48V
supply. The amplifier is disabled when the PD pin voltage is at CH2 2.00V T –516.000ms
CH3 200mV 25.0kS/s 100k POINTS
least 3.5 V from the +VS supply. Table 8 shows the required
Figure 58. Power-Down Operation
thresholds for power-down with supplies of ±5 V and 3 V, −2 V,
over temperature. If the PD pin is not used, connect it to the CAPACITIVE FEEDBACK
positive power supply to ensure proper startup. Due to package variations and pin to pin parasitics between the
single and the dual models, the ADA4817-2 has a little more
Table 8. PD Pin Control
peaking than the ADA4817-1, especially at a gain of 2. The
Supply Voltages ±5 V +3 V, −2 V recommended method to tame the peaking is to place a
Amplifier Enabled >4.1 V >2.1 V feedback capacitor across the feedback resistor. Figure 59 shows
Amplifier Disabled <1.5 V <−0.5 V the small signal frequency response of the ADA4817-2 at a gain of
When the amplifier is powered down with the supplies of +3 V 2 vs. CF. At first, no CF was used to show the peaking; but then
and −2 V, the PD pin needs to be driven below ground to ensure two other values of 0.5 pF and 1 pF were used to show how to
the power-down. This may be a problem if a microcontroller is reduce the peaking or even eliminate it. If the power consumption
being used to drive the PD pin. The circuit in Figure 57 can be is a factor in the system, using a larger feedback capacitor is
added to ensure that the required threshold is met. acceptable as long as a feedback capacitor is used across it to
+VS +VS control the peaking, as shown in Figure 59.
However, if power consumption is not an issue, a lower value
RF4 RF3
3.6kΩ 1kΩ feedback resistor, such as 200 Ω, does not require any additional
feedback capacitance to maintain flatness and lower peaking.
Q2 9
2N3906 CF = 0.5pF NO CF
RF1
3.6kΩ Q1
6
2N3904 PD
CLOSED-LOOP GAIN (dB)

CF = 1pF
3
PD_CONTROL +
0V TO 3.3V RF5 RF6
500ns TO 10µs 11kΩ 20kΩ
0
07756-358

–V S
–3
Figure 57. Power-Down Circuit
RF = 348Ω
The plot in Figure 58 shows that the PD pin is driven to the –6
G=2
VS = 10V
07756-049

positive rail when the microcontroller logic is high, and to the

VOUT = 100mV p-p
RL = 100Ω
–9
negative rail when the microcontroller logic is low. The RF5 and 1M 10M 100M 1G 10G
RF6 resistors must be chosen to be sufficiently high so that FREQUENCY (Hz)

minimal current is drawn by the circuit. Figure 59. Small Signal Frequency Response vs. Feedback Capacitor
(ADA4817-2)

Rev. G | Page 21 of 31
ADA4817-1/ADA4817-2 Data Sheet
HIGHER FREQUENCY ATTENUATION
L C

10nH
2pF
There is another package variation problem between the SOIC

07756-248
R
and the LFCSP package. The SOIC package shows approximately
120Ω
1 dB to 1.5 dB of additional peaking at a gain of 1, due to the
Figure 61. RLC Circuit
parasitic capacitances in the SOIC package, which is not
recommended for very high frequency parts that exceed 1 GHz. A The R in parallel to the series LC forms a notch that can be
good approach to reduce the peaking is to place a resistor, RS, in shaped to compensate for the peaking produced by the amplifier.
series with the noninverting input, which creates a first-order The result is a smooth 1 GHz −3 dB bandwidth, 250 MHz 0.1 dB
pole formed by RS and CIN, the common-mode input flatness, and less than 1 dB of peaking. Place this circuit in the
capacitance. path of the noninverting input when the ADA4817-1/ADA4817-2
are used at a gain of 1. The RLC values may need adjustment
Figure 60 shows the higher frequency attenuation, which
depending on the source impedance and the flatness and
reduces the peaking but also reduces the −3 dB bandwidth.
6
bandwidth required. Figure 62 shows the frequency response
after the RLC circuit is in place.
RS = 75Ω
6
RS = 50Ω
3
NO RLC
RS = 0Ω
CLOSED-LOOP GAIN (dB)

CLOSED-LOOP GAIN (dB)

0

RS = 100Ω 0
–3
RLC

–3
–6 RL = 100Ω
VS = ±5V
07756-247

VOUT = 0.1V p-p

–6 RL = 100Ω
G=1
–9 VS = 10V

07756-249
1M 10M 100M 1G 10G VOUT = 100mV p-p
FREQUENCY (Hz) G=1
–9
1M 10M 100M 1G 10G
Figure 60. Small Signal Frequency Response for Various RS (SOIC)
FREQUENCY (Hz)

As shown in Figure 60, the peaking dropped by almost 2 dB Figure 62. Frequency Response with RLC Circuit
when RS = 0 Ω to RS = 100 Ω, and in return, the −3 dB bandwidth
dropped from 1 GHz to 700 MHz. To maintain the −3 dB
bandwidth and to reduce peaking, an RLC circuit is recommended
instead of RS, as shown in Figure 61.

Rev. G | Page 22 of 31
Data Sheet
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
Laying out the PCB is usually the last step in the design process
and often proves to be one of the most critical. A good design can
be rendered useless because of poor layout. Because the
ADA4817-1/ADA4817-2 can operate into the radio frequency
(RF) spectrum, high frequency board layout considerations
must be taken into account. The PCB layout, signal routing, power
supply bypassing, and grounding all must be addressed to
ensure optimal performance.
SIGNAL ROUTING
The ADA4817-1/ADA4817-2 feature a low distortion pinout with
a dedicated feedback pin that allows a compact layout. The
dedicated feedback pin reduces the distance from the output to
the inverting input, which greatly simplifies the routing of the
feedback network.
When laying out the ADA4817-1/ADA4817-2 as a unity-gain
amplifier, it is recommended to place a short but wide trace
between the dedicated feedback pins and the inverting input to
the amplifier to minimize stray parasitic inductance.
To minimize parasitic inductances, use ground planes under
high frequency signal traces. However, remove the ground
plane from under the input and output pins to minimize the
formation of parasitic capacitors, which degrades phase margin.
Run signals are susceptible to noise pickup on the internal
layers of the PCB, which can provide maximum shielding.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, properly bypass the ADA4817-1/
ADA4817-2 power supply pins.
A parallel connection of capacitors from each of the power
supply pins to ground works best. Paralleling different values
and sizes of capacitors helps ensure that the power supply pins
see a low ac impedance across a wide band of frequencies,
which is important for minimizing the coupling of noise into
the amplifier. Starting directly at the power supply pins, place
the smallest value and sized component on the same side of the
board as the amplifier, and as close as possible to the amplifier,
and connect it to the ground plane. Repeat this process for the
next largest value capacitor. It is recommended to use a 0.1 µF
ceramic, 0508 case for the ADA4817-1/ADA4817-2.
The 0508 case offers low series inductance and excellent high
frequency performance. The 0.1 µF provides low impedance at
high frequencies. Place a 10 µF electrolytic capacitor in parallel
with the 0.1 µF. The 10 µF electrolytic capacitor provides low ac
impedance at low frequencies. Smaller values of electrolytic
capacitors can be used depending on the circuit requirements.
Additional smaller value capacitors help provide a low
Rev. G | Page 23 of 31
ADA4817-1/ADA4817-2
impedance path for unwanted noise out to higher frequencies
but are not always necessary.
Placement of the capacitor returns (grounds) is also important.
Returning the grounds of the capacitor close to the amplifier
load is critical for distortion performance. Keeping the distance of
the capacitors short, but equal from the load, is optimal for
performance.
In some cases, bypassing between the two supplies can help to
improve PSRR and to maintain distortion performance in
crowded or difficult layouts. Bypassing is another option to
improve performance.
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduces the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
which can introduce high frequency ringing at the output. This
additional inductance can also contribute to increased distortion
due to high frequency compression at the output. Minimize the
use of vias in the direct path to the amplifier power supply pins
because vias can introduce parasitic inductance, which can lead to
instability. When required to use vias, choose multiple large
diameter vias because this lowers the equivalent parasitic
inductance.
GROUNDING
The use of ground and power planes is encouraged as a method
of providing low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce stray
trace inductance and to provide a low thermal path for the
amplifier. Do not use ground and power planes under any of
the pins. The mounting pads and the ground or power planes
can form a parasitic capacitance at the input of the amplifier. Stray
capacitance on the inverting input and the feedback resistor form
a pole, which degrades the phase margin, leading to instability.
Excessive stray capacitance on the output also forms a pole,
which degrades phase margin.
EXPOSED PAD
The ADA4817-1/ADA4817-2 feature an exposed pad, which
lowers the thermal resistance by 25% compared to a standard
SOIC plastic package. The exposed pad of the ADA4817-1/
ADA4817-2 floats internally, which provides the maximum
flexibility and ease of use. It can be connected to the ground plane
or to the negative power supply plane. In cases where thermal
heating is not an issue, the exposed pad can be left floating.
The use of thermal vias or heat pipes can also be incorporated
into the design of the mounting pad for the exposed pad. These
additional vias help to lower the overall junction to ambient
temperature (θJA). Using a heavier weight copper on the surface
to which the exposed paddle of the amplifier is soldered can
ADA4817-1/ADA4817-2
greatly reduce the overall thermal resistance seen by the
ADA4817-1/ADA4817-2.
LEAKAGE CURRENTS
Poor PCB layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the ADA4817-1/ADA4817-2. Any
voltage differential between the inputs and nearby runs sets up
leakage currents through the PCB insulator, for example, 1 V/
100 GΩ = 10 pA. Similarly, any contaminants, such as skin oils
on the board, can create significant leakage. To reduce leakage
significantly, put a guard ring (shield) around the inputs and
input leads that are driven to the same voltage potential as the
inputs. This way there is no voltage potential between the inputs
and surrounding area to set up any leakage currents. For the
guard ring to be completely effective, it must be driven by a
relatively low impedance source and it must completely surround
the input leads on all sides (above and below) when using a
multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials,
such as Teflon® or ceramic, can be necessary in some instances.
Data Sheet
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can
be sensitive to parasitic capacitance between the inputs and
ground. A few picofarads of capacitance reduces the input
impedance at high frequencies, in turn increasing the gain of
the amplifier, causing peaking of the frequency response or
even oscillations if severe enough. It is recommended to place
the external passive components connected to the input pins
as close as possible to the inputs to avoid parasitic capacitance.
The ground and power planes must be kept at a small distance
from the input pins on all layers of the board.
INPUT-TO-INPUT/OUTPUT COUPLING
To minimize capacitive coupling between the inputs and outputs,
ensure that the output signal traces are not parallel with the
inputs. In addition, ensure that the input traces are not close to
each other. A minimum of 7 mils between the two inputs is
recommended.

Rev. G | Page 24 of 31
Data Sheet ADA4817-1/ADA4817-2

APPLICATIONS INFORMATION
LOW DISTORTION PINOUT The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
The ADA4817-1/ADA4817-2 feature a low distortion pinout
capacitance at the summing junction of the amplifier, including the
from Analog Devices. The new pinout provides two advantages
photodiode capacitance (CS) and the amplifier input capacitance.
over the traditional pinout. The first advantage is improved
RF and the total capacitance produce a pole in the loop
second harmonic distortion performance, which is accomplished
transmission of the amplifier that can result in peaking and
by the physical separation of the noninverting input pin and the
instability. Adding CF creates a zero in the loop transmission
negative power supply pin. The second advantage is the
that compensates for the effect of the pole and reduces the
simplification of the layout due to the dedicated feedback pin and
signal bandwidth. It can be shown that the signal bandwidth
easy routing of the gain set resistor back to the inverting input
obtained with a 45° phase margin (f(45)) is defined by
pin. This pinout allows a compact layout, which helps to
minimize parasitics and increase stability. fCR
f(45) = (14)
The designer does not need to use the dedicated feedback pin to 2π × RF × (CS + C M + CD )
provide feedback for the ADA4817-1/ADA4817-2. The output where:
pin of the ADA4817-1/ADA4817-2 can still be used to provide fCR is the amplifier crossover frequency.
feedback to the inverting input of the ADA4817-1/ADA4817-2. RF is the feedback resistor.
WIDEBAND PHOTODIODE PREAMP CS is the source capacitance including the photodiode and the
board parasitic.
The wide bandwidth and low noise of the ADA4817-1/
CM is the common-mode capacitance of the amplifier.
ADA4817-2 make it an ideal choice for transimpedance amplifiers,
CD is the differential capacitance of the amplifier.
such as those used for signal conditioning with high speed photo-
diodes. Figure 63 shows a current to voltage converter with an The CF value that produces f(45) is shown to be
electrical model of a photodiode. The basic transfer function is CS + C M + C D
CF = (15)
I PHOTO × RF 2π × RF × fCR
VOUT = (13)
1 + sCF RF
The frequency response shows less peaking if larger CF values
where: are used.
IPHOTO is the output current of the photodiode. Figure 64 shows the preamplifier output noise over frequency.
RF and CF are the parallel combination that sets the signal
bandwidth. f1 =
1
2 RF (CF + CS + CM + CD)
CF
1
f2 =
2 RFCF
VOLTAGE NOISE (nV/ Hz)

fCR
f3 =
RF (CF + CS + CM + CD)/CF

RF NOISE

VEN (CF + CS + CM + CD)/CF f3

IPHOTO RSH = 1011Ω CM
f2
CS
CD
CM VOUT f1

VEN
NOISE DUE TO AMPLIFIER
07756-048

07756-043

VB
FREQUENCY (Hz)
Figure 63. Wideband Photodiode Preamp
Figure 64. Photodiode Voltage Noise Contributions

Rev. G | Page 25 of 31
ADA4817-1/ADA4817-2 Data Sheet
45
The loop transmission zero introduced by CF limits the
40
amplification. The noise gain bandwidth extends past the pre-
35 amp signal bandwidth and is eventually rolled off by the decreasing
30 loop gain of the amplifier. The current equivalent noise from the
MAGNITUDE (dB)

25 inverting terminal is typically negligible for most applications.

20 The innovative architecture used in the ADA4817-1/ADA4817-2
15
makes balancing both inputs unnecessary, as opposed to traditional
FET input amplifiers. Therefore, minimizing the impedance
10
seen from the noninverting terminal to ground at all frequencies is
5
G = 63V/V critical for optimal noise performance.
R = 100Ω

07756-051
0 V L = 10V
S
VOUT = 6V p-p Integrating the square of the output voltage noise spectral
–5
0.1 1 10 100 1000 density over frequency and then taking the square root allows
FREQUENCY (MHz)
the user to obtain the total rms output noise of the preamp.
Figure 65. Photodiode Preamp Frequency Response Table 9 summarizes approximations for the amplifier and
The pole in the loop transmission translates to a zero in the feedback and source resistances. Noise components for an
noise gain of the amplifier, leading to an amplification of the example preamp with RF = 50 kΩ, CS = 30 pF, and CF = 0.5 pF
input voltage noise over frequency. (bandwidth of about 6.4 MHz) are also listed. VEN is the
equivalent voltage noise and IEN is the equivalent current
noise.

Table 9. RMS Noise Contributions of Photodiode Preamp

Contributor Expression RMS Noise with RF = 50 kΩ, CS = 30 pF, CF = 0.5 pF
RF 4kT × RF × f 2 × 1.57 94 µV

VEN Amp CS + C M + C D + C F 777.5 µV

VEN × × f 3 × 1.57
CF
IEN Amp IEN × RF × f 2 × 1.57 0.4 µV

Total 783 µV

Rev. G | Page 26 of 31
Data Sheet ADA4817-1/ADA4817-2
HIGH SPEED JFET INPUT INSTRUMENTATION The system bandwidth for G = 1 is 400 MHz. For gains higher
AMPLIFIER than 2, the bandwidth is set by the preamp, and it can be
approximated by
Figure 66 shows an example of a high speed instrumentation
amplifier with a high input impedance using the ADA4817-1/ In-amp−3 dB = (fCR × RG)/(2 × RF)
ADA4817-2. The dc transfer function is The match of resistor ratios, R1:R2 to R3:R4, primarily determine
 2R  the common-mode rejection of the in-amp and it is estimated by
VOUT =(VN − VP )  1 + F  (16)
 RG  VO
=
( δ1 − δ2 ) (17)
For G = 1, it is recommended that the feedback resistors for the VCM (1 + δ1) δ2
two preamps be set to 0 Ω and the gain resistor be open. The summing junction impedance for the preamps is equal
to RF || 0.5(RG). Keep this value relatively low to improve the
bandwidth response like in the previous example.
VCC

0.1µF 10µF
RS1

R2
VN 350Ω
ADA4817-2
U1

VCC
0.1µF 10µF

VEE 0.1µF 10µF

R1
350Ω

RF = 500Ω
ADA4817-1 VO
RG
R3
RF = 500Ω 350Ω
0.1µF 10µF
VCC
R4
350Ω VEE

0.1µF 10µF

ADA4817-2
RS2 U2

VP 0.1µF 10µF
07756-050

VEE

Figure 66. High Speed Instrumentation Amplifier

Rev. G | Page 27 of 31
ADA4817-1/ADA4817-2 Data Sheet
ACTIVE LOW-PASS FILTER (LPF) Resistor values are kept low for minimal noise contribution,
offset voltage, and optimal frequency response. Due to the low
Active low-pass filters are used in many applications such as
capacitance values used in the filter circuit, the PCB layout and
antialiasing filters and high frequency communication
minimization of parasitics is critical. A few picofarads can detune
intermediate frequency (IF) strips.
the corner frequency, fC, of the filter. The capacitor values
With a 410 MHz gain bandwidth product and high slew rate, shown in Figure 68 actually incorporate some stray PCB
the ADA4817-1/ADA4817-2 is an ideal candidate for active capacitance.
filters. Moreover, thanks to the low input bias current provided
Capacitor selection is critical for optimal filter performance.
by the FET stage, the ADA4817-1/ADA4817-2 eliminate any dc
Capacitors with low temperature coefficients, such as NPO
errors. Figure 67 shows the frequency response of 90 MHz and
ceramic capacitors and silver mica, are good choices for filter
45 MHz LPFs. In addition to the bandwidth requirements, the slew
rate must be capable of supporting the full power bandwidth of the elements.
filter. In this case, a 90 MHz bandwidth with a 2 V p-p output 15
12
swing requires at least 870 V/µs. This performance is achievable 9
6
at 90 MHz only because of the wide bandwidth and high slew 3 OUT2, f = 90MHz
rate of the ADA4817-1/ADA4817-2. 0
–3 OUT1, f = 90MHz

MAGNITUDE (dB)
–6
The circuit shown in Figure 68 is a 4-pole, Sallen-Key LPF. The –9
filter comprises two identical cascaded Sallen-Key LPF sections, –12
–15 OUT1, f = 45MHz
each with a fixed gain of G = 2. The net gain of the filter is equal –18
–21
to G = 4 or 12 dB. The actual gain shown in Figure 67 is 12 dB. –24
OUT2, f = 45MHz

This gain does not take into account the output voltage being –27
–30
divided in half by the series matching termination resistor, RT, –33
–36
and the load resistor. –39
–42

07756-062
Setting the resistors equal to each other greatly simplifies the 100k 1M 10M 100M 1G

design equations for the Sallen-Key filter. To achieve 90 MHz,

FREQUENCY (Hz)
Figure 67. Low-Pass Filter Response
set the R value to 182 Ω. However, if the R value is doubled, the
corner frequency is cut in half to 45 MHz, which is a
straightforward approach to tune the filter by multiplying the R
value (182 Ω) by the ratio of 90 MHz and the new corner
frequency in megahertz. Figure 67 shows the output of each stage
of the filter and the two different filters corresponding to R =
182 Ω and R = 365 Ω. It is not recommended to increase the
corner frequency beyond 90 MHz due to bandwidth and slew
rate limitations, unless unity-gain stages are acceptable.
C1
3.9pF C3
3.9pF

+5V 10µF
+5V 10µF

0.1µF
U1 0.1µF
R R U2
+IN1 R R RT
RT C2 49.9Ω
49.9Ω 5.6pF 10µF OUT1 C4 OUT2
5.6pF 10µF

0.1µF
0.1µF
–5V
–5V
R2 R1
348Ω 348Ω
07756-054

R4 R3
348Ω 348Ω

Figure 68. 4-Pole, Sallen-Key LPF (ADA4817-2)

Rev. G | Page 28 of 31
Data Sheet ADA4817-1/ADA4817-2
1.2
0.15

0.8 90MHz
0.10 90MHz
45MHz
45MHz
0.4
0.05

VOLTAGE (V)
VOLTAGE (V)

0 0

–0.05 –0.4

–0.10 –0.8

07756-064
07756-063
–0.15 –1.2
TIME (5ns/DIV) TIME (5ns/DIV)

Figure 69. Small Signal Transient Response (Low-Pass Filter) Figure 70. Large Signal Transient Response (Low-Pass Filter)

Rev. G | Page 29 of 31
ADA4817-1/ADA4817-2 Data Sheet

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
1.84
3.10
1.74
3.00 SQ
0.50 1.64
2.90
BSC
5 8

PIN 1 INDEX EXPOSED 1.55

AREA PAD
1.45
0.50 1.35
0.40
0.30
4 1
TOP VIEW BOTTOM VIEW
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)

0.80 FOR PROPER CONNECTION OF

0.75 SIDE VIEW 0.05 MAX THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
0.70 0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.30 0.08
PLANE 0.25 0.203 REF

08-17-2018-A
0.20
PKG-003886

COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4

Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
5.00
4.90 2.29
4.80 0.356

8 5 6.20
4.00 6.00
3.90 5.80 2.29
3.80 0.457
1 4

FOR PROPER CONNECTION OF

1.27 BSC BOTTOM VIEW THE EXPOSED PAD, REFER TO
3.81 REF THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
TOP VIEW SECTION OF THIS DATA SHEET.
1.75 1.65 0.50 45°
1.35 1.25 0.25
0.25
0.17
0.10 MAX
SEATING
PLANE 0.51 0.05 NOM 8°
1.04 REF
COPLANARITY 0° 1.27
0.31 0.10 0.40
06-02-2011-B

COMPLIANT TO JEDEC STANDARDS MS-012-A A

Figure 72. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
(RD-8-1)
Dimensions shown in millimeters

Rev. G | Page 30 of 31
Data Sheet ADA4817-1/ADA4817-2
DETAIL A
(JEDEC 95)
4.10 0.35
4.00 SQ 0.30
PIN 1
INDICATOR 3.90 0.25
AREA
P IN 1
13 16 IN D IC ATO R AR E A OP T IO N S
0.65 (SEE DETAIL A)

BSC 12 1

*2.40
EXPOSED
PAD 2.35 SQ
2.30
9 4

0.50 8 5
0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.30
0.80 FOR PROPER CONNECTION OF
0.75 SIDE VIEW THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70 FUNCTION DESCRIPTIONS
0.02 NOM
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE

08-24-2018-C
0.20 REF
PKG-004024

*COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3

WITH EXCEPTION TO THE EXPOSED PAD

Figure 73.16-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-20)
Dimensions shown in millimeters

ORDERING GUIDE
Temperature Package Ordering Marking
Model 1 Range Package Description Option Quantity Code
ADA4817-1ACPZ-RL −40°C to +105°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 5000 H1F
ADA4817-1ACPZ-R7 −40°C to +105°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 1500 H1F
ADA4817-1ARDZ −40°C to +105°C 8-Lead Standard Small Outline Package with Exposed Pad RD-8-1 1
ADA4817-1ARDZ-RL −40°C to +105°C 8-Lead Standard Small Outline Package with Exposed Pad RD-8-1 2500
ADA4817-1ARDZ-R7 −40°C to +105°C 8-Lead Standard Small Outline Package with Exposed Pad RD-8-1 1000
ADA4817-2ACPZ-RL −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-20 5000
ADA4817-2ACPZ-R7 −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-20 1500
ADA4817-2ACP-EBZ Evaluation Board for 16-Lead LFCSP
1
Z = RoHS Compliant Part.

©2008–2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D07756-0-4/19(G)

Rev. G | Page 31 of 31