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VHDL code for full subtractor using behavioral method – full

code & explanation
Deepak Joshi   |   Published November 9, 2018   |   Updated June 20, 2020

In this post, we will take a look at implementing the VHDL code

for full subtractor using behavioral method. We have seen the
design for a full subtractor in our digital electronics course.
Here, first, we will explain the logic and then the syntax. For the
full code, scroll down.

Contents 
1. Explanation of the VHDL code for full subtractor using behavioral
method. How does the code work?
1.1. Logic circuit of the full subtractor
1.2. Truth table of the full subtractor
2. VHDL code for full subtractor using behavioral method
3. Testbench
4. Simulation result
5. RTL Schematic

Explanation of the VHDL code

for full subtractor using behavioral
method. How does the code work?
Logic circuit of the full subtractor

Truth table of the full subtractor

A B D DIFFERENCE BORROW

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1
 1 0 0 1 0

1 0 1 0 0 View Course Path

1 1 0 0 0

1 1 1 1 1

In the VHDL code for full adder post, we made the use of if-else
commands. Here, we will make use of if-elsif commands.
VHDL code for full subtractor using
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behavioral method
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FULLSUBTRACTOR_BEHAVIORAL_SOURCE is

Port ( A : in  STD_LOGIC_VECTOR (2 downto

0);

Y : out  STD_LOGIC_VECTOR (1 downto 0));

end FULLSUBTRACTOR_BEHAVIORAL_SOURCE;

architecture Behavioral of
FULLSUBTRACTOR_BEHAVIORAL_SOURCE is

begin
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VHDL Course
process (A)
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VHDL design units – Syntax of a

begin VHDL program

What is VLSI? And what are the job

opportunities for a VLSI student?
if (A = "001" or A = "010" or A = "111") Data Types in VHDL
then
Dataflow modeling architecture in
VHDL
Y <= "11";
Behavioral modeling architecture in
VHDL
elsif (A = "011") then
Structural modeling architecture in
VHDL
Y <= "01";
Operators in VHDL – Easy
explanation
elsif (A = "100") then
Testbenches in VHDL – A complete
guide with steps
Y <= "10";
VHDL code for all logic gates using
dataflow method – full code and
else
explanation

VHDL code for half adder & full

Y <= "00";
adder using dataflow method – full
code & explanation

VHDL d f f ll b & h lf
 VHDL code for full subtractor & half
end if;
subtractor using dataflow method
– full code & explanation
end process; View Course Path
VHDL code for multiplexer using
dataflow method – full code and
end Behavioral; explanation

VHDL code for demultiplexer using

dataflow method – full code &
  Share and Support
Testbench
View Course Path
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_sub_tb is
end entity;

architecture tb of full_sub_tb is
component FULLSUBTRACTOR_BEHAVIORAL_SOURCE
is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (1 downto 0));
end component;

signal A: STD_LOGIC_VECTOR(2 downto 0);

signal Y: STD_LOGIC_VECTOR(1 downto 0);

begin

uut: FULLSUBTRACTOR_BEHAVIORAL_SOURCE port

map(
A => A, Y => Y);

stim:process
begin

A <= "000";
wait for 20 ns;

A <= "001";
wait for 20 ns;

A <= "010";
wait for 20 ns;

A <= "011";
wait for 20 ns;

A <= "100";
wait for 20 ns;

A <= "101";
wait for 20 ns;

A <= "110";
wait for 20 ns;

A <= "111";
 wait for 20 ns;
wait;
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end process;

end tb;

Simulation result

Full Subtractor Behavioral-waveform

RTL Schematic

Full Subtractor Behavioral-RTL

As always, if you have any queries, we would love to address

them. Just drop in a comment in the comments section below.

About the author

Deepak Joshi
Deepak is an undergrad student in ECE from Bhagwan Parshuram Institute of
Technology, Delhi. He is working as a student researcher in the field of antenna
designing for 5G communication. He is passionate about electronics and has good
skills in modeling digital circuits using VHDL. His passion and interest in electronics
led him to dive into embedded systems and IoT.

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