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5 Stage Pipelined RISCV Processor in RTL

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 5 Stage Pipelined RISCV Processor in RTL
Gaurav Srivastav Divya Sareen
M.Tech, IIIT Delhi M.Tech, IIIT Delhi
Department of ECE Department of ECE
Delhi, India Delhi, India
Abstract— This paper consists of RISCV (RV32I)
implementation in Verilog. We have implemented the processor
with 5 stage pipelines, i.e., fetch, decode, execute, memory,
writeback. The processor is designed using Harvard
Architecture i.e., two separate memories have been used for
storing instructions & data. To achieve better performance
Bypassing and stalling logic along with 10 different instructions
are implemented in this project. We have implemented 32-bit
architecture of RV321.
Keywords— RISCV(RV32I), pipeline, RTL, Xilinx Vivado
Introduction
RISC processor is a design technique which is used to
reducing the amount of area required, complexity of
instruction set, instruction cycle and cost during the
implementation of the design. After the fast growth of silicon
technology and fall in price of IC’s. RISC processor usage
increased rapidly in all areas of technology. RISC-V is an
open standard instruction set architecture (ISA) which is based
on established reduced instruction set computer (RISC)
principles. RISC-V provides an open-source license, which
means anyone can use it without paying anything. This
architecture is generally of 3 variants, i.e., 32-bit, 64-bit and
128-bit. But in this project, we are using 32-bit architecture.
It’s a load-store architecture just like RISC processor which
uses only registers. Other operations can be done on register-
to-register criteria [1].
The main aim of making RISC-V processor is that the
designer wanted the processor should be user friendly, could
be studied by anyone, could be purchased by anyone and
designer could make their own processors of their own
demand. Since ARM, Intel processor is very costly the
infrastructure required for learning and testing anything on it
costs a fortune. Moreover, the ARM providers don’t allow
much transparencies so that designer could know everything.
The framing of this paper is as below. Section I describes
about Implementation of whole code, how the code files are
working and how they are linked with each other. In
implementation we described all logics of operation. Section
II describes about instruction format in which formats of
different instruction showed. Section III describes about
simulation and results of our project.
Hanan Hamid
B.Tech IIIT, Delhi
Department of ECE
Delhi, India
Processor Architecture
A. Fetch Stage
Fetch is the 1st stage of a processor pipeline. It uses a
program counter that helps in fetching the instruction
code from the insruuction memory. The program
counter is incremented by 4 after every instruction.
B. Decode Stage
In the decode stage the instruction that has been fetched
is decoded and the values are fetched from the registers
mentioned in the instruction.
C. Execute Stage
This stage will get the values from the decode stage &
then perform the operations according to instruction
D. Memory
Memory stage in the processor will perform the
operations of memory access & forward the signals
which are not related with memory
E. Writeback
Writeback stage is for perform the write operations on
the registers where we have to store the new value.
I. IMPLEMENTATION
We have implemented this project in Verilog HDL.
Verilog is a hardware description language (HDL), widely
used for describing electronic hardware. We can design and
test abstract hardware circuits using Verilog without having to
worry about a specific technology. The design of the RISCV
architecture is done using the Register Transfer Level (RTL).
In RTL code the circuit is defined using operations and
transfer of data between different registers. This code can then
be synthesized to generate a schematic which produces a
graphical representation of the modules used and the
connections in-between them.
A. Code Modules & Working
Since we have implemented it with 5 stage pipelines, we have
divided our program in 5 stages i.e., fetch, decode, Alu,
memory, writeback. & Processor. Processor module contains
all the connections and instantiations of all 5 stages of the
pipeline and the corresponding modules that are required for
the functioning of the pipeline. This includes the instruction
memory, the data memory and the register files. The
testbench is instantiated with this main file for testing the
code outputs. A Clock is defined in testbench & used for
operations of the processor. On running the code first, the
main file is called by the test bench along with clock, program
counter & a starting pulse signal to start the working of the
processor. First of all, the instruction memory is loaded with
the 32-bit instructions that are to be executed on the
processor.
Then the main file which is Processor.v is first calling the
fetch stage, with the value of program counter. The fetch
stage uses the value of program counter (PC) to fetch the
respective instruction from the instruction memory. After
every fetch the program counter is automatically incremented
to PC+4 (in case of byte addressable memory) and PC+1 (in
case of word addressable memory), in our implementation we
are using the latter for updating PC.
Now the Processor.v file passes the fetched instruction from
instruction fetch stage to the decode stage. In the decode stage
the instruction is broken down into different segments
according to the requirements of RISC RV321 instruction set
architecture. The Decode stage prepares the required
information like source & destination registers used by the
instruction, which operation the instruction is performing &
if any offset is used the offset value along with sign extension
format for the next stage that is the ALU stage.
The ALU stage is for performing the arithmetic & logical
operations, it performs the required operation that is
mentioned in the instruction & if the instruction is branch
type then ALU calculates the next value of the program
counter taking for the branch. After all of these operations are
done ALU sends the output to main file which passes the
information to the Memory stage.
The function of the Memory stage is to perform memory
accessing operations for load and store instructions.
Otherwise, it forwards the ALU output to next stage that is
the Writeback stage.
At last, the output of Memory stage is sent to the Writeback
stage where the writing of register files is done for that
particular instruction.
All of this process is carried out sequentially that is why it is
called as a pipeline.
Processor Architecture [3]
Implementation of Branch Module
While decoding the instruction in the Decode stage if the
instruction is found to be a branch type instruction, then, we
calculate the value of program counter & check the condition
of jump in the ALU stage. We continuously give it to the fetch
stage, & in fetch stage if condition is true for jump, then we
are manipulating the program counter with the new program
counter value. Then the fetch stage starts fetching the next
instruction from the new value of program counter. Along
with this the speculative instructions that were already
fetched are flushed from the pipeline. For flushing those
instructions, we are disabling the memory and writeback
operations when the branch is taken.
Implementation of Stall
Stall logic is required to overcome the data hazard by stalling
the pipeline until the value of the source register used is
updated to its correct value by the previous instruction. For
example, if any dependency like RAW hazard comes in
picture so to solve that we require a control logic to freeze the
stages until the previous stages has finished with required
values
We have implemented the stall logic by sensing the inflight
register in the pipeline. We are continuously tracking the
register after each stage & if the source register in decode
stage is same as any inflight destination register in any stage,
then we are making the stall signal high & inserting NOP
instructions from fetch stage to flow through the pipeline and
delay the instruction until the dependency is over.
Implementation of Bypass
Bypassing/Forwarding is the method to bypass the values of
one instruction to the next instruction which is using the
updated value of the register before the first instruction has
reached the writeback stage.
For implementing it we are tracking the inflight registers
same as stall and if inflight destination register is same as
source register, then we are forwarding the output of that
stage directly to decode stage for the next instruction. By
means of bypassing we are able to complete the execution in
a smaller number of clock cycles.
 II. INSTRUCTION FORMAT 31-20 19-15 14-12 11-7 6-2 1-0
We are using the standard provided format of all instructions
which is as below [2]. offset[11:0] Rs1 010 rd 00000 11

a) AND Operation h) SW
Performs bitwise AND operation on registers rs1 and rs2 and Store 32-bit values from the low bits of register rs2
put the result in rd
31-25 24- 19-15 14-12 11- 6-2 1-0
31-27 26- 24- 19-15 14- 11- 6-2 1-0 20 7
25 20 12 7 Offset Rs2 Rs1 010 rd 01000 11
00000 00 Rs2 Rs1 111 rd 01100 11 [6:0]

i) SLL
b) OR
Perform the logical left shift on the value of register rs1 by the
Performs bitwise OR operation on registers rs1 and rs2 and shift amount held in the lower 5 bit of register rs2
put the result in rd
31-27 26- 24- 19-15 14- 11- 6-2 1-0
31-27 26- 24- 19-15 14- 11- 6-2 1-0 25 20 12 7
25 20 12 7
00000 00 Rs2 Rs1 001 rd 01100 11
00000 00 Rs2 Rs1 110 rd 01100 11

j) SRA
c) ADD
Perform the arithmetic right shift on the value of register rs1
Adds the registers rs1 & rs2 and stores the result in rd by the shift amount held in lower 5 bit of register rs2
31-27 26- 24- 19-15 14- 11- 6-2 1-0 31-27 26- 24- 19-15 14- 11- 6-2 1-0
25 20 12 7 25 20 12 7
00000 00 Rs2 Rs1 000 rd 01100 11 01000 00 Rs2 Rs1 101 rd 01100 11

d) SUB k) MAC
Subtract the register rs1 and rs2 and put the result in rd rd<---rd+(rs1*rs2)
31-27 26- 24- 19-15 14- 11- 6-2 1-0 31-27 26- 24- 19- 14- 11- 6-2 1-0
25 20 12 7 25 20 15 12 7
01000 00 Rs2 Rs1 000 rd 01100 11 00000 00 Rs2 Rs1 000 rd 11111 11

e) ADDI
Add the sign extended 12-bit given offset with register rs1 and
III. SIMULATION & RESULTS
put the result in rd
Input Assembly code with instruction
31-20 19-15 14-12 11-7 6-2 1-0

Imm[11:0] Rs1 000 rd 00100 11 Assembly Binary(in hexadecimal)

LW R1,0(R0) 00002083
f) BEQ ADD R2,R1,R3 00308133
Take branch if rs1==rs2 OR R4,R1,R0 0000e233
31-25 24- 19-15 14-12 11- 6-2 1-0 ADDI R2,R4,5 00520113
20 7
OR R6,R4,R5 00526333
Offset Rs2 Rs1 111 rd 01100 11
[6:0] ADD R7,R8,R9 009403b3
SUB R12,R10,R11 40b50633
g) LW
SW R20,R20,0 014a2023
Load the load the 32-bit from memory and store it in register
rd
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LW R16,R15,5 0057d403 R25 25 R25 0

SLL R19,R20,R21 01499ab3
SRA R22,R23,R25 417b5cb3
Conclusion
We have initialized all the registers like R0=0, R1=1, We have designed and implemented 5 Stage pipeline using
R2=2…& memory like with their address & the output of RISCV processor using Verilog HDL on VIVADO tool. We
above code is as given. have used ISIM to perform simulations of our project.
INITIAL AFTER SIMULATION
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