ISSCC 2023 / SESSION 1 / PLENARY / OVERVIEW

Session 1 Overview: Plenary

INVITED PAPERS

Chair: Eugenio Cantatore Associate Chair: Piet Wambacq

Eindhoven University of Technology imec, Heverlee, Belgium
Eindhoven, The Netherlands ISSCC International Technical
ISSCC Conference Chair Program Chair

8:30 AM
FORMAL OPENING OF THE CONFERENCE
The Plenary Session starts with welcoming remarks and introduction from the Conference Chair, Eugenio Cantatore, followed by the International Technical
Program Chair, Piet Wambacq, providing an overview of ISSCC 2023.
The Plenary Session will feature four distinguished keynote speakers, who are leaders or pioneers in their domain, covering together a broad spectrum of our
industry. An Awards Ceremony that recognizes major technical and professional accomplishments presented by the IEEE, Solid-State Circuits Society (SSCS),
and ISSCC, will take place after the first two Plenary talks. Plenary presentations will be live streamed at the Conference and broadcast live on various platforms,
including the ISSCC YouTube Channel.
The first plenary talk “Innovation For the Next Decade of Compute Efficiency”, by Lisa Su, Chair and Chief Executive Officer at AMD, explains how to innovate
in high-performance computing, which is becoming an increasingly indispensable part of modern life. Innovation in this field is only possible with an effective,
holistic strategy to improve energy efficiency, which is described in this talk.
The second plenary talk “Shape the World with Mixed-Signal Integrated Circuits, - Past, Present, and Future”, by Akira Matsuzawa, Professor Emeritus of Tokyo
Institute of Technology and CEO of Tech Idea, shows how over the past decades digitalization in many applications has taken benefit of the performance, power
and cost improvements of mixed-signal integrated circuits. Further, an outlook to emerging applications and developments of mixed-signal circuits is given.
The third plenary talk “EU Chips Act Drives Pan-European Full-Stack Innovation Partnerships”, by Jo De Boeck, Executive Vice-President and Chief Strategy
Officer at imec, gives a projection on how the European Chips Act, which targets to increase Europe’s global semiconductor production, can trigger innovation
in the entire semiconductor ecosystem ranging from chip processing to system design, impacting a broad field of application domains such as heterogeneous
cloud and distributed computing, connectivity, automotive and health.
The last plenary talk “5G Drives Exponential Increase in Processing Needs Across all Industries”, by Erik Ekudden, Senior Vice President and Chief Technology
Officer at Ericsson, explains how 5G - and its successor 6G - drives an exponential increase in the collection, processing and transport of data in and by vehicles,
industrial equipment and consumer products, which are becoming ever more intelligent and connected. The talk will address whether the semiconductor industry
is ready to tackle these challenges.
We hope that you will find these presentations informative, inspiring, and motivating. Enjoy!

8:45 AM
1.1 Innovation For the Next Decade of Compute Efficiency
Lisa Su, Chair and Chief Executive Officer, AMD, Austin, TX
Although traditional scaling has slowed over the past decade, we have made tremendous progress as an industry with new
approaches including chiplet-based architectures, domain-specific accelerators, and advanced packaging technologies which have
enabled major milestones including the first exascale supercomputers. As we look into the future, we need to accelerate the pace
of innovation to drive the next decade of advancement in high-performance computing. By far, the largest limiting factor to delivering
continued compounded growth in computation power is energy efficiency. In this paper, we highlight a holistic strategy for
accelerating innovation in energy efficiency required for next-generation high-performance computing and ultimately achieving
zettascale performance. These approaches will be built on continued innovation in process technologies, modular chiplet
architectures, and advanced packaging. Fully meeting the challenge will require new dimensions of improvement through extending
domain-specific architectures to accelerate core algorithms in combination with wide-scale deployment of AI across all aspects of
the system from transistors to software.

6 • 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

 ISSCC 2023 / February 20, 2023 / 8:30 AM

1
9:20 AM
1.2 Shape the World with Mixed-Signal Integrated Circuits - Past, Present, and Future
Akira Matsuzawa, Professor Emeritus of Tokyo Institute of Technology and CEO of Tech Idea, Kawasaki, Japan
The past 50 years has been an era in which analog equipment has been replaced by digital counterparts. Audio, TV, video,
camcorder, camera, recording, wired connection, and wireless communication have been subject to digitization. The digitization
of these devices and systems was due to the technological shift from bipolar to CMOS, and to the development of logic and
memory circuits supported by scaling laws. In addition, design innovation in mixed-signal integrated circuits such as ADCs and
DACs has shown to be indispensable. This talk will look back on the digitization of equipment and the mixed-signal integrated
circuit technology that contributed to it. Further, we will look forward to future applications and developments.

9:55 AM
ISSCC, SSCS, IEEE AWARD PRESENTATIONS
10:20 AM
BREAK

10:40 AM
1.3 EU Chips Act Drives Pan-European Full-Stack Innovation Partnerships
Jo De Boeck, Executive Vice President and Chief Strategy Officer, imec & KU Leuven, Leuven, Belgium
In every aspect of our life and society, semiconductors play a major role. The pandemic in conjunction with supply chain hiccups
and geopolitical tensions made all regions realize that they need to revisit their presence in the semiconductor value chain. The
European Commission projected the ambition of achieving a 20% share of the global semiconductor production by 2030.
Europe can leverage existing strengths such as, among others, the unique position of equipment companies and leadership
positions in 300mm semiconductor technology R&D. The Chips-for-Europe initiative will invest in pilot lines and ecosystems
for chip manufacturing, embracing leading-edge and first-of-a-kind technologies. The pilot lines will allow early exploration of
the potential impact of new technology features in advanced chip and system architectures. This will trigger increased demand
and accelerate industrial uptake of the novel technologies. This type of innovation loop is also essential for deep-tech start-ups
building their unique value proposition. The full-stack, networked model of industry collaboration is at the core of the EU Chips
Act ambition and will impact different application domains such as heterogeneous cloud and distributed computing, connectivity,
automotive, and health.
It is crucial for all this innovation potential that we, as an industry, consider that semiconductor manufacturing is resource-
intensive with respect to energy, water, chemicals, and raw materials. Design-technology co-optimization (DTCO) and
System-Technology co-optimization (STCO) methodologies can develop a framework for early sustainability assessments of
logic technologies. Finally, we urgently need to get the message across that climate, health, safety, and human connectedness
all require complex digital backbones, if we want to stand a chance of attracting the right talent.

11:15 AM
1.4 5G Drives Exponential Increase in Processing Needs Across all Industries
Erik Ekudden, Senior Vice President & Chief Technology Officer, Ericsson, Kista, Sweden
Across essentially all industrial sectors, advanced semiconductor technology is the key enabler for innovations in customer
offerings and internal efficiencies. The increase in the value of data and the related push for AI are examples of forces that
increase the demand for compute power, which translates to more complex and powerful silicon. Moore’s Law, supported by
rapidly evolving semiconductor technology and ever more advanced building practices and assembly technologies, has met the
need for decades.
But what is driving 5G today? If we look at the processing requirements, it is the digital front-end, physical layer processing,
and beam forming. Back in 2010, LTE/4G was a 20MHz carrier with two receive and two transmit branches, and there was a
transmission time interval of one millisecond. Fast forward to where we are today on 5G with massive MIMO, we typically have
100MHz carrier bandwidth. That is a factor of five increase. We have 64 transmitter and 64 receiver radios, which is an increase
by a factor of 32, and the transmission time is down to 0.5 milliseconds. In other words, there is only half the time to do 160
times more processing. This is driving an exponential increase in processing needs across the telecom business today, and will
continue to do so as we race towards 6G. This talk will address whether the semiconductor industry is ready to tackle these
challenges.

11:50 AM
PRESENTATION TO PLENARY SPEAKERS
11:55 AM
CONCLUSION

DIGEST OF TECHNICAL PAPERS • 7

ISSCC 2023 / SESSION 1 / PLENARY / 1.1
1.1 Innovation For the Next Decade of Compute Efficiency
Lisa Su1, Sam Naffziger2
AMD, Austin, TX1
AMD, Fort Collins, CO2
1.1 Introduction
With high-performance computing becoming an increasingly essential part of modern
life, efficiently delivering improvements in compute performance is the defining challenge
for our industry. The rapid growth in the number of connected devices is creating orders-
of-magnitude more data, requiring greater levels of compute to generate actionable
insights for personal use and businesses. At the same time, supercomputers have
become critical to enable research breakthroughs in fields including climate change,
renewable energy development, infectious disease research, complex life science
modeling, and much more.
Over the past two decades the industry has consistently doubled performance every 2
to 2.5 years through continued innovation, even as Moore’s Law has slowed down
(Figures 1.1.1 and 1.1.2). These increases in compute capability were realized through
architectural innovation, process technology gains, larger die sizes, and higher power
consumption [1]. It is now clear that energy consumption is the primary limiting factor
in maintaining the historical rate of performance improvements. To continue
improvements in energy efficiency, there are three key pillars where innovation is
required: advances in the energy of the compute operations themselves (energy-per-
operation), advances in the energy required to access and store data in memory
(energy-per-memory bit), and advances in the energy required to communicate the
results externally (energy-per-communication bit). In recent years, we have seen that
performance-per-watt improvements across the computing landscape have slowed down
because it has become increasingly harder to scale the energy required across these
three pillars (Figures 1.1.3 and 1.1.4).
The enormity of this energy efficiency challenge is highlighted in supercomputing. As
Figure 1.1.5 shows, supercomputing trends have led the industry in performance and
energy efficiency over the past two decades. However, although the rate of improvement
of performance has been relatively constant, doubling every 1.2 years, the rate of
improvement in efficiency is less than half that of the rate of performance increase [6].
We have recently delivered the first supercomputer, delivering over an exaflop of
performance, which is a major milestone [23]. As an industry, we are now setting our
ambitions on the technology required to achieve zettascale computing. Assuming the
historical rate and pace of advances in performance and efficiency are maintained over
the next decade, we could achieve a zettaflop of computing in ~10 years — but it would
require a half a Gigawatt of electricity, the equivalent output of half a nuclear power plant
(Figure 1.1.6). This is clearly not a viable solution!
In order for our industry to deliver progress over the coming decade that matches or
exceeds the advances of the past decade, we must embark on new vectors of physical
design, architectural innovation, and algorithmic improvements which prioritize energy
efficiency.
In addition to continuing to leverage Moore’s Law to deliver advanced process nodes,
the importance of new package technologies including further innovation around chiplets,
as well as new processor architectures and techniques to bring memory closer to
compute are critical. We must also reduce communications overhead by innovating in
system design and more efficient on-package and off-package communication. It is also
critical that we aggressive apply artificial intelligence throughout every aspect of the
design and system.
2. Process and Packaging Technology Advances Remain Essential
Silicon process improvements will always be a key component of compute efficiency
gains, as the energy per operation for logic gates continues to improve and provide
critical efficiency gains as shown in Figure 1.1.7 [8][9]. However, we have seen density
improvements slow down after the 7nm node and energy efficiency flatten at the 5nm
node. In addition, the increasing process complexity of advanced nodes has led to the
cost per mm2 growing significantly with each successive process generation (Figure
1.1.8). As shown in the figure, larger die are more impacted by the increasing cost trend.
Thus, it is increasingly attractive to use modular chiplet architectures where the most-
advanced nodes are only used for the most compute-heavy IP which get the most gains
from using the latest technology, and less advanced nodes are used for the IO and other
functions that do not benefit as much from the most-advanced node [10][11].
To continue advancing chiplet architectures over the next decade, innovation around the
die-to-die interconnect is critical. The aggregate bandwidths required between chiplets
continues to increase with each generation as performance requirements scale. This
8 • 2023 IEEE International Solid-State Circuits Conference
drives higher power consumption and requires significant improvements beyond where
the industry is at today with bandwidth density. As shown in Figure 1.1.9, there is a
continuum of linear and areal bandwidth density across classes of packaging approaches
used to connect chiplets. The industry is moving toward more advanced 2D and 2.5D
interconnects to enable smaller, lower power interfaces, but we will need to begin
adopting 3D construction more broadly in the future. As demonstrated by AMD with 3D
V-Cache [12] technology that stacks SRAM on top of a processor die, 3D stacking can
enable chiplet modularity across very high bandwidth internal interfaces with very low
overhead. To enable broader adoption of 3D construction in the future, significant
innovation is needed including dealing with the inevitable thermal challenges of increased
power density from stacking [13] and supporting the test requirements for known good
die (KGD) [14].
3. Improving the Efficiency of Memory
Another important area of innovation is improving the energy efficiency of moving data
between the processor and memory. The amount of energy consumed by moving data
between processor and memory is very much a function of both the type of memory and
how the memory is connected to the processor. Figure 1.1.10 shows the current state
of the art in memory bandwidth and energy efficiency. DDR5 is the workhorse memory
interface in modern servers [15]. In recent years, high bandwidth memory (HBM) has
become the memory of choice for the highest performance compute segments such as
GPU accelerators. HBM utilizes advanced packaging to deliver much higher bandwidth
and 3 to 4 times lower energy per bit than DDR5 [16]. The use of 3D stacking directly
on the compute die results in even higher bandwidth and lower energy per bit. AMD has
already demonstrated the benefits of this approach with our stacked SRAM V-cache
technology deployed for server and desktop products [12]. Extending this capability to
stacking of DRAM and potentially alternative DRAM-density memory technologies can
enable another order-of-magnitude reduction in data movement energy relative to HBM.
Another promising approach for addressing the memory efficiency challenge is to embed
special purpose compute data paths directly in the memory itself [17][18], also known
as Processing In Memory (PIM). The energy required to fetch a single bit from memory
is on the same order as the energy required to perform an entire 64b floating point
operation, so if there is limited reuse of the data retrieved from memory it can be much
more efficient to just perform the operation in the memory itself. Determining the right
set of operations that are candidates for this approach and crafting the software to exploit
them is non-trivial, but with up to an 85% savings in data movement energy this is a
promising technology for optimization in future systems.
4. Improving the Efficiency of IO
Improving the energy efficiency of communication between the processor and the outside
world including the network, a display, or output device is also critical. While the
increases in bit rates and the efficiency of external IO has been making impressive gains
over the years (Figure 1.1.11), when accounting for the lower loss (shorter, more
expensive) channels required to achieve those improvements, the results show much
more modest gains if not a flattening. This is problematic since system designs require
increasing numbers of compute, memory and storage devices tightly coupled for the
system scale computation of the future.
As copper connections become impractical, we will need to exploit optical interconnects
for system scale. To enable energy efficient use of those optical links, we will need to
exploit more efficient advanced packaging and 3D stacked communication channels
(Figure 1.1.12) coupled with optical interfaces. This requires innovations along two
parallel paths: co-packaged optics for long reach communication and advanced
packaging with chiplet architecture for system-in-package heterogeneous computation.
With UCIe as a new industry standard chiplet interface [20], an ecosystem can be enabled
such as shown in Figure 1.1.13 with the modular accelerator IP tightly coupled with
memory and general-purpose compute at minimum data movement power. For long
reach off-package communication, the future is optical, leveraging industry standard
protocols such as CXL [21] to support an ecosystem of power efficient, system scale
architectures. These optical links can be built on capabilities such as work presented in
this conference [22] which demonstrates a 2.5pJ/bit end-to-end efficiency, tightly
integrated on-package to enable the system architectures of the future.
5. Accelerators and AI
General purpose computation has been the backbone of compute infrastructure for
decades, but accelerators are becoming increasingly important. GPU accelerators have
been very effective in delivering significant improvements in compute efficiency. For
example, the AMD Instinct MI250 accelerator is the compute engine in the leading
exascale Frontier supercomputer [23]. In this case, an exaflop of compute was achieved
within a 21MW power budget delivering 2.5× the performance of the previous leading
supercomputer at 3.5× the power efficiency. This performance was achieved using a
highly parallel and efficient GPU architecture, and the implementation of special purpose
matrix multiply primitives to more efficiently perform the GEMM operations used in
Linpack and many HPC algorithms. This approximately halves the energy per 64b
978-1-6654-9016-0/23/$31.00 ©2023 IEEE

floating-point operation relative to legacy general-purpose floating-point operations,
enabling software algorithms that properly exploit these primitives to deliver much
higher compute efficiency.
This improvement is only the beginning. We have seen accelerators applied to
smartphones and PCs for many years, with significant energy savings for operations
like video encode and decode, display drivers, and image processing. These gains are
achieved through mapping the algorithm directly to hardware, eliminating the overhead
of general-purpose CPUs to support software programmability, and adapting the
precision of the operations to the algorithmic requirements. General-purpose
computation uses the IEEE floating point standard which provides plenty of precision
and has a wealth of software libraries to utilize it. However, the energy cost can be
high as shown in Figure 1.1.14 where reduced precision and domain-specific formats
can generate more than an order-of-magnitude more floating-point operations per
Joule. This approach is most evident in the machine learning training and inference
space where the race to reduced precision is driving new formats such as brain-float
16 (BF16) [24] and FP8 [25], yielding lower computation and data movement costs.
While these optimal-precision formats have been used in the AI application domain,
the ability to exploit these in the highly precise legacy scientific computing domain has
been less obvious until recently when research into AI surrogate models for HPC
acceleration started to take off [26].
The approach replaces some of the expensive and inefficient physics-based code with
AI-based surrogate models [27]. Practical HPC+AI applications combine both trained
AI approximations for the physics calculations with a final phase of pure physics code
to achieve the accurate result. An analogy can be made from travel as illustrated in
Figure 1.1.15, where driving from the Austin AMD office to San Francisco is like legacy
physics calculations, consuming a lot of time but getting exactly from point A to point
B. The AI-based approach zooms to a result that is close to correct (the airport), and
then leverages physics code (driving) to get to the exact destination.
The current methodology involves running the legacy physics-based calculations on
the initial phases of the simulation, which sources data used to train an AI inference
network. The dramatic accelerations in AI training performance (Figure 1.1.16) mean
that if we can leverage those gains for physics calculations, then this typically lengthy
calculation sequence can be greatly accelerated. Physics calculations can be used to
train a network which then enables the inference network, which runs 100s of times
faster than actual physics calculations, to converge close to the final solution. This
process is then repeated to get to the required accuracy (Figure 1.1.17). Researchers
are still in the early stages of optimizing these flows across more workloads, however
with an optimized platform with both parallel AI and HPC compute capability, it is
expected that solutions to these sorts of simulations can be reached in ½ to ⅓ the time
with the same amount of total hardware capability and power usage [27].
6. The Virtuous Cycle of Using AI Compute to Improve Compute Efficiency
The efficiency of AI computation has been improving at more than 10× the rate of
traditional CPU computation as shown in Figure 1.1.16. AI is also being applied to great
benefit to improve the efficiency of the processor design itself. EDA tools have started
to incorporate AI-driven approaches to Design Space Optimization (DSO) to drive
improvements in processor PPA. In an initial study, using the DSO.ai flow [28], we
have seen meaningful improvements in the result over the best tuned and optimized
designs produced by the most experienced design engineers. The AI-driven approach
currently searches the state space from synthesis to physical layout. As the AI
methodology pushes further upstream into logic refactoring, re-pipelining, and other
micro-architectural changes, the improvements are expected to grow dramatically.
And not only can AI benefit EDA tools and silicon implementation, but it has shown
excellent results in finding optimizations for low level library gates in ways that exceed
human capability [8]. These are a few examples of how applying the accelerating gains
in AI to traditional compute and design problems will enable a resurgence in compute
efficiency that is only beginning to be tapped. As AI capabilities become more pervasive,
the opportunities are boundless.
7. Conclusion
Our industry is at an inflection point – where energy efficiency is the single most
important driver of future improvements in compute. Innovations at every level
including silicon, packaging, design, architecture, software, and algorithms are required
for us to continue our rate and pace of compute deployment over the next decade. In
addition to focusing on the three main components of compute energy efficiency: the
efficiency of compute operations themselves, memory access energy, and
communication energy – the richest new opportunity to reach our efficiency goals
involves exploiting AI computation in new and disruptive ways. Only by fully exploiting
all of these approaches to the fullest extent will we have a pathway to zettascale
application-level performance within a 100MW envelope (Figure 1.1.18).
ISSCC 2023 / February 20, 2023 / 8:45 AM
Acknowledgement:
In addition to the global AMD engineering teams responsible for enabling the innovative 1
solutions that lay the foundation for the next generation of high-performance and
adaptive computing, the authors would also like to acknowledge the contributions of
Larry Bair, Tom Burd, Eric Dellinger, Nuwan Jayasena, Yohan Frans, Phil-James Roxby,
Mike Schulte, and Laurent White.
References:
[1] Su, Lisa T et al, “Multi-chip technologies to unleash computing performance gains
over the next decade”, IEDM 2017.
[2] Standard Performance Evaluation Corporation, “Published SPEC Benchmark
Results”, Available: https://spec.org/results.html
[3] K. Rupp, “50 Years of Microprocessor Trend Data”, Available:
https://github.com/karlrupp/microprocessor-trend-data
[4] Wikipedia, “List of Nvidia graphics processing units”, Available:
https://en.wikipedia.org/wiki/List_of_Nvidia_graphics_processing_units
[5] Wikipedia, “List of AMD graphics processing units”, Available:
https://en.wikipedia.org/wiki/List_of_AMD_graphics_processing_units
[6] TOP500.org, “Top #1 Systems”, Available: https://www.top500.org/resources/top-
systems/
[7] U.S. Dept. of Energy, “How Much Power Does A Nuclear Reactor Produce?”,
Available: https://www.energy.gov/ne/articles/infographic-how-much-power-does-
nuclear-reactor-produce
[8] M. Liu, “Unleashing the Future of Innovation”, ISSCC 2021.
[9] I. Kang, “The Art of Scaling: Distributed and Connected to Sustain the Golden Age
of Computation”, ISSCC 2022
[10] N. Beck, et. al., “’Zeppelin’: An SoC for Multichip Architectures”, ISSCC 2018.
[11] S. Naffziger, “AMD Chiplet Architecture for High-Performance Server and Desktop
Products”, ISSCC 2020.
[12] J. Wuu, et. al., “3D V-Cache: The Implementation of a Hybrid-Bonded 64MB
Stacked Cache for a 7nm x86-64 CPU”, ISSCC 2022.
[13] Salvi and Jain, “A Review of Recent Research on Heat Transfer in Three-
Dimensional Integrated Circuits (3-D ICs)”, IEEE Transactions on Components,
Packaging and Manufacturing Technology (Volume: 11, Issue: 5, May 2021).
[14] J. Rearick, “Tackling the test challenges of the chiplet revolution”, ITC 2021.
[15] B. Nitin et al., “DDR5 design challenges,” 2018 IEEE 22nd Workshop on Signal
and Power Integrity (SPI), 2018, pp. 1-4.
[16] C. Lee, et. al., “An Overview of the Development of a GPU with Integrated HBM on
Silicon Interposer”, 2016 IEEE 66th Electronic Components and Technology Conference
(ECTC), 2016, pp. 1439-1444.
[17] M. Lanuzza, et. al., “Cost-effective low-power processor-in-memory-based
reconfigurable datapath for multimedia applications,” ISLPED ‘05. Proceedings of the
2005 International Symposium on Low Power Electronics and Design, 2005, pp. 161-
166.
[18] S. Srikanth, et. al., “The Superstrider Architecture: Integrating Logic and Memory
Towards Non-Von Neumann Computing,” 2017 IEEE International Conference on
Rebooting Computing (ICRC), 2017, pp. 1-8.
[19] S. Mirabbasi, L.C. Fujino, K.C. Smith, “Through the Looking Glass—The 2022
Edition: Trends in solid-state circuits from ISSCC,” in IEEE Solid-State Circuits
Magazine, vol. 14, no. 1, pp. 54-72, winter 2022.
[20] UCIe Consortium, “UCIe 1.0 Specification”, Available:
https://www.uciexpress.org/specification
[21] CXL Consortium, “CXL 3.0 Specification”, Available:
https://www.computeexpresslink.org/download-the-specification
[22] M. Raj, et. al., “A 0.96pJ/b 7x50Gb/s-per-Fiber WDM Receiver with Stacked 7nm
CMOS and 45nm Silicon Photonic Dies”, ISSCC 2023.
[23] ORNL, “Frontier User Guide”, Available:
https://docs.olcf.ornl.gov/systems/frontier_user_guide.html
[24] S. Wang, P. Kanwar, “BFloat16: The Secret to High Performance on Cloud TPUs”,
Google Cloud Blog, August 2019, Available: https://cloud.google.com/blog/products/ai-
machine-learning/bfloat16-the-secret-to-highperformance-on-cloud-tpus
[25] N. Wang, et. al., “Training Deep Neural Networks with 8-bit Floating Point
Numbers,” 32nd Conference on Neural Information Processing Systems, 2018.
[26] P. Schwaller, et. al., “Molecular Transformer: A Model for Uncertainty-Calibrated
Chemical Reaction Prediction,” ACS Central Science, vol. 5, pp. 1572-1583, 2019.
[27] J. Yin, et. al., “Strategies for Integrating Deep Learning Surrogate Models with
HPC Simulation Applications.”, 2022 IEEE International Parallel and Distributed
Processing Symposium Workshops (IPDPSW), 2022, pp. 1-10.
[28] A. de Geus, “Catalyzing the Impossible”, ISSCC 2022.
DIGEST OF TECHNICAL PAPERS • 9
ISSCC 2023 / SESSION 1 / PLENARY / 1.1

Server 2P SpecIntRate Over Time GPU Single Precision FLOPs Over Time
100X 100,000 GF

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Figure 1.1.2: Trend in single precision (FP32) floating point operations for top-end industry
Figure 1.1.1: Trend in mainstream x86 2P server SpecIntRate scores over time [2]. GPUs over time [4][5].

Server Perf/Watt GPU Single Precision FLOPs/Watt

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Figure 1.1.3: The same mainstream 2P x86 server SpecIntRate performance trend as Figure
1.1.1, but divided by TDP [2][3]. Figure 1.1.4: The same GPU FP32 FLOP rate trend as Figure 1.1.2, but divided by TDP [4][5].

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top500.org list [6]. [6].

• 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

 ISSCC 2023 / February 20, 2023 / 8:45 AM

1
Technology Trends for Logic
Cost Per Yielded mm2 for a 350mm2, 250mm2, 100mm2 Die

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technology node (AMD internal analysis). node (AMD internal estimates).

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DIMMS 3D Hybrid Bond
 (HBM)
pj/bit ~12 ~3.5 ~0.2



 Image source: https:////commons.wikimedia.org/w
/wiki/File:SDRAM-Modul.jpg, Creative Commons 4.0.





Figure 1.1.10: Data movement energy for different integration methods, from traditional on-
Figure 1.1.9: Linear and areal bandwidth density for classes of packaging technology. board DIMMs to High Bandwidth Memory to 3D stacked.

Energy Efficiency of IO Interconnect Relative Bits/Joule

FOM = Power[mW]/(DataRate[Gbps]*
Power Efficiency vs. Year Channel Loss at Nyquist[dB])
1,000 100.00
60.0X

50.0X
Power Efficiency [mW/Gbps]

10.00
FOM [pJ/bit/dB]

100
40.0X

1.00
30.0X
10
0.10 20.0X

10.0X
1 0.01
2005 2008 2011 2014 2017 2020 2023 0 10 20 30 40 50 60
Year Channel Loss at Nyquist [dB] 0.0X
off-package copper off-package optical on-package advanced packaging 3D stacked

Figure 1.1.11: Interconnect power efficiency has improved consistently, but much of that is Figure 1.1.12: Reduced energy per bit from advanced packaging and integration will be critical
from reduced channel loss which is reaching the limits of improvement [19]. for efficiency gains.

DIGEST OF TECHNICAL PAPERS • 11

ISSCC 2023 / SESSION 1 / PLENARY / 1.1

Future Sysstem-in-Package Arch

c itecture Selected Floating Point Formats and Associated Energy Efficiency

Joule
FLOPs//J
Exponent Type
Ty Mantissa
35.0x

FP64 52
30.0x
Co-packaged
Optics FP32 23
High-speed Standardized 25.0x
Chip-to-Chip Interface (UCle)
TF32 10 20.0x
Memory
Heterogeneous FP16 10 15.0x
Compute cores
BF 16 7 10.0x
Domain Specific Advanced
Accelerators 2D/2.5D
/2 5D/3D BF 8 2 5.0x
Packaging
FP8 3 0.0x
FP64 FP32 BF16 FP8

Figure 1.1.13: Highly efficient, tightly coupled system-in-package architecture concept built Figure 1.1.14: Bits allocated to exponent and mantissa for various floating point formats and
around UCIe, domain-specific accelerators and memory integration with optical IO. the associated energy efficiency of computing a result.

AI Surrogate Physics Model Analogy AI vs. General Purpose Compute Gains





 


San Francisco 

3.5 hours


26 hours

Austin 
Airport

AMD Office


               
 
 

Figure 1.1.15: Similar to driving (legacy physics calculations) vs. flying (AI accelerated
physics) to the same destination, AI surrogate models leverage physics-trained models for Figure 1.1.16: Gains in lower precision AI-specific floating point operations vs. gains in
fast approximation. traditional, general purpose computation over time [2][3][4][5].

Potential Performance Gains from AI Accelerated HPC The Pathway to Zettascale Efficiency

Wall Time

Baseline Workflow


Time Gain
Hybrid

Workflow  "
  



Physics-based simulation 
!
AI-based surrogate training
AI-based surrogate inference

                     !

                    
   

Figure 1.1.17: Potential improvements in run time for physics calculations by leveraging AI Figure 1.1.18: Efficiency gains must outstrip those of the last decade in order for a zettascale-
surrogate approaches. capable system to fit within a reasonable power level.

12 • 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

ISSCC 2023 / SESSION 1 / PLENARY / 1.2
1.2 Shape the World with Mixed-Signal Integrated
Circuits - Past, Present, and Future
Akira Matsuzawa
Professor Emeritus of Tokyo Institute of Technology and CEO of Tech Idea
Kawasaki, Japan
1. Introduction
The last 50 years has been an era where analog equipment has been replaced by digital
devices. LP records have been replaced by Compact Discs, NTSC and PAL TV systems
have been replaced by digital TVs, VHS video recorders have been replaced by DVD
recorders, film cameras have been replaced by digital cameras, and analog wireless
communications have been replaced by digital wireless communications. Magnetic
recording, optical recording, and signal processing circuitry for wired and wireless
networks were replaced from analog to digital. The digitization of these devices and
systems was due to the technological shift from bipolar to CMOS and the development
of logic and memory circuits supported by scaling laws, but analog-digital mixed
integrated circuit technology such as ADCs and DACs was indispensable. Therefore,
this talk looks back on the digitization of equipment and the mixed signal integrated
circuit technology that contributed to it and discuss future developments.
2. Digital Audio
The first consumer digital electronic device was the Compact Disc (CD). CD which
reproduces music by reading digital data using a semiconductor laser, became very
popular after its release in 1983. In 1987, it surpassed the share of LP records, and LP
records quickly became obsolete. The CD uses a simple signal processing using the
Cross-Interleave Reed-Solomon Error-Correction Code (CIRC) to prevent burst errors
caused by fingerprints. Music playback requires a DAC with 16-bit resolution and 20kHz
bandwidth. Figure 1.2.1 shows the circuit and chip photo of the early popular audio
DAC [1]. 20V Bipolar technology was used and the nichrome thin film resistance was
trimmed by laser to ensure 16-bit accuracy. High-speed and highly accurate laser
trimming was realized by combining coarse trimming that cuts the film at perpendicular
angles, and fine trimming that cuts in parallel to the current flowing through the resistor.
Since then, hybrid ICs using module technology have been replaced by the monolithic
integrated circuit. The chip has been recognized as the world’s first 16-bit monolithic
IC for digital audio and is recognized by the IEEE as one of its milestones.
Currently, audio DACs mostly use the ΔΣ architecture. The ΔΣ modulation technology
[2] was invented during the research on PCM communication. ΔΣ modulator places
integrators in front of the quantizer and applies negative feedback to the input signal,
as shown in Figure 1.2.2. This gives the output Y as shown in equation (1) for input X
and quantization voltage Vq, where L is the order of the integrators.
(1)
Therefore, the noise power Pn is given in
(2)
where OSR is the oversampling ratio. Figure 1.2.2 shows the frequency spectrum of
the quantization noise in the first- and second-order integrators. The quantization noise
is suppressed in the lower frequency range. Therefore, if the order of the integrators is
increased, the noise can be effectively suppressed. However, there is a problem related
to instability such as oscillation due to the increased order of the integrators.
The architecture proposed as a solution to this problem is shown in Figure 1.2.2. In
the ΔΣ modulation method named MASH [3], the first order ΔΣ modulator is connected
in cascade, and added value via the digital differentiator is the output. As a result, it
becomes the same transfer function shown in equation (1), but absolute stability is
guaranteed because there is only a first-order integrator in the negative feedback loop.
This method was first announced as an analog-to-digital converter in 1987 [3] and then
as a digital-to-analog converter in 1989 [4]. However, the ΔΣ modulator of this
architecture has a limited SNR because if there is a mismatch in the transfer function
of each cascaded first order ΔΣ modulator, the quantization noise is not completely
canceled. Therefore, it is difficult to say that this approach is suitable for an ADC, but
in the case of a DAC, mismatches do not occur, so this approach was used as a DAC
for digital audio [5].
Initially, as shown in Figure 1.2.3 (a), a binary output using pulse-width modulation
was used in the same way as in a logic circuit. Therefore, it is easy to integrate in CMOS
and as such the semiconductor technology for DACs for audio has moved to CMOS,
making it possible to reduce costs. The second half of the eighties was also a tailwind
by the progress of CMOS IC technology. However, in the case of binary values,
ISSCC 2023 / February 20, 2023 / 9:20 AM
sensitivity to timing jitter and modulation of the time axis is high, and an expensive
low-jitter oscillator is required. For this purpose, one could use multiple voltage values, 1
but in that case, an extremely small mismatch between elements is necessary. For this
purpose, it is necessary to make the voltage-step multivalued, but in that case, an
extremely small mismatch of the element is necessary. Therefore, as shown in Figure
1.2.4, the Data Weighted Averaging (DWA) method was proposed, which was based
on uniformly selecting the constituent elements to be rotated [6]. The audio DAC of [7]
based on this method, using 5 values, has a dynamic range of 100 dB, which is about
12dB higher than that of the 1-bit DAC at the same clock jitter. In the design of [8]
shown in Figure 1.2.4, in addition to the 5-bit switched-capacitor (SC) DAC, an SC filter
is provided to attenuate unnecessary out-of-band high-frequency components, which
also improves immunity to clock jitter. This design has an extremely high dynamic
range of 120dB and this kind of audio DAC still supports today’s network audio.
3. Digital TV
The main purpose of TV digitization is to improve resolution. It is necessary to transmit
images with about twice the number of scanning lines and about four times the number
of pixels. However, since the signal band is almost equal to the one used for analog TV
broadcasting, image compression technology is required. Developments started already
in the second half of the seventies, but the digital TV broadcasting started in the 2000s,
more than 20 years later. The technology was changed from the MUSE method [9],
based on signal band compression using the subsampling technique shown in Figure
1.2.5, to the current approach based on MPEG image compression.
In the second half of the seventies, ADC integration was not yet advanced. Only an 8-
bit ADC for video was developed by TRW using bipolar technology, but 10-bit ADC
boards using hybrid ICs were still used by ADI as shown in Figure 1.2.6. There was not
yet a monolithic video-rate 10-bit ADC. In addition, the price was 3,500 dollars and the
power consumption was 20 W, so these boards were not suitable for commercial use.
We started developing video-rate ADCs at Panasonic: in 1981 we developed an 8-bit
video-rate ADC [10] and in 1982 a 10-bit ADC, see Figure 1.2.6 [11]. At that time, CMOS
IC technology required for S/H circuits was not yet available, so a flash ADC was used,
requiring many comparators. The mismatch voltage of the transistors constituting a
10-bit flash ADC comparator is required to be about 0.1mV sigma. This accuracy could
be achieved by using a high-precision bipolar transistor developed for VHS video
recorders. This 10-bit ADC was used for digital video switchers and HDTV broadcasting
equipment at the 1988 Seoul Olympic Games. In addition, HDTV requires A/D
conversion of a wideband video signal of about 25MHz from the camera, which requires
a conversion rate of 75MS/s or more, but at that time such a high-speed ADC did not
exist. In 1984, we developed an 8-bit 120MS/s Flash ADC using bipolar transistors [12].
For higher speeds and lower power consumption, trench-isolation bipolar technology
was used. In line with the high-definition test broadcast in 1989, a home HDTV receiver
was developed by Japanese companies that shared the necessary integrated circuits,
as shown in Figure 1.2.5. We were in charge of developing an ADC using BiCMOS
technology [13]. BiCMOS technology made it possible to use S/H circuits, and a two-
step parallel type was used in which the number of elements could be significantly
reduced. In principle, with a resolution of 10-bits, it is possible to reduce the number
of comparators from 1024 to 64. A major problem is that a large conversion error
occurs when the conversion range between the upper conversion and the lower
conversion does not match. Therefore, we developed an interpolation method as shown
in Figure 1.2.7. The differential outputs of the two differential amplifiers selected for
the upper conversion are connected by a series of resistors and the voltages between
taps are compared for the lower conversion. A smooth A/D conversion that flexibly
deals with voltage mismatches was realized. In 1994, we developed a 10-bit 300MS/s
ADC [14] realized by introducing the interpolation technology to flash ADCs. It was
used for optical fiber transmission of HDTV signals.
Later, digital TV made a transition to image compression technology based on MPEG
using computer vision and it has been used to the present day. Although the ADC for
video systems using bipolar and BiCMOS technology developed in the eighties is not
used anymore in today’s digital TV, it supported the early development stage of digital
TV systems.
4. Handy Camera Recorders
Handheld camcorders, which record and playback video images on a magnetic tape,
became popular before digital cameras. There was a certain demand in Japan for child
births, graduation ceremonies, sports days, family trips, and so on.
The first hit was the TR55, released by SONY in 1989. It used 8 mm size cassette
videotapes. In response to this, in 1990, Panasonic released the NV-S1 handheld
camcorder using digital signal processing. The successor model and signal processing
block diagram are shown in Figure 1.2.8. Although it is easier to realize automatic white
balance and automatic focus functions by using digital signal processing, the biggest
motivation for using digital signal processing was image stabilization.
DIGEST OF TECHNICAL PAPERS • 13
ISSCC 2023 / SESSION 1 / PLENARY / 1.2
Handheld camcorders are required to be small and lightweight, which means that they
are prone to camera shakes having a strong impact on image quality. Therefore, as shown
in Figure 1.2.8, the image is stored once in the frame memory and motion vectors are
detected [15]. At this time, it is necessary to judge whether there is a movement by the
subject or a hand. Therefore, several observation regions are used. If the correlation of
movement in each observation region is small, it is judged to be a movement produced
by the subject. On the other hand, when the correlation is high, it is judged to be a
movement by a hand. It also determines whether it is due to a hand or not by the period
of the motion vector. Image compensation to the camera shake is made by controlling
the read address of the memory for images using the motion vector.
Also, low power consumption is extremely important for portable devices, and it is
necessary to extend battery life and reduce temperature rise when downsizing. A 10-bit
video-rate ADC was required for the imaging signal, but at that time the power
consumption was larger than 200mW. In addition, CMOS is necessary for cost reduction
and downsizing, but CMOS ADCs were not necessarily low-power at that time. In 1993,
we developed a 10-bit 20MS/s 30mW CMOS ADC with a power dissipation that was 8
times smaller compared to the state of the art of that moment [16].
The comparator used in this design is the chopper-inverter proposed by Dingwall [17]
shown in Figure 1.2.9, composed of CMOS-friendly elements and circuits such as an
inverter, a switch, and a capacitance. The capacitors absorb and cancel the device
mismatches, and also realize a S/H function. With these elements a two-step parallel
type ADC can be configured. In addition to suppressing the deterioration of accuracy
due to the miniaturization of the elements, the area of the circuit itself can be reduced
because the circuit is simple. As a result, the parasitic capacitance and power
consumption can be reduced. However, the accuracy was about 8 bit and further
ingenuity was required. Figure 1.2.9 shows the upper and lower comparator circuits. In
the lower comparator, the output of the first stage inverter was first combined in 4 units
by capacitances, and the output of the inverter of the next stage was combined by
capacitances in 2 units. By performing interpolation using capacitances in this way, the
mismatch can be effectively suppressed to 1/4, so that 10-bit resolution can be achieved.
Furthermore, since the gray inverter can be removed, it was possible to further reduce
the power consumption. Figure 1.2.9 shows the state of the art in energy consumption
of 10-bit video-rate ADCs around the nineties. Although at that time a CMOS ADC was
not necessarily lower power compared to a bipolar ADC, the energy consumption of this
CMOS ADC is 1/8 compared to the other ADCs. A distinguished low energy consumption
has been attained.
Later, almost all ADCs used CMOS technology, which benefited from technology scaling,
high integration, high speed, and low power.
Low-power technologies for integrated circuits required for portable devices have
attracted attention [15] and low-power technologies have become a major technological
stream that has led to the realization of smartphones.
5. Imaging
In the development of solid-state image sensors, various technologies have been
developed and image quality has been improved so much, but it seems that the stage of
practical use was reached after the development of image sensors that transfer the
accumulated charges generated in a photodiode by a CCD (Charge-Coupled Device).
CCD is an amazing technology [18] that enables noiseless charge transfer by controlling
the potential in the bulk, as shown in Figure 1.2.10. The voltage at the gate on the surface
of the semiconductor is controlled and the charge is transferred along the potential by
sequentially changing the potential in the bulk. Figure 1.2.10 shows the basic
configuration of an image sensor using a CCD [19]. The accumulated charge in the
photodiode that is optically excited, is transferred by the vertical transfer CCD, then
transferred to the horizontal transfer CCD, converted from charge to voltage by an
amplifier, and then converted to a digital value by an ADC outside the image sensor. The
correlated noise is suppressed by using CDS (Correlated Double Sampling) technology
[20] that sequentially transfers the reference signal and the pixel signal and takes the
difference. The signal from the CCD image sensor is an analog serial signal, and a high-
speed ADC with a resolution of about 12 to 14 bits is required to cope with the high
dynamic range of the image signal. CCD image sensors mainly used pipelined ADCs.
Pipelined ADCs are used for wireless communications, especially base stations, but the
first mass-produced application was for CCD image sensors.
In a pipelined ADC, whose principle is shown in Figure 1.2.11, the input comparator
controls a DAC according to the level of the input signal, the CMOS operational amplifier
(“OP” in Figure 1.2.11) amplifies the subtracted signal. The next stage samples the output
signal of the previous amplifier and on the resulting signal it performs the same operation
as the first stage, in a pipelined manner. In this process, the input / output characteristics
become folding characteristics of the output of each conversion stage, and as the
14 • 2023 IEEE International Solid-State Circuits Conference
conversion stage progresses, finer folding characteristics are obtained. For this reason,
to increase the resolution by one bit, it is basically necessary to add a conversion stage,
so there is a good scalability of resolution compared to the two-step parallel ADC, and it
is not so difficult to develop a high-resolution ADC. However, the biggest problem is that
the linearity deteriorates because the signal voltage jumps out of the conversion range
caused by the offset voltage of the comparator as shown in Figure 1.2.12. The
fundamental solution to this problem is a redundant conversion architecture [21] shown
in Figure 1.2.12. By placing the fold return point sufficiently inside the conversion range,
linearity is not affected by the offset voltage of the comparator. Hence, a high accuracy
is possible, and as a result, the use of pipelined ADCs has spread rapidly.
An important technique in this aspect is the development of gain boosting, see Figure
1.2.13, to realize high op amp gains. The required gain G of the OP amplifier is related
to the resolution N as
G (dB ) > 6N +10 (3)
Assuming a resolution of 14 bits, a gain of 94 dB or more is required. A high-speed
single-stage configuration is desirable, but its gain is about 50 dB and does not reach
the target. A gain of 100 dB or more can be achieved in a single stage by boosting the
gain with an amplifier in the cascode circuit [22]. This technique has improved the
performance of pipelined ADCs and became widely used at conversion frequencies of
several hundred MHz with a resolution of about 12 to 16 bits. Development was also
boosted by CMOS scaling during the period of widespread use, by the speed
improvement of op amps, and by the availability of high-precision MIM capacitors.
It is first important to note that a CMOS image sensor does not perform a direct reading
of the photocurrent of the photodiode, but it reads a voltage at the output of source
follower [23]. Indeed, the charge generated by the photodiode is accumulated in the
depletion layer and transferred to the floating capacitance by the “charge transfer gate”
TX, as shown in Figure 1.2.14 [24]. The charge is converted to a voltage and read out as
a voltage via the source follower SF. At this time, the reset level is read first, the signal
level is read next, and the CDS operation is performed so that kT/C noise can be canceled.
Therefore, a small capacitance can be used for high sensitivity. Initially, the pixel signal
was read out in the analog domain, but as with the CCD, high-speed reading was required
as the number of pixels increased. This problem was solved by incorporating a parallel
read ADC in each column of the pixel matrix as shown in Figure 1.2.14. The initial
proposal used a SAR ADC [25], but nowadays integral ADCs using a TDC (Time to Digital
Converter) and counters as shown in Figure 1.2.15 [26] are widely used. An analog-
based CDS is applied using a comparator, and then a digital-based CDS is applied to
perform the signal conversion using a ramp wave. The main reasons for its widespread
use are that the small size of the ADC requires a simple configuration according to the
reducing pixel pitch and monotonicity is guaranteed. Also, a resolution up to about 12
bits is possible, together with a low power consumption and conversion speed according
to the specifications of the image sensor. Since column ADCs operate in parallel, they
do not require high-speed operation like the ADC used in conventional CCD image
sensors, and they have become rapidly popular thanks to their low area, low power and
high speed capabilities.
Additionally, recent image sensors have progressed to three-dimensional sensors by
measuring not only two-dimensional images but also distances. As shown in Figure
1.2.16, the measurement accuracy can be further improved by irradiating infrared light
and counting the number of clocks by a TDC and using voltage information by ADC.
Figure 1.2.16 shows an ADC and TDC circuit [27] that can measure voltage information
and time information simultaneously using a VCO.
With the spread of smartphones and image sensors, it has become possible for
individuals to communicate on a global level using both still and moving images on social
networks. By photographing 2D barcodes, it has become possible to authenticate various
things and easily access the Internet.
6. Recording
ADCs have also been used in HDDs, DVDs, and other recording devices and digital
transmissions. These signals are not natural signals introduced so far, but “1”, “0” digital
signals, and can usually be reproduced by threshold processing. However, due to the
high density of the recording device and the high speed of the transmission device, it is
no longer possible to expect an improvement in the recording density and transmission
speed by threshold processing.
Figure 1.2.17 shows the so-called plus signal, the succeeding minus signal, and the
synthesized signal that is to be detected by the magnetic head. With increasing recording
density it is subject to ISI (Inter Symbol Interference) which attenuates the signal strength
and shifts the timing of the peak. To deal with this challenge, the PRML (Partial-Response
978-1-6654-9016-0/23/$31.00 ©2023 IEEE

Maximum-Likelihood) method is used [28]. PR is a waveform that is distorted by ISI
with the transfer function of H(z-1) and the original waveform can be reproduced or
recorded by applying the inverse function 1/H(z-1) of the transmission line to the
waveform. There are several transmission models, such as PR4, EPR4, and E2PR4.
ML is a method of finding the most reliable data column based on past data sequences.
A Viterbi decoder is used for this. Figure 1.2.17 shows the state of Viterbi
decomposition.
By taking the squared average error of the judgment value D and the signal level S, we
can select the data column with the least error. In Figure 1.2.17, it is “011”. To determine
the data column in this way, an ADC is required to detect the signal level with higher
accuracy, rather than finding “0” or “1” by threshold processing. An integrated circuit
for HDD using this idea was developed in the late nineties [29] [30]. A resolution of 6
bits and a sample rate of several hundred MS/s ADC is often used.
A similar technique was required for DVD. Figure 1.2.18 shows the digital lead channel,
the pickup signal for the DVD recorder, and the reconstructed signal after digital signal
processing. Since a DVD recorder uses multi-value recording by a semiconductor laser,
the SNR is poor and there are many errors. Therefore, the signal is converted to a digital
value by the ADC, and digital signal processing using digital filtering and PRML error
correction reconstructs the error-free signals. Figure 1.2.19 shows the mixed-signal
SoC [31] in which the DVD system is fully integrated on a single chip. It not only
integrates analog circuitry and the PRML digital signal processing circuits, but also
image processors. Figure 1.2.19 shows the inside of the DVD recorder using the SoC
and the DVD recorder before it. Since the SoC integrated the functions of most of the
chips up to that point, a cost reduction has been achieved, together with a reliability
improvement, a low power consumption, and a high degree of miniaturization. Figure
1.2.20 shows the block diagram of the CMOS 7b 400MS/s Flash ADC that has been
developed for use in a SoC [32]. MOS transistors operating in the linear region are
provided at the source side of the differential flip-flop, and 3-bit interpolation (simplified
in the figure to a 2-bit case) was achieved by weighting the gate width. Unlike
interpolation with resistors, no steady-state current is flowing. As a result, a low power
consumption of 50mW has been obtained, which is about 1/10 of the power
consumption of ADCs with similar performance at that time.
PRML technology using ADCs has contributed to the increase of capacity and speed of
HDD and DVD. In general, mixed-signal SoCs, integrating not only digital circuits but
also analog circuits, ADCs and DACs, made it possible to realize an entire complex
system into a single chip, and this became a major trend in IC technology. This has led
to a miniaturization of large-scale systems, which has enabled the success of
smartphones, also thanks to the low power consumption and low cost.
7. Wireline Connections
For wired connections between devices, increasing the data rate is a constant challenge.
In the case of transmission electrical signals over wires or cables, high-frequency signal
attenuation is unavoidable. Therefore, the eye does not open as the transmission rate
increases. Recently, digital technology has been used as a solution [33] [34], as shown
in Figure 1.2.21. In [33] a received signal is converted by an ultra-high-speed ADC to
the digital domain where the frequency characteristics are compensated by a Decision
Feedback Equalizer (DFE) [33]. In [34] the most reliable data series is found in the digital
domain from the obtained waveforms [34] [35].
In long-distance optical transmission, the eye can be closed due to wavelength or
chromatic dispersion (CD) and polarization mode dispersion (PMD). The bottom part
of Figure 1.2.21 shows the impact of PMD and CD on a signal that is modulated with
polarization division multiplexing (PDM) and quadrature phase-shift keying (QPSK).
Since the dispersion shifts the phase of the signals on the X and Y polarizations over
time, the different constellation points. In the ultra-high speed DSP ASIC of [36] for
coherent detection of PDM-QPSK at 100Gbit/s the phase and frequency characteristics
are digitally compensated to reconstruct the normal signaling [36]. This requires an
ultra-fast ADC of about 100GS/s with 6 to 8 bits, for which an interleaved SAR
architecture is used.
The SAR ADC has a simple configuration consisting of a capacitive DAC (CDAC), a
comparator, and SAR logic, as shown in Figure 1.2.22. Since the comparator has a
circuit topology similar to a differential flipflop, no static current is flowing and it is
scaling friendly: both speed and energy consumption can be improved and the occupied
area can be reduced with technology scaling. The capacitance value cannot be scaled
because it is determined by kT/C noise, but the area can be scaled using inter-wiring
capacitance. In addition, a SAR ADC requires a very small capacitance and that can be
easily realized using inter-wiring capacitance. For high-resolution SAR ADCs, a low-
noise comparator with offset adjustment has been developed in [37] (see Figure 1.2.22).
Self-clocking circuits were also developed for high-speed operation.
ISSCC 2023 / February 20, 2023 / 9:20 AM
As shown in Figure 1.2.22, the ADC for wireline takes advantage of the small area and
low energy consumption of a SAR architecture, and by arranging many ADCs with 1
interleaving operation, an ultra-fast conversion of 96GS/s is achieved [38]. Since many
ADCs are used, it is necessary to adjust the offset voltage, conversion gain, and
sampling timing of each ADC. This has necessitated the development of both a
foreground calibration technology that performs these calibrations when the ADC and
DAC are not in operation, and a background calibration technology that acts while the
ADC and DAC are in operation, using the statistical properties of the converted values.
In addition, a low-jitter clock of 100fs or less is required for the conversion of ultra-
wideband signals. To realize high-precision A/D conversion of ultra-wideband signals,
not only ultra-high-speed ADC but also a low-jitter PLL is required. In the domain of
wireline communication, continuous progress in the conversion speed of ADC is
expected. So far, by responding to the quest for ever higher speeds, we have been able
to realize long-distance connections and large-capacity optical fiber networks across
continents. Internet on a global scale contributes to the realization of a society where
people around the world are instantly connected.
8. Wireless Communication
In wireless communication systems, analog communication has also evolved into digital
communication. The benefits of digitization, such as OFDM, sharp digital filters, channel
equalizers, error correction, encryption, and various controls are immeasurable. As a
result, mixed-signal circuits such as ADCs and DACs are also used. Just as with wireline
communication, there is a continuous demand for ever higher data rates. According to
Shannon’s theorem, this requires a wider bandwidth and a higher SNDR. In addition,
in wireless communication, interference exists, and low nonlinear distortion is required
to suppress intermodulations.
Figure 1.2.23 shows the use of ADCs in different wireless communication receiver
architectures. Conventionally, ADCs take as input an analog baseband signal, as shown
in Figure 1.2.23(a). Here the required performance for the ADC is the most relaxed.
Pipelined and SAR ADC architectures are conventionally used here. Alternatively, a
Continuous-Time (CT) ΔΣ ADC, shown in Figure 1.2.24, using a CT integrator has a
special feature for wireless systems. By making the CT integrator ΔΣ ADC shaped, it is
possible not only to extend the signal bandwidth, but also to reduce the burden on the
anti-alias filter [39]. Recently, as shown in Figure 1.2.24 and the upper half of Figure
1.2.25, the bandwidth that can be covered by CT ΔΣ ADCs has risen to about 465 MHz
with a MASH architecture [40] and 800MHz with a CT pipelined architecture [41] to
support a wide bandwidth which is needed for the latest radio applications.
In base stations ADCs that convert IF signals to baseband using IF sampling (see Figure
1.2.23 (b)) are commonly found. I and Q signals are then reconstructed in the digital
domain. This was often done using pipelined ADCs of about 1GS/s with a resolution
ranging from 12 to 16 bits [42] [43]. The newest technique is RF sampling with an ADC
as shown in Figure 1.2.23 (c). The mixer required for wireless systems has been omitted
and the sampling function of the ADC is used to convert the RF signal to a baseband
signal directly. High-speed and wideband ADCs are required, and the interleaved
pipelined ADC shown in Figure 1.2.25 [44] has been developed for this purpose.
Another application of mixed-signal technology in wireless communication, is in
beamforming. This is applied in mm-wave transceivers to boost the link budget by
concentrating the beam in a specific direction, Since at mm-wave frequencies the
wavelength is short and the antenna is small, an antenna array can be configured as
shown in Figure 1.2.26 [45]. By shifting the phase of the signal powering these many
antennas, the beam can be focused in any direction. For this phase control, a quadrature
modulator and a DAC are used. In this way, mixed-signal technology enables not only
high-frequency circuits but also beam control and this has become an indispensable
technology for highly directional mm-wave communication. With the development of
digital wireless communication technology, the personalization of wireless
communication has progressed regardless of location, and it has become possible to
easily communicate with anyone and anywhere via smartphones and other portable
devices. It also became easy to connect between devices wirelessly using Bluetooth.
Wireless communications are being developed for 6G systems that can communicate
at extremely higher speeds. The higher data rates that 6G will accommodate, will come
with channel bandwidths of several GHz, which, in combination with a high spectral
efficiency, will challenge ADC design to sampling rates well above 10GHz and,
depending on the modulation scheme, an effective resolution up to 9-10 bits in mobile
devices, together with a low power consumption
9. Future Progress
In the technology fields introduced so far, mixed-signal circuits such as ADCs and DACs
will continue to be required according to the application, target performance, and
process technology to be used, and further progress will be made. Future applications
for mixed-signal circuits are AI processors and quantum computers. Conventional
computer technology has achieved many remarkable results and has shaped society
DIGEST OF TECHNICAL PAPERS • 15
ISSCC 2023 / SESSION 1 / PLENARY / 1.2
by using extremely robust digital technology. However, AI processors and quantum
computing a good affinity with analog technology, but on the other hand, digital control
and digital signal processing are heavily required, so mixed-signal technology is vitally
required.
For example, it is said that a resolution of about 8 bits is sufficient for an AI processor.
With this level of accuracy, the calculation efficiency can be increased tens of times
compared to digital by performing operations on a CDAC [46] as shown in Figure 1.2.27.
Still the energy consumption, conversion speed, and silicon area are still not satisfactory,
but these are expected to improve in the future. In addition, as shown in Figure 1.2.27,
Compute-in-Memory (CIM) technology has been developed to provide analog arithmetic
functions in the memory itself [47] [48].
In quantum computers, those that use superconductivity for the qubits, require a signal
generation and detection circuit at microwave frequencies to control the spin. An SoC
operating at a low temperature of about 1°K or 4°K is required (see Figure 1.2.28),
containing readout and control electronics that resemble a transceiver [49]. Here, the
development of comprehensive low-temperature CMOS IC technology is indispensable.
The one using single-electron charge qubits [50] requires potential control as shown in
Figure 1.2.28 and requires lots of DACs and detectors. In the future, it will be necessary
to have many ADCs and DACs on such chips, similar to the column ADCs in image
sensors. Just as described above, there is also a possibility here that mixed-signal
technology in the future will develop into a core technology that controls analog
arithmetic, rather than a peripheral technology of computers and processors as in the
past.
Next, we briefly summarize the future direction of ADC developments (see also Figure
1.2.29). ADCs called SAR-based hybrid ADCs are gaining momentum. These use a
residual voltage after conversion in a SAR ADC as the input signal of another ADC. A
typical hybrid ADC is a noise-shaping SAR ADC that uses the residual voltage as the
input of a ΔΣ ADC to realize a higher-resolution ADC [51]-[53], or a pipelined SAR ADC
that uses the residual voltage to realize a faster conversion in a pipelined manner [54]
[55]. In either case, an amplifier is required, but since the requirement for amplifier
distortion can be alleviated by compressing the signal at an early stage, ring amplifiers
[54] [56] and floating amplifiers [57] with low standby current attracting attention instead
of conventional operational amplifiers with a large DC current and large power
consumption.
Next, the issues caused by the ADC sampling operation cause design difficulties for the
ADC peripherals such as anti-alias filters and input and reference voltage buffers. In this
aspect, a pipelined ADC that does not sample the input signal has attractive features [41]
[58].
Finally, the essential challenge in ADC is to overcome kT/C noise. A high-resolution ADC
needs a large capacitance, which increases the conversion energy and degrades the
conversion speed. For a long time, this has been thought to be unavoidable, but recent
research [59] has begun to overcome this problem. In that work, two capacitors,
switches, and an amplifier have been used to reduce the influence of kT/C noise by
changing the position and timing of signal sampling. As already mentioned above, ADC
developments have a great future potential!
10. Summary
The past 50 years has been an era of digitalization. Advances in memory and digital
integrated circuits have led to the evolution of signal processing with analog circuits to
digital signal processing. Since peripheral and environmental signals are in the analog
domain, mixed-signal ICs such as ADCs and DACs are required to interface with digital
electronics, and specific technologies have progressed in each field. While these circuits
were initially standalone products, the increase of the degree of integration over the years
has made it possible to mix these with digital functionality into a mixed-signal SoC. Along
with the improvement of performance, a strong reduction of power consumption and
cost has been achieved, contributing to the portability and popularization of devices such
as smartphones. In addition, in the field of recording and networking, digital “1” or “0”
were initially recorded and transmitted and read or received by threshold processing,
but as the recording density and transmission speed increased, ADCs that read signals
(which are then further processed in the digital domain) and DACs that write signals
became necessary. Digital signal processing requires equalization, error correction, and
maximum likelihood technology to select the most reliable sequence of data, and today
ADCs with speeds of 100 GS/s are required in various domains. Mixed-signal technology
is solving many digital problems today, but it is also evolving into digitally assisted analog
technology that uses digital technology to address analog issues such as mismatches,
variations, distortions and performance or power optimization.
Although it is difficult to show the progress of ADCs with simple indicators, the
conversion energy as a function of SNDR and the Schreier figure-of-merit FoMS as a
function of the conversion frequency conversion have progressed over the years as
16 • 2023 IEEE International Solid-State Circuits Conference
shown in Figure 1.2.30 [60]. This is the result of the evolution of mixed-signal circuits
that also profit from the scaling of logic device technology, SAR ADCs being a nice
example here. Still, fundamental challenges such as the performance constraint from
kT/C noise in ADCs need to be overcome, as today this is combatted with large
capacitances at the expense of a large conversion energy.
Finally, in the future, it will be important to develop computers such as AI processors
and quantum computers whose operations are essentially analog, so mixed-signal
technology is expected to develop even further.
Acknowledgement:
I would like to express my sincere thanks to Dr. M. A. Abdel, Dr. T. Kuroda, Dr. I.
Takayanagi, Dr. Y. Oike, Dr. K. Nishimura, Dr. I. Fujimori, Dr. T. Hamasaki, Dr. K.
Nakamura, Dr. H. Shibata, Dr. M. Sugawara, Dr. T. Saida, Dr. K. Okada, Dr. R. B.
Staszewski, and Dr. R. Nikandish for providing useful information in each area and for
the useful discussions.
References:
[1] J. R. Naylor, “A 16b Monolithic DAC with Voltage Output,” IEEE International Solid-
State Circuits Conference, Dig. Tech. Papers, pp. 186-187, Feb. 1983.
[2] H. Inose, Y. Yasuda, and J. Murakami, “A Telemetering System by Code Modulation
-Δ-Σ Modulation,” IRE Transactions on Space Electronics and Telemetry (Volume: SET-
8, Issue: 3, September 1962.)
[3] Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T. Yoshitome, “A
16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise
Shaping,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 6, pp. 921-929, Dec. 1987.
[4] Y. Matsuya, K. Uchimura, A. Iwata, and T. Kaneko, “A 17-bit Oversampling D-to-A
Conversion Technology Using Multistage Noise Shaping,” IEEE Journal of Solid-State
Circuits, vol. 24, no. 4, pp. 969-975, Dec. 1989.
[5] Y. Tani, K. Nuriya, N. Seki, and T. Kaneaki, “20-bit A-to-D & D-to-A converting
systems for digital audio,” IEEE Transactions on Consumer Electronics, vol. 35, no. 3,
pp. 528–535, Aug. 1989.
[6] R. T. Baird and T. S Fiez, “Linearity Enhancement of Multibit DS A/D and D/A
Converters Using Data Weight Averaging,” IEEE Tran. on circuits and Systems-II: Analog
and Digital Signal Processing, vol. 42, no. 12, pp. 753-762, Dec. 1995.
[7] T. Hamasaki, Y. Shinohara, H. Terasawa, K. Ochiai, M. Hirooka, and H. Kanayama,
“A 3-V, 22mW Multibit Current-Mode SD DAC with 100 dB Dynamic Range,” IEEE
Journal of Solid-State Circuits, vol. 31, no. 12, pp. 1888-1894, Dec. 1996.
[8] I. Fujimori, A. Nogi, and T. Sugimoto, “A Multibit Delta-Sigma Audio DAC with 120-
dB Dynamic Range,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1066-1073,
Aug. 2000.
[9] Y. Ninomiya, Y. Ohtsuka, Y. Izumi, S. Gohshi, and Y. Iwadate, “An HDTV Broadcasting
System Utilizing a Bandwidth Compression Technique—MUSE,” IEEE Transaction on
Broadcasting, vol. BC-33, no. 4, pp. 130-160, Dec. 1987.
[10] A. Matsuzawa, M. Inoue, H. Sadamatsu, T. Takemoto, and T. Yoneda, “Low-power
Parallel 8-bit A/D Converter with Video Speed,” Proc. IEICE annual meeting.
Semiconductor and material field, p.137, 1981.
[11] T. Takemoto, M. Inoue, H. Sadamatsu, A. Matsuzawa, and K. Tsuji, “A Fully Parallel
10-Bit A/D Converter with Video Speed,” IEEE Journal of Solid-State Circuits, vol. SC-
17, no.6, pp. 1133-1138, 1982.
[12] M. Inoue, H. Sadamatsu, A. Matsuzawa, A. Kanda, and T. Takemoto, “A Monolithic
8-bit A/D Converter with 120MHz Conversion Rate,” IEEE Journal of Solid-State Circuits,
vol.SC-19, no. 6, pp. 837-841, 1984.
[13] A. Matsuzawa, M. Kagawa, M. Kanoh, K. Tatehara, T. Yamaoka, and K. Shimizu, “A
10b 30MHz Two-Step Parallel Bi-CMOS ADC with Internal S/H,” IEEE International Solid-
State Circuits Conference, Dig. Tech. Papers, pp. 162-163, Feb. 1990.
[14] H. Kimura, A. Matsuzawa, T. Nakamura, and S. Sawada, “A 10-b 300-MHz
Interpolated-Parallel A/D Converter,” IEEE Journal of Solid-State Circuits, vol.28, no.4,
pp. 438-446, 1993.
[15] A. Matsuzawa, “Low-Voltage and Low-Power Circuit Design for mixed Analog/Digital
Systems in Portable Equipment,” IEEE Journal of Solid-State Circuits, vol.29, no.4, pp.
470-480, 1993.
[16] K. Kusumoto, A. Matsuzawa, and K. Murata, “A 10-b 20-MHz 30mW Pipelined
Interpolating CMOS ADC,” IEEE Journal of Solid-State Circuits, vol.28, no.12, pp. 1200-
1206, 1993.
[17] A. G. F. Dingwall, “Monolithic Expandable 6 Bit 20MHz CMOS/SOS A/D Converter,”
IEEE Journal of Solid-State Circuits, vol. SC-14, no. 6, pp. 926-932, Dec. 1979.
[18] W. S. Boyle and G.E. Smith, “Charge Coupled Semiconductor Devices,” Bell System
Tech. J., 49, p.587, Apr. 1970.
[19] M. F. Tompsett et al, “Charge-coupled imaging devices: Experimental results,” IEEE
Trans. on Electron Device, vol ED-18, No. 11, pp. 992-996, Nov. 1971.
[20] M. White, D. Lampe, F. Blaha, and I. Mack, “Characterization of Surface Channel
CCD Image Arrays at Low Light Levels,” IEEE Journal of Solid-State Circuits, vol. SC-9,
no. 1, pp. 1-12, Feb. 1974.
978-1-6654-9016-0/23/$31.00 ©2023 IEEE

[21] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr, R. Ramachandran, and T. R.
Viswanathan, “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE Journal of
Solid-State Circuits, vol. 27, no. 3, pp. 351-358, March 1992.
[22] K. Bult and G. J. G. M. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with
90-dB DC Gain,” IEEE Journal of Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384,
Dec. 1990.
[23] F. Andoh, K. Taketoshi, J. Yamazaki, M. Sugawara, Y. Fujita, K. Mitani, Y.
Matsuzawa, K. Miyata, and S. Araki, “A 250000-pixel image sensor with FET
amplification at each pixel for high-speed television cameras,” IEEE International Solid-
State Circuits Conference, Dig. Tech. Papers, pp. 212 -213, Feb. 1990.
[24] K. Yonemoto and H. Sumi, “A CMOS Image Sensor with a Simple Fixed-Pattern-
Noise Reduction Technology and a Hole Accumulation Diode,” IEEE Journal of
Solid-State Circuits, vol. 35, no. 12, pp. 2038-2043, Dec. 2000.
[25] A. Krymski, D. Van Blerkom, A. Anderson, N. Bock, B. Mansoorial, and E. R.
Fossum, “A High Speed, 500 Frames/s, 1024 x 1024 CMOS Active Pixel Sensor,”
Symposium on VLSI Circuits Digest of Technical papers, pp. 137-138, June 1999.
[26] S. Yoshihara, et al., “A 1/1.8-inch 6.4 M Pixel 60 frames/s CMOS Image Sensor
With Seamless Mode Change,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp.
2998-3006, Dec. 2006.
[27] S. Kondo, et al., “An Automotive LiDAR SoC for 240 x 192-Pixel 225-m-Range
Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based
AFE,” IEEE Journal of Solid-State Circuits, vol. 55, no. 11, pp. 2866-2877, Nov. 2020.
[28] T. H. Patel, “A class of partial response systems for increasing storage density in
digital magnetic recording,” IEEE Trans. on Magnetics, vol. 23, no. 5, pp. 3666-3668,
Sept. 1987.
[29] J. G. Chen, et al., “An EPRM Digital Read/Write Channel IC,” IEEE International
Solid-State Circuits Conference, Dig. Tech. Papers, pp. 320-321, Feb. 1997.
[30] T. Pan, et al., “A Trellis-Coded E2PRML Digital Read/Write Channel IC,” IEEE
International Solid-State Circuits Conference, Dig. Tech. Papers, pp. 36-37, Feb. 1999.
[31] K. Okamoto, et al., “A Fully Integrated 0.13-μm CMOS Mixed-Signal SoC for DVD
Player Applications,” IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1981-
1991, Nov. 2003.
[32] K. Sushihara and A. Matsuzawa, “A 7b 450MSPS 50mW CMOS ADC in 0.3mm2,”
IEEE International Solid-State Circuits Conference, Dig. Tech. Papers, pp. 170-171, Feb.
2002.
[33] J. Cao et al., “A 500 mW ADC-based CMOS AFE with digital calibration for 10 Gb/s
serial links over KR-backplane and multimode fiber,” IEEE Journal of Solid-State
Circuits, vol. 45, no. 6, pp. 1172–1185, June 2010.
[34] H-M, Bae, J. B. Ashbrook, J. Park, N. R. Shanbhag, A. C. Singer, and S. Chopra,
“An MLSE Receiver for Electric Dispersion Compensation of OC-192 Fiber Links,” IEEE
Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2541–2554, June 2010.
[35] A. Masuda, S. Yamamoto, H. Taniguchi, M. Nakamura, and Y. Kisaka
“255-Gbps PAM-8 Transmission under 20-GHz Bandwidth Limitation using NL-MLSE
Based on Volterra Filter,” 2019 Optical Fiber Communications Conference and Exhibition
(OFC).
[36] Y. Miyamoto and M. Tomizawa, “High-Capacity Scalable Optical Communication
for Future Optical Transport Network,” IEEE International Solid-State Circuits
Conference, Dig. Tech. Papers, pp.118-119, Feb. 2014.
[37] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A Low-Noise Self-Calibrating
Dynamic Comparator for High-Speed ADCs,” 2008 IEEE Asian Solid-State Circuits
Conference, pp. 269-272, Nov. 2008.
[38] J. Cao, et al., ”A Transmitter and Receiver for 100Gb/s Coherent Networks with
Integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS,” IEEE International Solid-
State Circuits Conference, Dig. Tech. Papers, pp. 484-485, Feb. 2017.
[39] T. Caldwell, D. Alldred, and Z. Li, “A reconfigurable ΔΣ modulator with up to 100
MHz bandwidth using flash reference shuffling,” Proceeding of the IEEE 2013 Custom
Integrated Circuits Conference, pp. 1-4, 2013.
[40] Y. Dong, et al., “A 72dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in
28nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp-2917-1927, Dec.
2016.
[41] H. Shibata, et al., “An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC
with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter, “IEEE International
Solid-State Circuits Conference, Dig. Tech. Papers, pp. 260-261, Feb. 2020.
[42] A. M. A. Ali, et al., “A 16-bit 250-MS/s IF Sampling Pipelined ADC with Background
Calibration,” IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp-2602-2612, Dec.
2010.
[43] A. M. A. Ali, et al., “A 14-bit 1 GS/s RF Sampling Pipelined ADC with Background
Calibration,” IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp-2857-2867, Dec.
2014.
[44] A. M. A. Ali, et al., “A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband
Trac-and-Hold Amplifier and Background Calibration,” IEEE Journal of Solid-State
Circuits, vol. 55, no. 12, pp. 3210-3224, Dec. 2020.
ISSCC 2023 / February 20, 2023 / 9:20 AM
[45] J. Pang, et al., “A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-
Shifting Architecture with Gain Invariant Phase Tuning for 5G New Radio. IEEE Journal 1
of Solid-State Circuits, vol. 54, no. 5, pp. 1228-1242, May. 2020.
[46] D. Bankman, L. Yang, B. Moons, M. Verhelst, and Boris Murmann, “An Always-
On 3.8 μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip
in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 158-172, Jan.
2019.
[47] H. Valavi, P. J. Ramadge, E. Nestler, and. N. Verma, “A 64-Tile 2.4-Mb In-Memory-
Computing CNN Accelerator Employing Charge-Domain Compute,” IEEE Journal of
Solid-State Circuits, vol. 54, no. 6, pp. 1789-1799, June 2019.
[48] Z. Jing, B. Yan, Y. Yang, and R. Huang, “VSDCA: A Voltage Sensing Differential
Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory
Accelerators,” IEEE Trans. on Circuits and Systems-I: Regular papers, pp. 1-14, June
2022.
[49] B. Patra, R. M. Incandela, J. P. G. van Dijk, H. A. R. Homulle, L. Song, M.
Shahmohammadi, R. B. Staszewski, A. Vladimirescu, M. Babaie, F. Sebatiano, and E.
Charbon, “Cryo-CMOS Circuits and Systems for Quantum Computing Applications,
“IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 309-321, Jan. 2019.
[50] R. B. Staszewski, I. Bashir, E. Blokhina, and D. Leipold, “Cryo-CMOS for Quantum
System On-Chip Integration,” IEEE Solid-State Circuits Magazine, pp. 46-53, Spring,
2021.
[51] Y. Chae, K. Souri and K. A. A. Makinwa, “A 6.3 μW 20 bit Incremental Zoom-ADC
with 6 ppm INL and 1 μV Offset,” IEEE Journal of Solid-State Circuits, vol. 48, no. 12,
pp. 3019-3027, Dec. 2013.
[52] K. Obata, K. Matsukawa, T. Miki, Y. Tsukamoto and K. Sushihara, “A 97.99 dB
SNDR, 2 kHz BW, 37.1 μW noise-shaping SAR ADC with dynamic element matching
and modulation dither effect,” 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits),
pp. 1-2, 2016.
[53] Y-S. Shu, L-T. Kuo, and T-Y. LO, “An Oversampling SAR ADC With DAC Mismatch
Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm
CMOS,” IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928-2940, Dec. 2016.
[54] Y. Lim and M. P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential
Ring Amplifier Based SAR-Assisted Pipeline ADC,” IEEE Journal of Solid-State Circuits,
vol. 50, no. 12, pp. 2901-2911, Dec. 2015.
[55] W. Jiang, Y. Zhu, M. Zhang, C. -H. Chan and R. P. Martins, “A Temperature-
Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With
Dynamic Gm-R-Based Amplifier,” IEEE Journal of Solid-State Circuits, vol. 55, no. 2,
pp. 322-332, Feb. 2020.
[56] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita and U. -K. Moon,
“Ring Amplifiers for Switched Capacitor Circuits,” IEEE Journal of Solid-State Circuits,
vol. 47, no. 12, pp. 2928-2942, Dec. 2012.
[57] X. Tang et al., “An Energy-Efficient Comparator with Dynamic Floating Inverter
Amplifier,” IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1011-1022, April
2020.
[58] H. Shibata et al., “A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline
ADC Achieving −164-dBFS/Hz NSD,” IEEE Journal of Solid-State Circuits, vol. 52, no.
12, pp. 3219-3234, Dec. 2017.
[59] J. Liu, X. Tang, W. Zhao, L. Shen and N. Sun, “A 13-bit 0.005-mm2 40-MS/s SAR
ADC With kT/C Noise Cancellation,” IEEE Journal of Solid-State Circuits, vol. 55, no.
12, pp. 3260-3270, Dec. 2020.
[60] Editors: D. C. Daly, L. C. Fujino, and K. C. Smith, Reporter: Un-Ku Moon, “Though
the Looking Glass-The 2018 Edition, Analog Systems: Data Converters” IEEE Solid-
State Circuits Magazine, p. 3, Winter 2018.
DIGEST OF TECHNICAL PAPERS • 17
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20 • 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

 ISSCC 2023 / February 20, 2023 / 9:20 AM
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DIGEST OF TECHNICAL PAPERS • 21

ISSCC 2023 / SESSION 1 / PLENARY / 1.2


   


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22 • 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

ISSCC 2023 / SESSION 1 / PLENARY / AWARDS
ISSCC 2023 AWARDS
2022 Lewis Winner Award for Outstanding Paper
“Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing”
Wilfred Gomes1, Altug Koker2, Pat Stover3, Doug Ingerly1, Scott Siers2,
Srikrishnan Venkataraman4, Chris Pelto1, Tejas Shah5, Amreesh Rao2,
Frank O’Mahony1, Eric Karl1, Lance Cheney2, Iqbal Rajwani2, Hemant Jain4,
Ryan Cortez2, Arun Chandrasekhar4, Basavaraj Kanthi4, Raja Koduri6
1
Intel, Portland, OR, 2Intel, Folsom, CA, 3Intel, Chandler, AZ
4
Intel, Bengaluru, India 5Intel, Austin, TX, 6Intel, Santa Clara, CA
2022 Anantha P. Chandrakasan
Distinguished-Technical-Paper Award  Liuhao Wu1, Jiaqi Guo1, Rucheng Jiang1, Yande Peng2, Han Wu1, Jiamin Li1,
“A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time
Reduction and 0.68ppm/°C Duty-Cycled Machine-Learning-Based RCO
Calibration”
Jaehong Jung, Seunghyun Oh, Joomyoung Kim, Gihyeok Ha, Jinhyeon Lee,
Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seungyong Bae,
Wonkang Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee,
Thomas Byunghak Cho
Samsung Electronics, Hwaseong, Korea
2022 Jan Van Vessem Award for Outstanding European Paper
“A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving
7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range”
Youngwoo Ji1,2, Jiawei Liao1, Sina Arjmandpour1,3, Alessandro Novello1,
Jae-Yoon Sim2, Taekwang Jang1
ETH Zürich, Zürich, Switzerland
1
2
Pohang University of Science and Technology, Pohang, Korea
3
Sharif University of Technology, Tehran, Iran
2022 Takuo Sugano Award for Outstanding Far-East Paper
“Side-Channel Attack Counteraction via Machine Learning-Targeted Power
Compensation for Post-Silicon HW Security Patching”
Qiang Fang , Longyang Lin , Yao Zu Wong , Hui Zhang , Massimo Alioto
1 1,2 1 1
1
National University of Singapore, Singapore, Singapore
2
Southern University of Science and Technology, Shenzhen, China
ISSCC 2022 Jack Kilby Award for Outstanding Student Paper
 “A 10GS/s 8b 25fJ/c-s 2850μm2 Two-Step Time-Domain ADC Using Delay-
Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology”
Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
University of Southern California, Los Angeles, CA
2022 ISSCC Award for Outstanding Forum Presenter
“Sensor Interface, Analog, and Mixed-Signal Circuits for
Miniaturized IoT Devices”
Taekwang Jang
ETH Zurich, Zurich, Switzerland
February 20, 2023 / 9:55 AM
1
2022 ISSCC Award for Outstanding Forum Presenter
“6G Communications: Vision and Challenges”
Gary Xu
Samsung, Plano, TX
2022 Demonstration Session Certificate of Recognition
“BatDrone: A 9.83M-focal-points/s 7.76μs-Latency Ultrasound Imaging System
with On-Chip Per-Voxel RX Beamfocusing for 7m-Range Drone Applications”
Yilong Dong1, Miaolin Zhang1, Zhuoyue Li1, Kian Ann Ng3, Chne-Wuen Tsai1,
Lian Zhang1, Longyang Lin4, Liwei Lin2, Jerald Yoo1,5
1
National University of Singapore, Singapore, Singapore
2
University of California, Berkeley, CA
3
Digipen Institute of Technology, Singapore, Singapore
4
Southern University of Science and Technology, Shenzhen, China
5
The N.1 Institute for Health, Singapore, Singapore
2022 Demonstration Session Certificate of Recognition
“A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation”
Yoav Segal1, Amir Laufer1, Ahmad Khairi1, Yoel Krupnik1, Marco Cusmai1,
Itamar Levin1, Ari Gordon1, Yaniv Sabag1, Vitali Rahinski1, Gadi Ori1, Noam Familia1,
Stas Litski1, Tali Warshavsky1, Udi Virobnik1, Yeshayahu Horwitz1, Ajay Balankutty2,
Shiva Kiran2, Samuel Palermo3, Peng Mike Li4, Ariel Cohen1
1
Intel, Jerusalem, Israel, 2Intel, Hillsboro, OR
3
Texas A&M University, College Station, TX, 4Intel, San Jose, CA
ISSCC 2023 Silkroad Award
“A 16.4kpixel 3.08-to-3.86THz Digital Real-time CMOS Image Sensor with 73dB
Dynamic Range”
Min Liu
Chinese Academy of Sciences, Beijing, China
1
ISSCC 2022 Student-Research Preview (SRP) Poster Award
“Amber: a 441.2 GOPS/W 16nm Coarse Grained Reconfigurable Array-Based
SoC Accelerator for Image Processing and Computer Vision”
Kathleen Feng
Stanford University, Stanford, CA
ISSCC 2022 Student-Research Preview (SRP) Poster Award
“A Ka-Band Dual Circularly Polarized CMOS Phased-Array Transmitter with
Adaptive Scan Impedance Tuner and Circular Polarization Calibration”
Dongwon You
Tokyo Institute of Technology, Tokyo, Japan
DIGEST OF TECHNICAL PAPERS • 23
ISSCC 2023 / SESSION 1 / PLENARY / AWARDS

IEEE SOLID-STATE CIRCUITS SOCIETY AWARDS

2021 Journal of Solid-State Circuits Best Paper Award
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4
Transmitter with Nonlinear Equalization and Thermal Control
Hao Li1, Ganesh Balamurugan1 Taehwan Kim1, Meer N. Sakib2, Ranjeet Kumar2,
Haisheng Rong2, James Jaussi1, Bryan Casper1
1
Intel, Hillsboro, OR, Intel, Santa Clara, CA
2
2023 IEEE Solid-State Circuits Society New Frontier Award
Ruonan Han
Massachusetts Institute of Technology, Cambridge, MA
The IEEE SSCS New Frontier award recognizes and honors SSCS members in their early career
who are exploring innovative and visionary technical work within the field of solid-state circuits.
The award aims to pioneering developments that are at the frontiers of IC design or possess
an imminent potential to expand the field through new categories of circuit technologies,
system design, and/or emerging applications.

2022 IEEE Solid-State Circuits Society Chapter Awards

SSCS Chapter of the Year 2023 IEEE Solid-State Circuits Society Industry Impact Award
IEEE SSCS Switzerland Chapter Samuel Naffziger
Taekwang Jang, Chair
Advanced Micro Devices, Fort Collins, CO
Michel Bron, Vice Chair
Mathieu Coustans, Secretary
Domenico Pepe, Industry Relations Coordinator The IEEE SSCS Industry Impact Award recognizes and honors SSCS members who have had
a seminal impact and made distinctive contributions to the field of solid-state circuits and the
integrated circuits industry. The award recognizes extraordinary accomplishments in
entrepreneurship, leadership and/or technical excellence that led to significant breakthroughs
and paradigm shifts in the IC business, thereby enabling new products and services within the
SSCS Student Branch Chapter of the Year ten year period prior to the application deadline.
IEEE EDS/SSCS University of Niš Student Branch Chapter

Sandra Veljković, Chair

Vojkan Davidović, Treasurer 2023 IEEE Solid-State Circuits Society
Nikola Mitrović, Secretary James D. Meindl Innovators Award
Danijel Danković, Faculty Advisor
Daniel Limbrick

IEEE SSCS University of Science and Technology North Carolina Agricultural and Technical State University, Greensboro, NC
of China Student Branch Chapter
The IEEE SSCS New Frontier award recognizes and honors SSCS members in their early career
Muhammad Hunain Memon, Chair who are exploring innovative and visionary technical work within the field of solid-state circuits.
Fujiang Lin, Faculty Advisor The award aims to pioneering developments that are at the frontiers of IC design or possess
an imminent potential to expand the field through new categories of circuit technologies,
system design, and/or emerging applications.
SSCS Chapter with Best Educational Program Award
IEEE SSCS University of Bordeaux Student Branch Chapter
2023 IEEE Brokaw Award for Circuit Elegance
Maxandre Fellmann, Chair
Yann Deval, Faculty Advisor Benjamin Hershberg

Intel, Hillsboro, OR
IEEE SSCS KU Leuven Student Branch Chapter
This Award was created to enhance appreciation and encourage innovation of simple, smart,
Carl D’heer, Chair and elegant circuit design. The award is presented in recognition of a unique, innovative,
Ariane De Vroede, Vice Chair simple, smart, and elegant circuit design, created during the past decade that has demonstrated
Jonas Pelgrims, Treasurer its viability.
Arnaud Van Mieghem, IEEE SB
Bram Veraverbeke, Media & Public Relations
Senne Gielen, Secretary
Berke Güngör, Member

SSCS Chapter with Best Pre-University Outreach Award

IEEE SSCS Ss. Cyril & Methodius University in Skopje
Student Branch Chapter

Stefan Momyr, Chair

24 • 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

 ISSCC 2023 / February 20, 2023 / 9:55 AM

IEEE Technical Field Awards

1

2023 IEEE Donald O. Pederson Award in Solid-State Circuits

Ingrid Verbauwhede
KU Leuven, Leuven, Belgium
“For pioneering contributions to energy-efficient and high-performance secure integrated circuits and systems.”

The IEEE annually recognizes outstanding contributors worldwide to the art and science of electro- and information technologies
with technical awards in 3 dozen technical specialties. The IEEE Donald O. Pederson Award for Solid-State Circuits for
outstanding contributions in the field of solid-state circuits goes to an individual or team of not more than three. The award
includes a bronze medal, certificate, and cash honorarium which are presented at the ISSCC.

2023 IEEE Fellows

Walid Y Ali-Ahmad Kenichi Okada

Apple, San Carlos, CA Tokyo Institute of Technology, Tokyo, Japan
“For leadership in development of low-cost direct-conversion “For contributions to millimeter-wave communication circuits design”
cellular RF systems”

Omer Oralkan
Jason H. Anderson North Carolina State University, Raleigh, NC
University of Toronto
“For contributions to micromachined ultrasonic transducers
“For contributions to high-level synthesis and low-power FPGAs” and integrated microsystems development,
for imaging, therapy, and sensing”

Keith Bowman
Qualcomm, Raleigh, NC Woogeun Rhee
Tsinghua University, Beijing, China
“For contributions to variation-tolerant adaptive processor designs”
“For contributions to phase-locked circuits and systems”

Tetsuo Endoh
Sriram Vangal
Tohoku University, Sendai, Japan
Intel, Portland, OR
“For contributions to nonvolatile memory and spintronic logi”
“For contributions to network-on-chip architectures”

Roberto Gomez-Garcia
Marian Verhelst
University of Alcala Getafe, Madrid Spain
K.U. Leuven, Heverlee, Belgium
“For contributions to planar multi-function microwave filters”
“For contributions to energy-efficient near-sensor processing
and embedded Machine Learning Processors”
Donhee Ham
Harvard University, Cambridge, MA
Hua Wang
“For contributions to semiconductor electronic interfaces Georgia Institute of Technology, Atlanta, GA
with biological systems”
“For contributions to high-efficiency microwave
and millimeter-wave power amplifiers”
Muhammad M. Khellah
Intel, Tigard, OR
Qiangfei Xia
“For contributions to co-optimization of on-die dense memory University of Massachusetts Amherst, Winchester, MA
and fine-grain power-management circuits”
“For contributions to resistive memory arrays
and devices for in-memory computing”
Thomas Mikolajick
NaMLab, Dresden, Germany
“For contributions to nonvolatile memory”

DIGEST OF TECHNICAL PAPERS • 25

ISSCC 2023 / SESSION 1 / PLENARY / 1.3
1.3 EU Chips Act Drives Pan-European Full-Stack Innovation
Partnerships
Jo De Boeck
imec and KU Leuven, Leuven, Belgium
Jean-René Lèquepeys
CEA-Leti and Université Grenoble Alpes, Grenoble, France
Christoph Kutter
Fraunhofer EMFT and Universität der Bundeswehr, Munich, Germany
1. The Impact of Semiconductors and the European Chips Act
In every aspect of our life and society, semiconductors play a major role and that impact
is set to increase even further. The pandemic in conjunction with supply chain hiccups
and geopolitical tensions made all regions realize that they need to revisit their position
and potential in the semiconductor value chain. The European Commission expressed
[1] the ambition of achieving a 20% share of global semiconductor production by 2030.
This is roughly a ‘times four’ increase with respect to the situation today. To achieve
that, a plan is proposed that invests in research and development, promotes larger
incentives for manufacturing, and indicates measures for a more stable supply chain.
Worldwide ambitious investments are planned for semiconductor R&D and
manufacturing. Europe should leverage its existing strengths (see Figure 1.3.1) such
as its unique position of certain materials and equipment companies ( ASML, SOITEC,
ASM-I, and so on), leadership positions in R&D on the industrial 300mm wafer standard
(imec, CEA/Leti, Fraunhofer), and existing ecosystems for chip manufacturing embracing
mature nodes and specialties, as well as partnerships for advanced semiconductor
fabrication. The high-quality educational system and the presence of strong OEMs, such
as automotive companies, are key assets to drive the demand. The openness to
partnerships in all layers of the value chain and at all levels of technology maturity will
be essential for success, given the very strong position of other regions in certain
domains (EDA, leading-edge node chip manufacturing, packaging, memory).
The first pillar of the European Chips Act centers around two intertwined concepts (see
Figure 1.3.2): (1) the establishment of pilot line facilities to enable the Lab-to-Fab
transition of breakthrough semiconductor technology ideas; and (2) the build-up of large-
scale design capacities for integrated semiconductor technologies. This combination will
allow advanced demonstration and validation of circuit and system innovation. Programs
for talent development and venture capital for start-ups and scale-ups are explicitly
present in the plans, as key factors for success. Under ‘pillar one’ the EU semiconductor
ecosystem will benefit through access to the Chips for Europe pilot line facilities and
design capabilities. One-stop-shop interfaces will be established to perform specific
activities such as: (i) the ‘injection’ of the most advanced technology in an innovation
project; (ii) the engineering of a demonstrator at higher TRL; or (iii) the preparation of
the production capacity ecosystem for swift market uptake and growth. Such activities
will be of high value to the full value chain, from materials and tool providers over IDM
and foundries to the fabless and design companies. Programs for start-up and scale-
ups access will be rolled out.
The second pillar of the EU Chips Act focuses on increasing the capacity of manufacturing
and counts on financial contribution from EU member states and industry. The third
pillar is concentrating on the supply chain monitoring and potential interventions in crisis
situations.
The focus of this paper is on pillar one, the pilot line facilities and the associated design
platform. Some pilot-line technologies have been earmarked in the plans, such as Fully-
Depleted SOI (FDSOI) 10nm, leading-edge sub-2nm technology, heterogeneous
integration, and chiplet technology, as well as quantum computing chips. A pilot line at
the Research and Technology Organizations (RTOs) allows for exploration of new device
and circuit integration technology and early integration experiments to demonstrate basic
architectures at an early stage as proof-of-concept on industry-grade equipment and
within industry-relevant boundary conditions (see Figure 1.3.3). Though maturity is very
low still, the initial models are in place to draft a research process design kit (PDK) that
allows to interface with the designers for first circuit-level impact experiments. In close
collaboration with the industry, and for not overly complex technologies, the pilot lines
can mature the technology to the stage of low volume manufacturing or technology
module integration on foundry wafers (embedded memories, 3D stacking, photonics
functionality integration and so on) that allows to explore application specific functionality
improvements. Such demonstrations will build the economical case for transfer to
industry pilot production or prequalification, where further engineering will take place
for up-scaling, yield improvement, and risk production for the early adopters.
The pilot-line technologies will indeed have to invest in design enablement to allow early
exploration of the potential impact of new features in advanced chip and system
architectures (see Figure 1.3.4). Virtual prototyping will exploit experimental PDKs for
logic, memory, and other features. Feedback from these explorations will instigate
26 • 2023 IEEE International Solid-State Circuits Conference
changes to be made in integration technology, leading to a more mature process in line
with future application needs that will allow building early demonstrators and help reduce
the time for introducing new products by paralleling several activities such as new
process technology, design enablement, and IC chips development. As a result, the
industrial uptake of the technologies will be triggered, supported by an increased
demand. This type of innovation loop is also essential for deep-tech start-ups that want
to convince their investors of their unique value proposition and get first customers to
adopt it.
The concept of building up large-scale design capacities through a network of
Competence Centers for integrated semiconductor technologies is a key ingredient to
boost Europe’s competitiveness for semiconductor design innovations. The goal is to
lower the cost and the access barriers to advanced and leading-edge technologies and
to enable and stimulate the exchange of design IP between academia and industry. The
latter can be achieved by creating such a ‘virtual’ design environment, which should
contain design tools, PDKs, and design IP repositories. The most likely vehicle to
integrate all those elements is the cloud. Already now, one can observe a shift of design
activities into the cloud [2]. The main drivers for moving IC design to the cloud are
amongst others enhanced security (including IP protection for the advanced technology
nodes), more flexibility and scalability (such as pay-per-use for EDA tools) and more
collaboration between designers. In the end, these developments will lead to more
innovations and a vibrant design ecosystem in Europe.
The innovation engine described above will drive a multitude of future applications and
services in fields like high-performance computing (HPC), distributed computing and
IoT, telecommunications, automotive and robotics, augmented and virtual reality
(AR/VR), smart sensors, healthcare and wearables, to name a few important ones. In
all these applications, the most-advanced semiconductor technologies will be combined
with more mature nodes or derivatives for sensors, imagers, power, RF, and so on. This
smart mix of semiconductor technologies adapted to specific electronic functions will
be integrated altogether thanks to advanced packaging and a 3D heterogeneous
integration toolbox.
2. The Need for ‘Full-Stack’ and Sustainable Innovation
The innovation in semiconductor technologies and design must comply with
specifications and requirements from applications (see Figure 1.3.5). This means that
there is a strong connection between the introduction of new materials and processes
in the fab, the design options, and system architectures, the crucial and growing
middleware libraries (operating system and libraries that are supporting dynamic memory
and storage management, the parallelization of the tasks and threads over the
increasingly complex heterogeneous multi-core platforms, and so on), the algorithms
and final application functionality. This is a “stack” of various disciplines that requires
a networked model of industry collaboration (see Figure 1.3.6).
The sequential innovation process is outdated. There is a need to accelerate and make
more insightful choices in the innovation by co-optimizing all layers in this full stack.
This means it is required to really understand how a decision or boundary condition in
one layer impacts the whole stack and the products and business (models) of the
companies involved.
It is crucial for all this innovation potential that we, as an industry, consider that
semiconductor manufacturing is resource-intensive with respect to energy, water,
chemicals, and raw materials. It generates various classes of emissions, including
greenhouse gases and has a negative environmental impact due to mineral extraction in
mining and recycling operations very often done in economically challenged countries.
It has become clear that we need to look at the green and the digital transformations as
“twin challenges”: digital technologies will not only continue to create opportunities in
traditional sectors but will also increasingly help to meet challenges faced on our road
towards a healthy planet. But at the same time, we then must make sure that the negative
impact from semiconductor manufacturing and use is minimized. Design-Technology
Co-Optimization (DTCO) and System-Technology Co-Optimization (STCO) methodologies
and tools, building transversal knowledge from manufacturing to design to workloads,
provide an opportunity to develop a framework for early sustainability assessments of
semiconductor technologies. Life Cycle Analyses done at an early stage in the
development phase are mandatory to minimize both the energy consumption and the
environmental footprint by avoiding the use of rare or difficult-to-recycle materials. As
a result, “environmental scores” can be derived together with the established Power,
Performance, Area, Cost (PPAC) metrics enabling a holistic approach to account for the
environmental impact as well: PPACE [3].
The interplay of deep technology insight, sustainability goals and innovation at the
application and systems level is at the core of the EU Chips Act ambition. The sections
below illustrate this from different application perspectives and are only indicative of the
vast number of other opportunities in these and many other sectors.
978-1-6654-9016-0/23/$31.00 ©2023 IEEE

3. Compute from Heterogeneous Cloud to the Extreme Edge
The current high-end scaling roadmap incorporates options for continued dimensional
scaling with device and material innovations (see Figure 1.3.7) (together with suitable
context-aware interconnect schemes). The forksheet device (see Figure 1.3.8 a) has
recently been proposed as the most promising architecture to extend the GAA
nanosheet device generation [4], providing additional scaling and performance beyond
the 2nm technology node (down to the A7 generation). While device area reduction has
been driven by ever-tighter gate and metal pitches, further scaling is accomplished by
reducing the number of available intracell routing tracks (T). Nanosheet and forksheet
devices prove unsuitable for 4-Track (4T) standard-cell designs, while complementary
FET (CFET) devices (see Figure 1.3.8 b) provide a performant and cost-effective 4T
solution [5] starting from the A5 technology generation (see Figure 1.3.7). The materials
and process technology innovations this requires are matured in R&D pilot lines and
new integration schemes are under exploration, in close collaboration with the suppliers
of materials and equipment. When novel devices or interconnect schemes are
demonstrated in the advanced pilot line setting, they can be translated into a ‘research
PDK’, and later as a more mature PDK with more complete features, for IC designers
to assess the new technology and provide early feedback to tune the technology in line
with future applications needs. EDA tools for providing iterative versions of a PDK in a
more automatic way are necessary to fully exploit the potential of emerging
technologies.
A very close interplay of pilot line infrastructure and design platform innovation enables
early design excursions which allow exploring the circuit and systems impact of the
new options like a forksheet or CFET device architecture, 3D heterogeneous integration,
new interconnect options, Back-Side Power Delivery Network (BSPDN), compute-in-
memory, Voltage Gated Spin-Orbit Torque (VGSOT) MRAM, analog computing,
neuromorphic architectures, quantum technologies, RF options, and many more. The
EDA tool challenges multiply as we go below 2nm because the need for STCO (with
BSPDN, thermal vias, 3D floor planning, and so on) raises the complexity level of
manufacturing reliable chips. The pilot lines and EDA community need to act as one to
make an impact and timely create value downstream. This way the design community
is enabled to create the demand for high-end systems-on-chip that will spur economic
growth throughout the full stack.
The CMOS-based compute engines will be complemented by accelerators like compute-
in-memory, neuromorphic and quantum-based systems. Quantum computers are
hailed as a potentially disruptive computing concept in the space of supercomputing-
like applications such as advanced materials design, new drugs development,
computational chemistry, and cryptanalysis. The current state of the art (100s of
uncorrected quantum bits) is still many orders-of-magnitude away from theoretical
requirements (millions of quantum bits operating in synchrony as a fully ‘error-
corrected quantum computer’ [6]). Bridging this enormous gap will require a sustained
combination of brilliant ingenuity, conceptual breakthroughs, and dedicated engineering
work to reduce individual error rates and improve homogeneity. Given the heterogeneity
of the quantum computing technologies currently investigated worldwide
(superconductors, photonics, cold atoms, trapped ions, qubit on semiconductor, and
so on) and the relative immaturity of the state-of-the-art – with no winning solutions in
sight yet – this will not be a sinecure. Nevertheless, funding the research and
development into more mature, stable, reproducible quantum hardware technology,
and subsequently making such hardware technology widely available to the community
may help close the scaling gap from both sides. The quantum computing ecosystem is
to adopt a more sustainable, long-term innovation model known from the past decades
of semiconductor technology innovation, including a solid STCO approach to further
scaling.
Moving to the compute edge there are many other STCO requirements appearing.
Internet-of-Things (IoT) application end points are the interface between the digital and
the physical world and therefore are creating the data overflow. There is a clear need
for sensor fusion and new on-device compute paradigms in order to transform the raw
data into useful data as soon as possible (i.e. not send them to the cloud) to drastically
limit power consumption. For example, new perception modalities like infrared and
hyperspectral imaging, depth sensing, time-of-flight sensors, and so on, are enabling
rich AR/VR/XR and similarly at the actuation side, holography is being added to end-
point. These represent the next dimension in the sectors of AI and data handling. Such
complex applications pose a stiff challenge in dealing with highly heterogeneous data
streams in combination with real-time processing with a strong need to improve the
energy efficiency of computing.
The smart extreme-edge or IoT devices impose many analog and low-energy
functionality requirements and traditionally have been, for a combination of technical
and economic reasons, slow to adopt new semiconductor integration technologies.
New process nodes have, however, allowed the community to hugely improve the
performance of analog, RF, and mm-Wave design due to close co-design with the new
technology. For instance, innovations like all-digital PLLs and digital-style transceivers
essentially emerged thanks to the high time-domain precision becoming available in
ISSCC 2023 / February 20, 2023 / 10:40 AM
advanced CMOS at the expense of voltage headroom in older nodes and the related
design style. 1
FDSOI is unmatched for cost-effective markets requiring digital and mixed-signal SoC
integration and performance, with low power and intrinsic high robustness. FDSOI
technology is strongly positioned in the IoT market; it was “born and raised” in Europe
and is currently scaling to the 10nm generation. In the coming years the technology
will be further optimized for IoT and automotive applications, RF connectivity, 5G/6G
chips, microcontrollers, smart imagers and sensors, cybersecurity applications, and
wearables [7]. The next generation will be a Gate-All-Around (GAA) implementation
where there will be a lot of common challenges with the extended device roadmap for
leading-edge devices.
Heterogeneous integration of different functionalities – and hence different
semiconductor technologies – is extremely important in the edge-AI domain (see Figure
1.3.9). Starting from a deep understanding of the system workload, the system
architecture can be explored making use of the most appropriate combination of diverse
technology platforms. R&D on semiconductor technology, interconnect strategy,
reliability, thermal management, EDA for system partitioning, and so on, in close
concertation is required.
4. Connectivity
While data is becoming one of our most precious assets, the insatiable hunger for data
also drives technology and design to the extremes, both for the wireless and the wired
part of connectivity.
Wireline transceivers are the beginning and the endpoint of each fiber-optic link: in the
backbone of our internet infrastructure connecting countries and cities; in the access
networks (hybrid coax, fiber-to-the-home); in between servers inside data centers, and
in IO interfaces for large digital SoCs.
Scaled CMOS is in many cases both a driver for wireline as well as an enabling factor:
these transceivers are preferably implemented on the same CMOS chip as their digital
core. To cope with the ever-increasing need for capacity, baud rates are growing rapidly
versus the channel bandwidth: telecom applications will soon start deployment of
coherent transceivers with baud rates beyond 100Gbaud, with a doubling anticipated
in the next few years. Such transceivers rely on digital signal processing to overcome
bandwidth limitations and distortion of the channel and analog / opto-electronic front-
ends. At baud rates beyond 100Gbaud, the DSP cores need to handle multiple Terabit/s
throughput. This can only be realized within reasonable power and area requirements
using scaled CMOS. High baud-rate transceivers will therefore rely on the capabilities
of the latest CMOS nodes. Associated pilot lines and research PDKs will allow making
predictions regarding power, performance, and area trade-offs.
Optical transceivers are also the poster child for heterogenous integration. Photonic
integrated circuits (PICs) form a crucial part of these transceivers and can be realized
on Silicon Photonic or InP platforms. Silicon Photonics offer the advantage of dense
integration of both passive (wavelength multiplexing) and active functionality
(modulators and detectors) in a monolithic chip with high yield and manufacturing
throughput; optical amplification and lasers are not yet feasible although significant
research in this area is on-going. InP also allows active and passive functions in addition
to lasers and optical amplifiers but has less manufacturing throughput due to smaller
wafer sizes. With bandwidth requirements for the opto-electronic front-ends set to
exceed 100GHz, the inclusion of novel materials such as BTO, LiNbO3, PZT, graphene
and so on will be needed. Facilitating dense integration of photonic chips or chiplets
from different material systems with large-scale CMOS SoCs while maintaining signal
integrity requires advanced 2.5D and 3D heterogeneous integration technologies. These
include through-silicon vias, fine-pitch flip-chip, micro-transfer printing, and wafer-
bonding processes. While volumes are much smaller than in the consumer space, the
requirements of wireline transceivers will remain a driver for and adopter of these
advanced technologies—which can then percolate to wireless and other domains.
Indeed, the need for higher data rates also in wireless drives the carrier frequencies to
the mm-Wave spectrum, where bandwidth is available to accommodate the high data
rates. At these mm-Wave frequencies, which will go beyond 100GHz for the most
demanding high data-rate segment of 6G, the speed and power limitations of silicon
devices will necessitate the use of novel material systems and substrates, mainly for
power amplifiers. Four of these technologies are globally recognized to be at the core
of the next generation RF/mm-Wave front-end [8]: SiGe, FDSOI, GaN. and InP (see
Figure 1.3.10).
SiGe technology platforms enable high-performance RF Front-End thanks to extremely
fast Heterojunction Bipolar Transistors (HBT) and small CMOS nodes onto the same
die (down to 55nm like ST-B55x). It offers operating frequencies beyond 100GHz, large
bandwidth, low-noise and high-linearity potential and decent output power in the mm-
Wave mid- to high-bands.
DIGEST OF TECHNICAL PAPERS • 27
ISSCC 2023 / SESSION 1 / PLENARY / 1.3
FDSOI CMOS technology combines best-in-class electrostatic behavior and
attractiveness for both digital (28nm/22nm today, 10nm tomorrow), and analog/RF/mm-
Wave integration. Cut-off frequencies fT and fmax around 300GHz have been demonstrated
for the 28nm node [9], together with high-performance passive devices.
Further, GaN is a strong contender for medium to high output power wireless applications
from low-frequency bands up to mm-Wave ones, as it combines high output power with
a high energy efficiency. Applications include infrastructure (base stations), and cells
(small cells, picocells, and access points). Various flavours of GaN implementation exist
and GaN-on-Si gains traction over the more expensive GaN-on-SiC technologies.
Finally, InP allows increasing the wireless carrier frequencies in use, much above 100GHz
as the gains are higher than with other semiconductor technologies. HBTs and High
Electron Mobility Transistors (HEMT) have been demonstrated with fmax above 1THz. InP
PAs operating above 100GHz combine a high efficiency with an output power that beats
silicon-based (CMOS and BiCMOS SiGe) PAs such that their use in phased-array
transmitters leads to significant energy savings [8]. However, to scale to volume, InP
technology should be co-integrated with Si to add processing features that will benefit
system performance and integration. The cost effectiveness and performance/power
consumption trade-off will be achieved with hybrid solutions, enabled by the availability
of both single-technology components and integration technologies. Moreover, the
deployment of circuits that use III-V devices to the huge volumes that are expected for
6G can benefit from the research on integration of III-V devices on 200mm or 300mm
silicon wafers. Importantly, the heterogeneous nature of wireless communication,
consisting of a 2.5D or 3D combination of antennas as well as chips from dissimilar
materials and components in the package such as transmissions lines, heat spreaders,
and so on poses a challenge for EDA tools, that should be able to co-simulate this blend
of different circuits and components.
Three of the recommendations for the EU Chips Act that emphasize the need for the full-
stack innovation from leading European R&D actors [10] are: (i) support the complex
co-integration of mixed technologies by putting efforts into technologies that will help
co-integration at wafer level or in advanced packaging to maximize efficiency of individual
chips together into a single module, including the associated digital processes; (ii)
consider the system-level architecture for RF and mm-Wave systems that will make use
of advanced semiconductor technologies in a holistic approach of the best line-up of a
complete module, from antenna to digital; hardware suitable for high-frequency bands
equipment is a must-have, with embedded analog and digital signal processing; (iii)
networks will have to face complex partitioning for the expected wide variety of 6G
deployments which includes also satellite, device-to-device and vehicle-to-vehicle
communication, with an ever-increasing focus on distributed infrastructure and
disaggregation. Efforts must be put in considering together the impacts of these new
architectures on RF and mm-Wave front-ends and their associated basebands to drive
semiconductor technologies to enable the large benefits of these concepts.
5. Chips on Wheels
The increased dependence of the automotive sector on semiconductors has recently
been painfully demonstrated: in 2021 the global production of vehicles was 79.1 million,
but 9.5 million were delayed [11] due to increased lead times for the embedded
semiconductor components. The electronics content per vehicle increases steadily to
further support and drive automation, electrification, digital connectivity, in-cabin
entertainment, and security. To control, monitor and manage the myriad of systems in
a car, manufacturers have developed Electronic Control Units (ECUs). These ECUs
comprise at least one microcontroller and some other components, such as sensors,
connectivity, and discrete power. Each ECU module will house several chips and an
average car will probably have close to 100 individual modules [12]. Because of the mix
of sensors, mixed-signal and computational functions, advanced nodes and mature
nodes co-exist and are equally important for the automotive semiconductor market. The
main driver for advanced technology nodes in future cars is AI, needed for autonomous
driving [13] and in-car entertainment.
The history of cost pressure has partly driven the use of mature nodes, as until recently
output from depreciated fabs could meet the needs. Moving forward, either these
functions will require redesign into more advanced nodes to move along with foundry
volume, or dedicated investments in these mature fabs will be required. Other industries
with significant volume scaling, such as the smartphone industry, have seen a similar
evolution for components that were traditionally implemented in mature or more exotic
nodes. This has driven significant research and development on the design side,
especially for mixed-signal components and IP. In 2021 the share of the automotive
semiconductor market was 8% of the global semiconductor market and this is expected
to grow to about 14% by 2030. In Figure 1.3.11, it is seen that the automotive
semiconductor markets will be multiplied by a factor 3 from 2020 to 2030 [14]. It is the
fastest growing segment, with almost twice the growth rate of the largest current market
segments (wireless communication and computing/data storage). ASIC design skills are
being built up across the industry, including OEMs and tier-1 companies, that start
designing these components. It is interesting to point out recent estimates indicating
28 • 2023 IEEE International Solid-State Circuits Conference
that by 2026 the demand will exceed the supply also at nodes beyond 7nm, based on
the required number of SoCs and FPGA chips. As acknowledged earlier, AI and in-car
entertainment domains are the main computational loads and the driver for much more
advanced digital programmable platforms, relying on automotive-specific STCO taking
in all relevant technology and design features mentioned in the compute section above.
Node scaling is much less important for power semiconductors – such as IGBTs – than
materials and process development. It is important to note that Silicon Carbide (SiC) and
Gallium Nitride (GaN) are becoming more popular for power electronics in automotive
applications, as they can handle much higher voltages than silicon. In particular, SiC
offers higher-speed switching which is of key importance for battery management.
Power-semiconductor manufacturers are setting up specialized fabs with dedicated
equipment parks and power processes.
6. Chips Supporting Health
The European medical technology market, with an estimated size of more than 140 billion
EUR in 2020 [15], is one of Europe’s most diverse and innovative sectors, as
demonstrated by the number of filed patents [16] (see Figure 1.3.12). Silicon technology
has a tremendous potential to help transform healthcare. Combining silicon technology
with other technologies and system innovations will significantly improve healthcare
affordability, quality, and coverage. As advanced lithography enables the fabrication of
silicon features with similar dimensions as biology elements such as cells, antibodies
and DNA, CMOS technology is also expected to bring plenty of additional functionality
to healthcare devices.
Although the industry has already been working for many years on a shift towards digital
healthcare and remote patient care, the pandemic has accelerated this significantly. This
would not have been possible without silicon innovations in low-power, highly integrated
and connected medical devices enabling at-home diagnostics, patient monitoring, and
point-of-care solutions which have been researched and developed in recent years.
Similarly, a growing industry interest exists in smart, connected implantable and
ingestible devices. Due to the extreme size and power constraints, success depends even
more on CMOS technology that can integrate ultra-low-power sensing, actuation, data
analytics and connectivity into complex SoC and SiP solutions. Advanced medical
imaging is another area that highly depends on specialized technologies.
However, the need for silicon technology is not limited to medical devices. Rapid DNA
sequencing is having a big impact on human-disease therapies and personalized
medicine. The need for reliable, fast, and easily deployable large-scale DNA sequencing
has been made very clear by the recent pandemic. Nanopore-based sequencers [17]
have the potential to sequence the entire human genome quickly and reliably for less
than 100 USD, which can be further accelerated by co-integration of synthetic nanopores
with advanced-node CMOS electronics. Such an approach can produce highly
parallelized, high-throughput, miniature, and portable DNA sequencing devices. Looking
further into the future, advanced genomics and proteomics have even larger scaling
challenges. Especially for proteomics, the required dynamic range is orders-of-magnitude
larger due to the abundance of interfering proteins, thus requiring extremely high-
throughput solutions.
Similar co-integration approaches are currently used to fabricate advanced CMOS multi-
electrode arrays (MEAs) for drug discovery in the pharmaceutical industry [18]. Such
devices can significantly increase the throughput of in-vitro pre-clinical drug trials, thus
reducing the development time and cost (currently up to 15 years and >2 billion USD,
respectively) and increasing the success rate [19]. Moreover, advanced CMOS
functionality can also address the need for personalized medicine (cell and gene
therapies, cancer treatments or antibiotics) by enabling profiling of individuals using
personalized electro-physiological fingerprints and organs-on-a-chip approaches [20].
Another area where silicon technology can make a difference is in drug and vaccine
manufacturing. Biological drugs (including vaccines) require the development and
upscaling of biomanufacturing processes. Quality control and on-line monitoring of the
bioprocesses is one of the major cost-driving factors in the manufacturing process.
Improving yield and reducing cost in biomanufacturing will require innovative closed-
loop sensing solutions. MEA chip solutions can monitor cell viability, important
metabolites, and environmental factors in real-time, and steer the process accordingly.
All applications mentioned above require not only ICs, but also special materials,
advanced microfluidics, surface chemistry, and biology. This offers the opportunity to
set up suitable multi-disciplinary pilot lines to accelerate innovation in these areas.
Finally, just like in other industries, various medical-technology domains will eventually
face a big data problem. This is already apparent in DNA sequencing and will only be
more apparent in next-generation sequencing and advanced genomics and proteomics
[21]. Also, medical imaging is an area where AI-based analysis is getting a stronger
foothold. The performance requirements of these complex digital systems are extremely
high. Moreover, for many of the envisioned deployments, limited size and bounded
energy availability will make CMOS scaling even more needed. Hence, access to advanced
technology nodes will be essential to meet those demanding specifications.
978-1-6654-9016-0/23/$31.00 ©2023 IEEE

In all healthcare-related examples mentioned above there is a clear need to connect the
specifications and boundary conditions to the technology, and validate early prototypes
with clinicians, patients, biotech companies and labs and other stakeholders. This is
an area where the connected pilot lines and the design platforms will make a huge
difference.
7. Talent
To be successful in realizing the full potential of the above technology and market
dynamics (and many more we could not address in the frame of this paper), an
interconnected set of actions will be required on the cloud-based use of IP and tools,
on building a close encounter of system and technology, on getting the required
financial support in place, and so on. But if there is one Achilles heel of such audacious
plans, it is the lack of talent. There are currently over 60,000 vacancies for electronics
engineers in Europe [22], while all of the above ambitions require highly skilled and
well-trained individuals, and a lot of them. In Europe the number of students in science
and engineering and technically oriented curricula is too low. The efforts to train the
young talent in technology and design need a ramp-up on all fronts. The
EUROPRACTICE [23] program that enables circuit and system design for more than
600 European university departments and research institutes asserts that close to half
of the research teams innovate in mature technology nodes (130nm and higher), as
can be seen in Figure 1.3.13. This figure illustrates that there is a lot of innovation power
in the mature nodes, but also that design experiments in the leading-edge nodes from
academia are underrepresented. Also, the typical ISSCC paper distribution reflects this
large presence of innovative designs in the mature nodes, which can perfectly serve
the application domains where many university groups are focusing on, such as medical
and even RF. The lack of academic activity in the most advanced technologies can also
be explained by 1) the fact that design platforms are difficult to access and to design in
for university teams; and 2) cost issues that do not allow moving towards silicon
validation.
Access to self-learning material, tools, and multi-project wafer shuttles, also for
advanced technologies, is paramount in making sure the young graduates are ready
for industry. Also, efforts are ongoing in Europe to tightly interweave formal education
with industry experience, lifelong learning and international collaboration. Having the
most experienced designers in the industry engage in these programs is essential. The
pilot line infrastructures, closely networked with the many advanced university nano-
labs, can attract new generations of engineers, materials scientists and physicists, and
inspire them to tackle the many challenges faced when developing new semiconductor
technologies, which in turn are key to develop a myriad of novel applications.
The attractiveness of the professions related to the semiconductor industry suffers from
the invisibility of the ever-shrinking electronic systems. To motivate the young
generations, we must actively increase the awareness that our industry is key to help
solve the important challenges of the 21st Century. We urgently need to get the message
across that climate, health, safety, and human connectedness all require adequate digital
backbones, if we want to stand a chance of attracting the right talent.
8. Conclusions
With the paramount importance of semiconductors in our everyday life in mind, the EU
Chips Act aims at shoring up Europe’s position in the semiconductor value chain.
Semiconductor technology is diversifying and becoming application-specific, and a
growing number of segments of the semiconductor market will thrive on a symbiosis
between advanced and mature technology nodes. The pilot lines and design technology
platforms that are at the core of ‘pillar one’ in the EU Chips Act enable an acceleration
“from the lab to the fab”. Also, a clear strategy for making the whole industry more
sustainable will need to be adopted. To be successful in the market, full-stack innovation
involving the intimate interplay between deep technology insight, SoC architectures and
innovation at the system level is essential. This paper illustrates this through the lens
of various application domains: (i) computing is becoming increasingly heterogeneous
and STCO will allow design excursions to obtain early insights into the circuit and
system impact; (ii) communication systems will see profound innovations involving
co-integration of mixed-signal and RF technologies and with the advent of 6G, networks
will face an increasingly complex partitioning, while wireline communication drives the
excursions in advanced nodes and integration of photonics; (iii) today chips and the
embedded software define what age the car is and the need for advanced nodes will
grow while deep semiconductor technology insight is essential for the OEMs; (iv)
healthcare is one of Europe’s most diverse and innovative market segments and it is
being disrupted through advances in semiconductor technology and design.
The innovation potential envisaged by Pillar One of the European Chips Act hinges on
several key success factors: talent, IP access, a cloud-based design environment, and
early access to novel technology features.
Acknowledgement:
The authors acknowledge the support by R. De Keersmaecker in writing the paper and
by C. Ringoet for the illustrations. We also acknowledge the input from F. Catthoor, J.
Craninckx, K. De Greve, N. Horiguchi, A. M. Jagadeesa Das, C. Mora Lopez, P. Ossieur,
ISSCC 2023 / February 20, 2023 / 10:40 AM
M. Peeters, K. Philips, P. Vandenameele, A. Van den Bosch, N. Van Helleputte, M.
Verhelst (imec), C. Reita (CEA/Leti) and P. Bressler (Fraunhofer). 1
References:
[1] EC communication COM (2022) 45 “A Chips Act for Europe”, 8 Feb 2022
[2] https://blogs.synopsys.com/from-silicon-to-software/2022/03/23/cloud-based-chip-
design-and-verification-2022/
[3] Garcia Bardon M. et al., “DTCO including Sustainability: Power-Performance-Area-
Cost-Environmental score (PPACE) Analysis for Logic Technologies”, IEDM 2020
[4] Mertens H. et al., “Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned
Gate Cut, and Isolation between Adjacent Source-Drain Structures”, paper 23.1 at IEDM
2022; Gupta M.K. et al., “A Comprehensive Study of Nanosheet and Forksheet SRAM
for Beyond N5 Node,” in IEEE Trans. on Electron Devices, vol. 68, no. 8, pp. 3819-3825,
Aug. 2021, doi: 10.1109/TED.2021.3088392.
[5] Schuddinck P. et al., “PPAC of sheet-based CFET configurations for 4 track design
with 16nm metal pitch”, 2022 IEEE Symposium on VLSI Technology & Circuits; doi:
10.1109/VLSITechnologyandCir46769.2022.9830492
[6] Martin D., “Turning a million-qubit quantum computing dream into reality”, May
10, 2022, https://www.nextplatform.com/2022/05/10/turning-a-million-qubit-quantum-
computing-dream-into-reality/
[7] Moursy Y. et al.,” A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-
Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30%
Power Reduction in 22nm FDSOI Technology”, 2021 IEEE Int’l Solid-State Circuits
Conference.
[8] Strinati E.C. et al., “The Hardware Foundation of 6G: The NEW-6G Approach,” 2022
Joint European Conference on Networks and Communications & 6G Summit
(EuCNC/6G Summit), 2022, pp. 423-428, doi:
10.1109/EuCNC/6GSummit54941.2022.9815700.
[9] Esfeh B.K. et al., “28 nm FD SOI Technology Platform RF FoM”, 2014 SOI-3D-
Subthreshold Microelectronics Technology Unified Conference (S3S), 2014, pp. 1-3,
doi: 10.1109/S3S.2014.7028208.
[10] CEA-Leti, imec and Fraunhofer, “6G leadership through European Semiconductor
Technology and Design Pilot Platforms” (Position Paper)
[11] CLEPA, https://clepa.eu/mediaroom/global-production-shortfall-of-nearly-10-
million-vehicles-in-2021-highlights-urgent-need-for-eu-chips-act/
[12] Electronic Sourcing, “How many chips are in our cars?”, 4 May 2022,
https://electronics-sourcing.com/2022/05/04/how-many-chips-are-in-our-cars/
[13] Reuters, “Samsung in talks with Tesla to make next-gen self-driving chips”, 23
Sept 2021, https://www.reuters.com/business/autos-transportation/samsung-talks-
with-tesla-make-next-gen-self-driving-chips-korea-economic-daily-2021-09-23/
[14] ASML, “EU Chips Act – Position paper”, Feb 2022,
https://www.asml.com/en/news/press-releases/2022/asml-position-paper-on-eu-chips-
act/
[15] MedTech Europe, 2020, European IVD Market Statistics Report 2020. 2020 IVD
market size data is preliminary and is based on MedTech Europe Statistics Programmes
- Fitch Solutions, 2021, Worldwide Medical Devices Market Factbook 2020
[16] MedTech Europe, “The European Medical Technology in figures – 2021”,
https://www.medtecheurope.org/wp-content/uploads/2021/06/medtech-europe-facts-
and-figures-2021.pdf/
[17] Feng Y. et al., “Nanopore-based fourth-generation DNA sequencing technology”,
Genomics Proteomics Bioinformatics. 2015 Feb;13(1):4-16.
[18] Müller J. et al., “High-resolution CMOS MEA platform to study neurons at
subcellular, cellular, and network levels”. Lab Chip. 2015 Jul 7;15(13):2767-80; and
Lopez C.M. et al., “A Multimodal CMOS MEA for High-Throughput Intracellular Action
Potential Measurements and Impedance Spectroscopy in Drug-Screening Applications,”
in IEEE Journal of Solid-State Circuits, vol. 53, no. 11, pp. 3076-3086, Nov. 2018, doi:
10.1109/JSSC.2018.2863952.
https://www.news-medical.net/news/20190131/Enhancing-HD-MEA-Systems-with-
CMOS.aspx/
[19] Sun D. et al., “Why 90% of clinical drug development fails and how to improve
it?” Acta Pharm. Sin. B. 2022 Jul;12(7):3049-3062.
[20] Jodat Y.A. et al., “Human-Derived Organ-on-a-Chip for Personalized Drug
Development”. Curr. Pharm. Des. 2018;24(45):5471-5486.
[21] Zou Y. et al., “Parallel computing for genome sequence processing”, Briefings in
Bioinformatics, Volume 22, Issue 5, September 2021.
[22] EC Staff Working Document 147, “A Chips Act for Europe”, May 2022
[23] www.europractice-ic.com; Hoofman R. et al., “Next Europractice eXtended
Technologies and Services”, presented at Smart Systems Integration; 13th Int’l Conf.
and Exhibition on Integration Issues of Miniaturized Systems, 10-11 April 2019,
https://ieeexplore.ieee.org/document/8727800
[24] Subramanian S. et al., “First Monolithic Integration of 3D Complementary FET
(CFET) on 300mm Wafers”, 2020 IEEE Symposium on VLSI Technology,
doi:10.1109/VLSITechnology18217.2020.9265073.
DIGEST OF TECHNICAL PAPERS • 29
ISSCC 2023 / SESSION 1 / PLENARY / 1.3

Figure 1.3.1: Europe can build on existing strengths like the unique position of certain
materials and equipment companies (e.g., ASML, SOITEC, ASM-I, ...), leadership Figure 1.3.2: Pillar one of the EU Chips Act combines design and system integration
positions in R&D on the industrial 300mm wafer standard (imec, CEA/Leti, infrastructure and an upscaling of advanced and leading-edge semiconductor
Fraunhofer), and existing ecosystems for chip manufacturing. technology pilot lines, allowing to demonstrate new system concepts.

Figure 1.3.3: A continuum of pilot-line maturity, going from immature process

technology, research PDK and basic functionality tests to facilities in industrial Figure 1.3.4: Pilot-line technology supported by design enablement, allowing to
setting that allow for first industrial deployment and risk production. explore advanced technologies in virtual prototyping.

Figure 1.3.6: An industry-grade pilot line infrastructure at RTOs supports the

Figure 1.3.5: In full-stack innovation, the needs and requirements dictated by the networked innovation model bringing the full value chain in close contact around
future applications are translated in design and architecture challenges and inspire generic, precompetitive challenges in technology development as well as in
technology innovations. innovation tracks focused on domain-specific devices, circuits, and systems.

30 • 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

 ISSCC 2023 / February 20, 2023 / 10:40 AM

1
10 nm
23 nm
Si Si
WSi=23nm
W Si Si TSi=5nm

SiN TiAl
SiO2 HfO2
liner

(a)


 

  
 


 



    

   






 
   

   





  



(b)

Figure 1.3.7: The semiconductor roadmap extends along several concurrent tracks
that allow to co-optimize the circuit and system performance, power, area, and cost
through the technology options delivered by dimensional scaling, device and material
innovations.
Figure 1.3.8: TEM cross-section image of an NMOS forksheet device [4] (a) with
bottom dielectric isolation, after replacement metal gate processing; and (b) TEM
cross-section images of a CFET [24]: (left) bottom PMOS FinFET and (right) top NMOS
nanosheet FET in a CFET device. PMOS and NMOS have LG = 20nm, fin pitch = 45nm
and gate pitch = 90nm.

Figure 1.3.9: Heterogeneous integration, 3-D stacking and a rapidly evolving chiplet Figure 1.3.10: A comparison of the frequency performance of the major technologies
approach allow to build complex systems-on-chip. for the mm-Wave frequencies beyond 100 GHz, the high data-rate of 6G.

Figure 1.3.11: Analysis of the growth of advanced and mature nodes of semiconductor Figure 1.3.12: Top 10 technical fields in patent applications: number of patent
chips in automotive applications. applications filed with the European Patent Office in 2020.

DIGEST OF TECHNICAL PAPERS • 31

ISSCC 2023 / SESSION 1 / PLENARY / 1.3

Figure 1.3.13: Distribution of technology nodes for the circuits fabricated through
EUROPRACTICE by European universities and research centers (2021 data).

32 • 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

ISSCC 2023 / SESSION 1 / PLENARY / 1.4
1.4 5G Drives Exponential Increase in Processing Needs Across
all Industries
Erik Ekudden
Senior Vice President & Chief Technology Officer, Ericsson, Kista, Sweden
1. Introduction
The extreme development of semiconductor-based compute technologies has not
escaped anyone but the fact that mobile communications has followed a similar
trajectory may be less obvious to most. Over five generations of mobile
communications, data rates, and capacity has improved with more than six orders-of-
magnitude, and this trend shows no signs of weakening. Mobile communications
equipment (both infrastructure and devices) is among the most complex and advanced
electronics produced.
Mobile infrastructure goes far beyond being a means of just communications. It is also
a platform for continuous innovation. The smartphone revolution would not have
happened without 4G LTE, and the industrial digitalization wave is very much fueled by
5G NR, and with the network compute fabric introduced with 6G, the possibilities are
essentially endless.
Modern innovation in industry, services, and consumer products is very much driven
by connectivity, data, and intelligence. This paper intends to demonstrate how the rapid
evolution of mobile infrastructure fuels an as dramatic increase in computational needs
not only in wireless infrastructure but also in applications.
1.1 The Mobile Network
A mobile communication network comprises of two main domains: the core network
(CN) and the radio access network (RAN). The core network manages things like traffic
control, billing, and the communications contexts of all connected devices, effectively
hiding the mobility to any application. The radio access network is the fabric that
connects all cell towers and manages resources such as spectrum in a highly optimized
manner. The design philosophy of modern networks is to offload as much complexity
as possible from the devices, for reasons of economy of scale, and reduced device
costs and energy consumption.
With the ever-growing traffic, cellular networks move to higher frequencies to access
new frequency bands with more bandwidth. Higher frequency bands have shorter range
which calls for more advanced antenna systems and denser deployments of radio base
stations and towers. This constant increase in management systems complexity and
signal processing capacity drives a drastic increase in computing needs.
2. 5G as a Driver for Compute Needs
2.1 Connectivity and Traffic
The main challenge of the mobile communications industry is the exponential growth
in traffic. The Ericsson Mobility Report [1] tracks, correlates, and projects the evolution
of traffic in mobile networks. Comparing the traffic volume with a normalized compute
index it becomes obvious that the collective compute power of a mobile
communications network has this same exponential development. To add further to
the challenge, the wireless industry is committed to achieving this at a fixed energy
budget.
5G enables much higher data rates, lower latency, and higher reliability than 4G and its
predecessors, but this is achieved through more advanced concepts. The radio-near
processing needs are essentially proportional to the bandwidth and the number of
antennas. For 4G LTE an advanced base station has two antennas and a carrier
bandwidth of some 20MHz. For 5G the numbers can be 64 and 100MHz, translating to
an increase in computational needs of roughly 160 times.
Deeper into the network, compute requirements grow more proportionally to transferred
user data. Still the increase is significant as 5G-enabled devices offer up to two orders-
of-magnitude higher peak data rates together with much lower latency. An overview of
the distribution and increase of processing in 5G can be seen in Figure 1.4.1.
2.2 Innovation and Applications
5G is a key enabler for taking the next step in mobile communications, for humans as
well as for machines. Catering for reliable, high-speed, and low-latency access to cloud
or other networked resources forms an extremely strong platform for driving innovation
[2].
Cloud robotics [3] is one example of an application that is taking its first steps on the
factory floor but has mass market, consumer driven potential. With a reliable and highly
ISSCC 2023 / February 20, 2023 / 11:15 AM
secure connection to cloud compute resources, the image of the traditional industrial
robot in the shape of a giant arm reaching from the floor loses its validity. A cloud 1
powered robot can be manufactured at a fraction of the cost of one with embedded
intelligence, it can update its software on a daily basis, and it can learn from other robots
that do not even need to be nearby. With sensors such as vision and hearing, the robot
can become both more exact, efficient, and safe. A cloud robot however still needs
massive compute resources, but they can be shared with others through the cloud.
Personal mobility is another example of an area going through a massive transition,
much fueled by advanced connectivity. Vehicles can for instance collect and process
video feeds for updating a real-time digital twin of a city for use by other traffic, even
including bicycles [4]. Real-time maps including traffic flow can be constantly updated
for navigation and traffic management. Pedestrian flows can be accurately monitored
to optimize and manage public transportation, the opportunities are endless, and the
sustainability gains considerable.
All the examples above, and of course many more, rely on advanced sensors, large
amounts of data, and advanced computing, driving the needs for evermore powerful
and energy efficient semiconductors.
3. Optimized Semiconductors for Communication Infrastructure
3.1 The Semiconductor Evolution
Across essentially all industrial sectors, advanced semiconductor technology is a key
enabler for innovations in customer offerings and internal efficiency. The increase in
the value of data and the related push for AI are examples of forces that further increase
the demand for compute power and storage, which translates directly into more
complex and powerful semiconductors. The exponential evolution, essentially following
what is known as Moore’s Law [5] has provided large and continuous improvements
in computational performance at constantly reduced cost. At a component level the
evolution has however not been linear but includes several stepwise changes.
During the 1980s and 1990s, often referred to as the Megahertz era, processor
performance increased mainly through an increase of clock rate. However, the
diminishing returns of this linear development pushed for new approaches and around
the turn of the century the industry entered the Multicore era, adding more and more
processing elements to systems. With this paradigm now facing challenges in scaling
and even physical distances on chips, we are now entering the Architecture era with
application-specific computing and algorithmic acceleration as central elements.
Heterogenous integration is an important tool in the Architecture era. Putting multiple
tiles of silicon, each optimized for purpose and functionality will provide means for
further system scaling. This technology is not new but now there are forces pushing a
potential multi-vendor chiplet ecosystem. A promising development is the newly started
Universal Chiplet Interconnect Express [6] . Heterogenous integration opens
opportunities to build systems in a package by combining silicon tiles designed in
specialized technologies. An important example is combinations of analog and advanced
digital tiles in the same package.
3.2 Communication Infrastructure Portfolio
Ericsson’s portfolio [7] is focused on all aspects of mobile communications
infrastructure with its radio-near parts being the most computationally intense. To keep
its technology leadership, Ericsson has done highly customized silicon for these
products for decades and radio access network processing is for this reason the focus
of this paper. Figure 1.4.2, shows an overview of the Ericsson network portfolio.
3.3 Radio-Near Processing
To optimize the utilization of the limited resource of radio spectrum, radio access
networks use massive amounts of signal processing to amplify, filter, shape, code, and
decode radio signals. Figure 1.4.3 shows the typical RAN processing functions with the
connection to the core network to the left and the antenna to the right. The differences
between the transmitted and received signals drive differences in algorithms,
processing, and analog implementation close to the antenna.
3.3.1 Ericsson Silicon
Ericsson has developed highly specialized silicon for many product generations but
significantly increased investments in recent years. Ericsson Silicon [8] is a tailor-made
family of advanced chipsets that integrates a mix of compute and signal processing
elements, high-speed shared and dedicated memory, digital logic accelerators,
switching fabrics, and key security technologies for both protocol acceleration and
hardware level intrusion protection. It is a modular architecture that scales across
Ericsson’s entire portfolio. Ericsson Silicon enables enhanced network performance,
shorter time from invention to customer, and highly optimized energy efficiency.
DIGEST OF TECHNICAL PAPERS • 33
ISSCC 2023 / SESSION 1 / PLENARY / 1.4
3.3.2 The Analog Front-End
The analog front-end contains both receive and transmit functions with very different
challenges. In the receive signal path the wanted signal may be just a few microvolts
causing requirements on dynamic range with over 100dB to achieve the needed receiver
sensitivity. In the transmit path the output power can be hundreds of watts with extreme
requirements on power efficiency, spectral purity, and linearity. Given these
fundamentally different challenges, co-integration using the same semiconductor
technology is not trivial, and involves trade-offs related to speed and power capabilities.
As a result, cost-efficient heterogenous integration of semiconductor technologies are
becoming a growing area of importance for the industry.
Apart from the plain analog functions, the front-end subsystem is also responsible for
conversion to and from the digital domain, typically at gigahertz sample rates. Given the
frequency band fragmentation below 10GHz, the need for flexible multiband front-end
architectures has pushed data converters to handle sampling at radio frequency while
still meeting very stringent performance requirements. As a result, adding advanced
correction processing to the converter subsystem is needed and represents a growing
field of research. All in all, this has pushed the data converter development to use leading-
edge CMOS technologies and is another proof point that heterogeneous integration will
gain importance.
3.3.3 The Digital Front-End
The digital front-end (DFE) processes the digitalized radio signal, shaping, and filtering
it to the communication standard’s requirements. Innovative concepts such as AI-
assisted pre-distortion of transmit waveforms, dynamic resolution arithmetic, and
algorithm-specific accelerators are key to reaching the very tough requirements on
energy budget as well as cost. Energy is important not only because of the cost of
operation but also in terms of reliability and life span.
Radios are in most cases tower-mounted outdoors and passive, convection-based
cooling system is far more reliable and robust than one with moving parts. In addition
to a harsher environment the big challenge in the DFE domain is the increasing amount
of processing driven by the increased number of antennas times increased bandwidth.
tracking. Historically Moore’s Law has enabled this increase in compute, but how will
the industry address this need when Moore’s Law is slowing down?
Through the many engagements with other industries, it is clear to Ericsson that it will
not stand alone facing this challenge. The products of the future are connected,
intelligent, and have sensing capabilities. Massive amounts of data will be collected,
processed, and transported by vehicles, industrial equipment as well as consumer
products. The race for evermore intelligent and connected products happens in close
symbiosis with the equally rapid development of even more performant infrastructure.
Mobile communication is becoming a critical service for society in general, supporting
industrial production, power generation, healthcare etc. There are multiple examples of
enhanced sustainability driven by improved connectivity, including video conferencing
to reduce travel. The demands on the communication infrastructure will continue to grow,
and the industry relies on semiconductor and computational system innovations.
References:
[1] https://www.ericsson.com/en/reports-and-papers/mobility-report. [Online]
[2] https://www.ericsson.com/en/reports-and-papers/white-papers/5g-wireless-
access-an-overview. [Online]
[3] https://www.ericsson.com/en/reports-and-papers/ericsson-technology-
review/articles/cloud-robotics-5g-paves-the-way-for-mass-market-automation.
[Online]
[4] https://www.ericsson.com/en/future-technologies/networks-as-a-platform-for-
innovation/5g-advanced-driver-assistance-systems-adas. [Online]
[5] https://en.wikipedia.org/wiki/Moore%27s_law. [Online]
[6] https://www.uciexpress.org. [Online]
[7] https://www.ericsson.com/en/portfolio. ericsson.com. [Online]
[8] https://www.ericsson.com/en/ran/ericsson-silicon. [Online]
[9] https://www.ericsson.com/en/blog/2020/9/case-for-integrated-high-performance-
ran-processing. [Online]

3.3.4 Custom Processor Cores

Advanced radio concepts like antenna beamforming, MIMO, and AI-assisted modulation
schemes offer significant improvements in performance but also require massive
amounts of signal processing/compute resources.

Requirements on cost, size, and energy consumption exclude the use of off-the-shelf
processor chips which has led Ericsson to develop its own massively parallel DSP
processor architecture known as the Ericsson Many-Core Architecture (EMCA) [9]. The
EMCA architecture enables massive parallel processing of signals through a large pool
of DSP cores sharing a common low latency memory and a set of specific hardware
accelerators.

While EMCA is optimized for radio physical layer procession like FFT, FEC coding, and
beamforming. Higher protocol layers are typically handled using more traditional
processing architectures, albeit still optimized for the purpose. Packet processing in the
user plane can be relatively efficiently implemented on network-accelerated general-
purpose processing (GPP) cores. Due to the possibility of exposure of user data, all
digital parts of Ericsson silicon are protected with advanced and hardware-based
intrusion and compromise protection systems.

Going forward, the increased user data throughput, lower latency, and more complex
control structures is the main compute challenge in this domain. Further integration of
optics may support some performance increase as the interconnect part of the
networking solutions are becoming challenging.

4. Conclusion
In a 5G mobile network, more and wider antenna signal streams combined with more
advanced algorithms have significantly increased the compute demand in the mobile
network infrastructure. Advanced ASIC design with custom processor cores and
accelerators in the latest semiconductor technology combined with advanced packaging
has been Ericsson’s very successful recipe.

With 6G on the horizon, there is no doubt that the requirements on bandwidth, reliability,
security, sustainability, and cost will continue to grow exponentially. However, looking
ahead, keeping up with Moore’s Law just gets tougher and tougher.

In Figure 1.4.4 there is a correlation between the mobile network traffic growth and the
aggregated compute demand in mobile network infrastructure. So far there is good

34 • 2023 IEEE International Solid-State Circuits Conference 978-1-6654-9016-0/23/$31.00 ©2023 IEEE

 3.2 Communication Infrastructure Portfolio
ISSCC 2023 / February 20, 2023 / 11:15 AM
3.2 Communication Infrastructure Portfolio

Conclusion

  






  




  


   

   



Figure 1.4.1: 5G increase in compute. 3.3 OverviewRadio-Near

Figure 1.4.2: of Ericsson’sProcessing
network portfolio.
3.3 Radio-Near Processing

Figure 1.4.4: Mobile network traffic evolution in Exabytes per month, including
projection to 2027 (line) and total processing delivered to radio access networks [+],
scaled to traffic evolution. As can be seen, the RAN processing needs increase with
Figure 1.4.3: Radio access network processing chain. the mobile network traffic.

DIGEST OF TECHNICAL PAPERS • 35