Edge - Triggered

6.3.2 Dynamic
Transmission - Gate Registers
dynamic transmission gate positive edge-triggered register based on the
A
master-slave concept is shown in Fig 6.17.

CLK
CLK

A B
T2 S
D TË
C1

CLK
CLK
I
Master Slave

Fig 6.17 Dynamic positive edge- triggered register

SyuentialLogic Circuit Design 6.17|
the Fig 6.17 TË and T; are transmission gates and I, and I, are inverters,
Cjand1Ch are eequivalent capacitances at node-l and node-2.

=0
CLK
()
Transmission gate T,is ON and T, is OFE.
o Input data D is sampled on storage node 1, which has an equivalent

capacitance C, consisting the combination of gate capacitance of Ii, junction

capacitance of T, and an overlap gate capacitance of T,.
During this period, the slave is in a hold mode and node 2 is in the high
impedance (floating) state.

) CLK=1
o On the rising edge of clock, transmission gate T, is ON and T, is OFF.
Hence, the value sampled on node 1 at CLK = 0is propagated to an
output Q.
o Thus, node -2 stores the inverted value of node-1,
A Setup Time
The setup time of this circuit is simply the delay of the transmission gate and
it corresponds tothe time taken by node -1 tosample the D inpu.

Propagation Delay
The propagation delay is equal to two inverter delays plus the delay of the
transmission gate T2.

IAdvantages
) An eficient implementation is achieved due to the use of only eight
transistors. If NMOS-only pass transistors are used, then six-transistors
implementation is achieved.
(i) Used in high performance and low power systems.
6.18
CIlocked CMOS (C²MOS)
Register VLSI Design
6.3.3
reduce power dissipation and
ClockedCMOS (C'MOS) is used to
and to increase the speed. layout size
shows a positive edge-triggered register based on the
Fig 6.I8 master-
& concept which is insensitive to clock overlap. This circuittis also called
-slave
register.

VpD Voo

M2 M6
CLK
M4 Mg
X

CLK
M3 CL1 M7
CLK

M1 M5

Master Slave

Fig 6.18 CM0A register

) cuK =o(CLK =1):
oMaster stage is ON and acts as an inverter. i.e., it samples the inverted input D
onthe internal node X. This is called evaluation mode, whereas the slave is in
a hold mode (or) high impedance mode.
oIn Slave stage, M, and M, transistors are OFF, decoupling an output ron u
input. The output Qretains its previous value stored on the output capacitt
yemia lLogic CircuitDesign 6.19

CK=
1

The transistors M, and M, are OFF and the master is in the hold mode. The
o
transistors M, and Mg are ON and the slave is said to bee in an evaluation
mode.

o The value stored on capacitor Cu is transmitted to the output node through

the slave stage, which acts as an inverter. The output on Q is actually an
inverted form of the input.
AC'MOS register with CLK & CLK clocking is insensitive to overlap, as
long as the rise and fall times of the clock edges are sufficiently small.
621 Bistability Principle
Satic latches use positive feedback so that bistable circuit can be formed. I.
has beo stable states that represent 0' and '1
Two inverters are connected in cascade to form a basic bistable circuit as
shown in Fig 6.4.
Vi Vot = Vi2 Vo2

Vo2 = Vit

Fig 6.4 Two cascaded inverters

Voltage- Transfer Characteristics (VTC):
oThe VTC of the first inverter .i.e. Vol versus Vi is given in Fig 6.5 (a) and the
dnverter ie. Voa Versus Vp is given in Fig 6.5 (b). This is plotted by
Considering that Vi =Vol:
 o o o 6.6|
required externally
Ino circuit The three The ofNow,
the Vo1
order o resulting
twpossible
is firstassume
to voltage (a)
to
makechange to operating inverter
change operating VTC that
transfer Fig
voltage an
its its stableany at of Vil,output 6.5
operating
operating curves points two as VTC
gain shown Vip = Vo1
cascaded of Vi1
of as the of
inverter intersects by two
point point. point, shown second
the cascaded
remainwi l it inverter (c) V2 = Vo1
loop a in dottedinverterVo2 iS C
sufficiently at
three Fig
greater 6.5(c). (basic lines inverter Vin=Vo2
points B
in
than large in bistable Fig (b)
its (A, connected
unity. 6.4.
external staftoercat B,
element) Vo2
DesigyVLS
andC).Ius
unless to
the
voltage shows input
5
 Logic Circuit
Syuemtial
Design 6.7
Suppose, this cross-
o coupled inverter pair is biased at at point C. A small
deviation from this bias point is
regenerated around the
caused by noise. ItIt isis amplified and
circuit loop. As a result, the gain around the loop being
larger than1.

o Now,
A and B are the only stable
operation points, and Cis a metastable
operating point. Metastable means every deviation (even the smallest one)
pUSes the operation point to run away from its original point.
The croSs COupling of two inverters results in a bistable circuit that is a circuit
with two stable states, each corresponding to a logic state. The circuit serves as
a memory which helps to store either a l (or) a 0.
438. High Speed Adders
43.8.1. Carry-select adder
The carry is calculated in cach n-bit
group and then sum is calculated within the
BOup based on input carry in both
carry-skip and carry-look ahead adders.
 carry-in possible
multiplexer 4.20
Cout
of
The The
The n-bit
figure critical asinputs.speed
adders
0°
B16:13
A16:13
selects of
4.31 path and
Sn6:13 Then the
is
Iselect
shows delay the the used critical
-o appropriate other a
C12 multiplexer
in
the is
pgt given adder each path
g. carry +
1. [(n by
calculates is
A12:
B1299 select sugroup-one
m accelerated
is
S12:9
+ used
y 1 (*-2)] triggered
0 adder.
t the adder to
select by
Ao sums
by precomputing
er max + thecalculates
assuming between
actual
Ag;s
Sg:5 1
Bg:5
carry. the the
0 Ba:s a two the
carry-in
assumingsumsa outputs
As:Bt
1 outputs.
Design
VLSI
S41 as
B41 for
'1'.
The pair Aboil