Explicit Layout Pattern Density Controlling
based on Transistor-array-style
Chao Geng, Bo Liu, and Shigetoshi Nakatake
The University of Kitakyushu, Fukuoka 808-0135, Japan
Email: naka-lab@is.env.kitakyu-u.ac.jp
Abstract—An aggressive controlling for layout pattern density
is becoming essential for the manufacturability of advanced
processes. Focusing on analog layout under severe density con-
straints, this paper provides a novel idea that layout generation
and verification are co-working on a density-aware format.
Our idea follows a transistor-array(TA)-style of analog layout
where unit-transistors of the same channel-size are used to form
an array. In this style, we can explicitly control the layout
pattern density by changing array pitch, stretching poly gates or
widening diffusion of unit-transistors. We present a framework
to enumerate feasible design parameters satisfying density and
DRC constraints. In a design case of an OPAMP layout in a
65nm process, we demonstrate that our framework can converge
the design in much fewer iterations compared with a traditional
style layout by manual drawing.
Index Terms—analog layout, density constraint, transistor-
array
I. I NTRODUCTION
In manufacturing integrated circuits on advanced processes,
CMP (Chemical Mechanical Polishing) is a predominant tech-
nique to control the planeness. However, significant surface-
topography variation still exists, which affects depth of fo-
cus in lithography and in return affects the performance
of circuits[1]. To avoid the variation in interlayer-dielectric
thickness, we need to pay attention to the fabrication-process
uniformity and predictability, the layout must be uniform with
respect to a certain density criteria[2].
A reasonable solution for repairing density variation is to
use techniques like fill insertion, inserting dummy fills into
the sparse regions to make the pattern density even. A lot
of design automation papers have been published to deal
with the fill insertion in the past decades. In ICCAD2014, a
technical contest[3] had reported a variety of effective automa-
tion algorithms for the fill insertion. Most of papers consider
speed-up of dummy fill insertion procedure, optimizing the
amount of fills and placement structure based on some efficient
algorithms[4], [5]. In addition, several papers mainly take
the parasitic effects such as capacitance coupling and signal
mismatch into account for making the optimization more
reasonable [6], [7].
With respect to analog layout, especially, dummy fill inser-
tion closes to the signal lines and devices, bringing unexpected
parasitics that significantly affect the electrical behavior of
circuit. Also, for passing the density checking, tuning the
position and dimension of device layers such as diffusion,
poly, metal, and contact, directly results in overmany iterations
978-1-5090-6389-5/17/$31.00 ©2017 IEEE 1557
of layout redrawing and verification. Hence, the dummy fill
insertion for analog layouts severely influence the yield and
the time-to-market.
On the other hand, a transistor-array(TA)-style is proposed
for analog layout to suppress process-induced variability [8],
where a large-channel transistor is divided into a set of
regular grid-based unit-transistors connected in parallel or
serial. The works related to TA-style demonstrate the circuit
performance is not deteriorated even when introducing unit-
transistor decomposition [9], [10], [11].
Based on TA-style, unlike the fill insertion, we introduce an
explicit controlling of the layout pattern density by changing
the array pitch, stretching the poly gates or widening the
diffusion of unit-transistors. The contributions of this paper
are summarized as follows;
1) We provide a density-aware format for synchronizing
layout generation and verification. In the format, TA-
style is not only consistent with a density checking pro-
cedure, but also precisely estimates the process variation,
so that it guarantees the performance of the circuit.
2) We propose a framework to enumerate feasible layout
parameters which satisfy multi-layer density constraints
as well as design rules. As a result, it significantly
reduces the iterations of redrawing and verification of
analog layout.
3) We demonstrate an example of CMOS OPAMP layout
in a 65nm process for the effectiveness and applicability
of our framework.
The rest of paper is organized as follows. Section II briefly
introduces transistor-array-style for analog layout. Section III
formulates density and DRC constraints used in this paper.
Section IV is devoted to describing our framework for control-
ling the layout density and demonstrating a design example,
and Section V concludes this work.
II. T RANSISTOR - ARRAY
In MOS analog layout, [8] addresses the layout-dependent
variability based on the measurement results of test chips in a
90nm process. When increasing the channel size, i.e., L × W ,
the variation decreases. However, for two transistors with the
same channel length and width, if they have different layout
structures, the difference of Vth might be bigger than that of
the transistors with the same structure. This result reveals that
the transistors with unified channel length and channel width
can alleviate the layout-dependent variation as expected.
 wdiff st
sl
wu hpoly sy
sx
lu
wtile
(a) MOS transistor htile
htile tile
wtile
window
(b) tile (c) transistor-array: ncol x nrow
Fig. 1. A density-aware layout format of TA-style: (a) Design parameters of
an unit MOS transistor; (b) Checking window partition; (c) Design parameters
of the transistor array.
[8] proposes transistor-array(TA)-style for analog layouts. In
TA-style, a large transistor is decomposed into a set of unified
sub-transistors, which are connected in series or parallel. Since
the transistor decomposition in the channel length direction
does not introduce a significant error, all the sub-transistors are
then able to be arranged on a uniform grid like a array, thereby
obtaining a well structured layout. With such an array-based
structure, a better post CMP profile is expected to be achieved
as well. The works introduced in [8], [10], [11] clarify that,
analyzing the DC/AC measurement results from the test chip,
the channel decomposition of the MOS transistor, as well as
TA-style layout are applicable to analog designs if it is not so
high-end.
III. D ENSITY C ONSTRAINT AND C HECKING
Layout pattern density in design rules is defined as a ratio
of the sum of area for a layout layer divided by area of a
pre-defined box, called checking window. A checking window
moves along x-axis with a step denoted by xstep , when it
reaches the right-side of the layout area, it returns to the initial
position, and moves upward with the same step size (ystep ),
the window moving goes until sweeping over the whole layout.
The density is calculated at each step of the checking window,
and the checking at every step must be satisfied with the
density constraint which is given as a pre-specified range of
the density.
In general, the calculation of the density becomes more
complicated when including the density effects from multiple
layers. As the number and complexity of density checking
increasing, both the window size and the step size get smaller.
In 65nm process used in this work, the width and height
of checking windows are denoted by wwin and hwin , respec-
tively. The step sizes, xstep and ystep , are 1/2 of wwin and
hwin , respectively.
A. Density-aware Layout Format
In this paper we provide a layout format based on TA-
style which is composed of parameters of density checking,
transistor-array, and design rule. Fig. 1 illustrates a layout
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format example. As seen in the figure (a), a unit-transistor
of TA-style has a unified channel length and width denoted
by lu and wu , respectively, and they are user-defined values.
hpoly and wdif f are height of poly gate and width of diffusion
of a unit-transistor, respectively. These are tunable parameters
to satisfy a given density constraint.
In this paper, a checking window is divided into four square
tiles according to its moving step, and the width and height of a
tile are denoted by wtile and htile , respectively (See the figure
(b)). Note that xstep and ystep may be 1/3 or 1/4 of window
size in other processes, therefore the window can be divided
into 9 or 16 squares so as to apply to various processes. We
define a format of TA-style layout corresponding to one tile as
shown in the figure (c). Since we limit the layout structure is
TA-style, we can arrange tiles of the same structure to cover
the given layout area (wlayout × hlayout ). The size of TA to
a tile is nrow × ncol which is a parameter to pass the design
checking while the size of window is prescribed by foundry.
Note that unit-transistors unused in circuit are regarded as
dummies, which has no impact on the electrical characteristics
of the circuit.
Unit-transistors are placed by spaces sx and sy along x- and
y-direction, respectively. The spaces are tunable parameters to
satisfy a given density constraint. A tile has a boundary and a
space from the left boundary to the left edge of the diffusion
layer of the unit-transistor is sl . Similarly, a space from the
top boundary of a tile to poly layer is st .
Furthermore, a typical set of design rules prescribed by
foundry must be considered. Such as the minimum values
of channel length, channel width, diffusion, and poly gate of
a transistor. Plus, the minimum area of diffusion and poly,
the minimum spaces corresponding to sx , sy , st and sl are
also given. As for the density constraint, the minimum and
maximum values for each layer are prescribed, respectively.
dmin (k) and dmax (k) denote the minimum and maximum
density of layer k.
B. Density Constraint
Given a tile of nrow × ncol TA, the density is calculated as
a ratio of the total polygon area for a specified layer divided
by the area of the tile.
Density constraints for diffusion layer (=dif f ) and poly
layer are as;
dmin (dif f ) ≤ d(dif f ) ≤ dmax (dif f ), (1)
dmin (poly) ≤ d(poly) ≤ dmax (poly) (2)
where
wdif f · wu · nrow · ncol
d(dif f ) = , (3)
wtile · htile
hpoly · lu · nrow · ncol
d(poly) = (4)
wtile · htile
Their geometric relations in tile are as;
htile = 2 · st + hpoly · nrow + sy · (nrow − 1), (5)
wtile = 2 · sl + wdif f · ncol + sx · (ncol − 1) (6)
 Partition for Circuit Elements
Floorplanner
A B E A, B
C D
F G H F, G, H
Device Generation Grid Based
Common-centroid Placement Equilong/Symmetry Routing
A B B A E E
Router
Placer
D C D C E E
C D C D E E
F G H H H
G F H H H
Fig. 2. Design flow based on the TA layout synthesis.
For the simplicity, we describe the density constraint and
geometric relation only for diffusion and poly layers, but
contact and metal layers must be considered as well.
IV. G ENERATION A LGORITHM AND D ESIGN C ASE
This paper provides a TA-style layout generation according
to the density-aware layout format. The procedures of our
approach are organized as follows. Firstly, it decomposes a
full-transistor circuit into a TA-style circuit, from which the
dimension and the number of unit transistors can be obtained.
Secondly, it configures a solution space of feasible design
parameters satisfying design rules and density rules. The
unit transistor dimension, checking window size and density
constraints as known conditions, are used to obtain design
parameters. Thirdly, we choose the best parameters aiming
at optimization objective. In the optimization, for example,
we can consider “centering choice” for high yield of the
mass production and “Min-dummies” for saving layout area.
Fourthly, once we obtain the design parameters, according
to its mapping relations with transistor array in tile, we can
synthesize a layout and map the given circuit onto it, as shown
in Fig. 2.
A. Extraction of Feasible Design Parameters
In the following, we describe the procedures to extract
feasible design parameters based on the density-aware layout
format. As shown in the Algorithm 1, the procedures from
step(2) to step(7) configure feasible range of design parameters
satisfying design rules and density constraints for specified
layers. At step(8), we describe the best solution, but in fact,
we need a criteria. One is “as-less-as-possible” of dummy
transistors, which saves the layout area. Another is “centering”
for the yield, which is to choose center values within the
feasible ranges and contributes to improve the yield of the
mass production.
Once a TA-style layout for a tile is obtained by our
generation algorithm, we copy tile and place the copied tiles
to cover the given layout area. Since TA in tile can meet
the DRC and density constraints, any region of layout pattern
surrounded by checking window can also meet them. Then, the
given circuit, which is decomposed into a set of unit-transistors
Floorplanner Algorithm 1 O(n2 ) Density-aware layout generation.
Input: wlayout , hlayout , lu , wu , wtile , htile , dmin(k) and
E dmax(k) for each layer k;
C, D
Output: (nrow , ncol ), hpoly , wdif f , sx , sy , sl , st ;
1: Set user-defined parameters such as lu , wu , wtile , and
htile .;
2: Let feasible ranges of output variables be (Nrow , Ncol )∗ ,
∗ ∗ ∗ ∗ ∗ ∗
Hpoly , Wdif f , Sx , Sy , Sl , and St , respectively. Initially,
all feasible ranges are set to be large enough.;
3: Place a tile at (0, 0). Let the upper-right corner of the tile
be (x, y), that is, (x, y) ← (wtile , htile );
4: While(y ≤ hlayout ) repeat step(5)-(7), otherwise proce-
dure stops;
5: While(x ≤ wlayout ) repeat step(6)-(7), otherwise x ← 0,
y ← y + htile , and then return to step(4);
6: For each layer k, find a feasible range of each output
variable under density constraints and DRC constraints.
(k)
Let the ranges for a layer k be (Nrow , Ncol )(k) , Hpoly ,
(k) (k) (k) (k) (k)
Wdif f , Sx , Sy , Sl , and St , respectively;
7: Update the feasible ranges. (Nrow , Ncol )∗ ←
(k)
(Nrow , Ncol )∗ ∩ (Nrow , Ncol )(k) , Hpoly ∗ ∗
← Hpoly ∩ Hpoly ,
∗ ∗ (k) ∗ (k)
Wdif f ← Wdif f ∩ Wdif f , Sx ← Sx∗ ∩ Sx ,
(k) (k) (k)
Sy∗ ← Sy∗ ∩ Sy , Sl∗ ← Sl∗ ∩ Sl , and St∗ ← St∗ ∩ St .
∗ ∗
8: output the best solution from (Nrow , Ncol ) , Hpoly ,
∗ ∗ ∗ ∗ ∗
Wdif f , Sx , Sy , Sl , and St ;
in parallel or serial connection, is assigned to the tiles. Note
that we need to choose another feasible design parameters if
the numbers of rows and columns are not sufficient. Plus, if
we have many redundant unit-transistors after the assignment,
they are regarded as dummies.
B. An Example of Feasible Design Parameters
In this paper, targeting a certain 65nm process, we demon-
strate an example how to extract ranges of feasible design
parameters. Based on the our experience to realize an analog
block by TA-style, we set an unit-transistor dimension as,
lu = 2μm, wu = 1μm. The size of a tile is specified as,
wtile = 25μm and htile = 25μm. Hereinafter, we omit the
unit μm from the numerical values.
The given design rules are translated as the following
constraints. 2·lu ≥ wdif f −lu ≥ 0.32, 2·wu ≥ ·hpoly −wu ≥
0.32, sx ≥ 0.14, sy ≥ 0.14, sl ≥ 0.14, st ≥ 0.32.
In addition, taking Eq. (3), (4), (5) and (6) into account,
we calculate the range of feasible design parameters. Table I
shows an example of the calculation of the range. We cannot
describe the real parameters related to density constraints
due to the non-disclosure agreement with the foundry. In
this example, we make the table by extracting the parameter
ranges for diffusion, poly, metal and contact layers. Their
density values are automatically calculated and displayed, in
order to indicate designer to control layout pattern density. A
mathematical method serves the efficient way to configure the
table, but we omit it here for the space.
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 TABLE I and by our TA-style generation, both layouts can pass LVS
F EASIBLE DESIGN PARAMETERS . verification. The TA-layout densities are nearly consistent with
(nrow , ncol ) wdif f hpoly sx sy sl st predicted density. However, densities for manual design are
(8, 10) ··· ··· ··· ··· ··· ··· unknown before verification. Compared with layout (a) with
(8, 11) ··· ··· ··· ··· ··· ··· inserting dummy fills in empty spaces, the density of each
··· ··· ··· ··· ··· ··· ···
··· ··· ··· ··· ··· ··· ··· layer of layout (b) is better. The sizes of layout (a) and
(12, 8) 2.56 1.60 0.30 0.35 1.22 0.98 (b) are almost same. Obviously, the number of iterations of
(12, 8) 2.49 1.49 0.28 0.34 1.53 1.66 verification by TA layout is much smaller than that by hand.
(12, 8) 2.38 1.85 0.79 0.14 0.22 0.64
··· ··· ··· ··· ··· ··· ··· The layout design includes routing, and all the iterations by
(16, 8) ··· ··· ··· ··· ··· ··· TA layout are for routing. As well, our design time is further
(16, 9) ··· ··· ··· ··· ··· ··· shorter than the manual design. Note that most of design time
is spent for the verification and the correction, so less iteration
is efficiently saving the time.
V. C ONCLUSION
Focusing on the density issue in analog layout, we provide a
density-aware layout format of TA-style, and present an novel
method for synchronizing the layout generation and verifica-
tion. Besides, the solution space constructed by feasible design
parameters contributes to design flexibility, in which tunable
design parameters explicitly control layout pattern density.
In a design case of an OPAMP layout in a 65nm process,
we demonstrate the high efficiency and applicability of the
algorithm compared with the custom design. In future works,
we will develop a generation algorithm for an complicated
analog circuit mixed with resistor arrays and capacitor arrays,
pushing the algorithm forward from “cell level” to “chip
Fig. 3. OPAMP layout: (a) manual design; (b) TA layout by our algorithm.
level”.
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