1. a) Draw the block diagram of 8259 and explain each block.

Ans:

Block Diagram of 8259 Programmable Interrupt Controller

Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade Buffer
Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.
1. Data bus buffer – This Block is used as a mediator between 8259 and 8085/8086
microprocessor by acting as a buffer. It takes the control word from the 8085 (let say)
microprocessor and transfers it to the control logic of 8259 microprocessor. After selection
of Interrupt by 8259 microprocessor (based on priority of the interrupt), it transfer the
opcode of the selected Interrupt and address of the Interrupt service sub routine to the other
connected microprocessor. The data bus buffer consists of 8 bits represented as D0-D7 in
the block diagram. Thus, shows that a maximum of 8 bits data can be transferred at a time.
2. Read/Write logic – This block works only when the value of pin CS is low (as this pin is
active low). This block is responsible for the flow of data depending upon the inputs of RD
and WR. These two pins are active low pins used for read and write operations.
3. Control logic – It is the center of the PIC and controls the functioning of every block. It
has pin INTR which is connected with other microprocessor for taking interrupt request
and pin INT for giving the output. If 8259 is enabled, and the other microprocessor
Interrupt flag is high then this causes the value of the output INT pin high and in this way
8259 responds to the request made by other microprocessor.
4. Interrupt request register (IRR) – It stores all the interrupt level which are requesting for
Interrupt services.
5. Interrupt service register (ISR) – It stores the interrupt level which are currently being
executed.
6. Interrupt mask register (IMR) – It stores the interrupt level which have to be masked by
storing the masking bits of the interrupt level.
7. Priority resolver – It examines all the three registers and set the priority of interrupts and
according to the priority of the interrupts, interrupt with highest priority is set in ISR
register. Also, it reset the interrupt level which is already been serviced in IRR.
8. Cascade buffer – To increase the Interrupt handling capability, we can further cascade
more number of pins by using cascade buffer. So, during increment of interrupt capability,
CSA lines are used to control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else in
slave mode. In Non Buffered mode, SP/EN pin is used to specify whether 8259 work as master
or slave and in Buffered mode, SP/EN pin is used as an output to enable data bus.

b) Illustrate with an example, to interface an D/A converter with 8086 microprocessor

Ans:

Interfacing Digital to Analog Converters (DAC)

• The DAC converts binary numbers into their equivalent analog voltages.

• The DAC finds applications in areas like digitally controlled gain, motor speed controls,
programmable gain amplifiers, etc.
• The DAC 0800 is a monolithic 8-bit DAC manufactured by National semiconductor

• It has settling time around 100ms and can operate on a range of power supply voltages,
i.e. from 4.5 v to +18 v. Usually V+ is 5v or +12 v

• The V– pin can be kept at a minimum of -12V

• Write an ALP to generate a triangular wave of frequency 500 Hz using the interfacing
circuit shown below. The 8086 system operates at 8MHz. The amplitude of the triangular
wave is +5V ,

• The Vref+ should be tied to +5v to generate a wave of +5V amplitude

• The required frequency of the output is 500Hz. i.e the period is 2 ms

• Assuming the wave to be generated symmetric, the waveform will rise for 1 ms and fall
for 1 ms. This will be repeated continuously.
2. a) Explain in detail about the DMA controller with a neat diagram.
Ans:
Key Features:
3. 24-bit length address register
4. 16-bit length count register
5. 4 independent DMA channels
6. 4 clock / 1 bus cycle
7. Byte transfer / word transfer selectable
8. Supports three transfer modes (Single, Demand, Block)
9. DMA request Maskable on an individual channel basis
10. Software DMA request in uPD1037 mode
11. Auto initialization function
12. Two kinds of channel priority order (Fixed & Rotating)
13. Cascading capability
8237 Internal Registers
CAR
 The current address register holds a 16-bit memory address used for the DMA transfer.
 Each channel has its own current address register for this purpose
 When a byte of data is transferred during a DMA operation, CAR is either incremented
or decremented. depending on how it is programmed
CWCR
 The current word count register programs a channel for the number of bytes to transferred
during a DMA action.
CR
 The command register programs the operation of the 8237 DMA controller.
 The register uses bit position 0 to select the memory-to-memory DMA transfer mode.
1. Memory-to-memory DMA transfers use DMA channel
2. DMA channel 0 to hold the source address
3. DMA channel 1 holds the destination address
BA and BWC
 The base address (BA) and base word count (BWC) registers are used when auto-
initialization is selected for a channel.
 In auto-initialization mode, these registers are used to reload the CAR and CWCR after
the DMA action is completed.
MR
 The mode register programs the mode of operation for a channel.
 Each channel has its own mode register as selected by bit positions 1 and 0.
1. Remaining bits of the mode register select operation, auto-initialization,
increment/decrement, and mode for the channel

BR
 The bus request register is used to request a DMA transfer via software.
1. very useful in memory-to-memory transfers, where an external signal is not
available to begin the DMA transfer
MRSR
 The mask register set/reset sets or clears the channel mask.
1. If the mask is set, the channel is disabled
2. The RESET signal sets all channel masks to disable them

MSR
 The mask register clears or sets all of the masks with one command instead of individual
channels, as with the MRSR.

SR
 The status register shows status of each DMA channel. The TC bits indicate if the
channel has reached its terminal count (transferred all its bytes).
  When the terminal count is reached, the DMA transfer is terminated for most modes
of operation.
 The request bits indicate whether the DREQ input for a given channel is active.

8237 Software Commands

Master clear
Acts exactly the same as the RESET signal to the 8237. As with the RESET signal, this
command disables all channels
Clear mask register
Enables all four DMA channels.
Clear the first/last flip-flop
Clears the first/last (F/L) flip-flop within 8237. The F/L flip-flop selects which byte (low
or high order) is read/written in the current address and current count registers. if F/L = 0,
the low-order byte is selected if F/L = 1, the high-order byte is selected Any read or write
to the address or count register automatically toggles the F/L flip-flop.

b) Draw a typical stepper motor interface with 8255 and explain its functioning.

Ans:

Stepper motor interface

• A stepper motor is a device used to obtain an accurate position control of rotating shafts

• It employs rotation of its shaft in terms of steps rather than continuous rotation as in case
of AC or DC motors
 • To rotate the shaft of the stepper motor, a sequence of pulses is applied to the windings
of the stepper motor in a proper sequence

• The number of pulses required for one complete rotation of the shaft of the stepper motor
is equal to its number of internal teeth on the rotor

• The stator teeth and the rotor teeth lock with each other to fix a position of the shaft.

• With a pulse applied to the winding input, the rotor rotates by one tooth position or an
angle x

• X=3600/no. of rotor teeth

• After the rotation of the shaft through angle x, the rotor locks itself with the next tooth in
the sequence on the internal surface of stator

• Fig below shows the internal schematic of a four winding stepper motor. Stepper motors
have been designed to work with digital circuits. Binary level pulses of 0-5v are required
at its winding inputs to obtain the rotation of shafts

The sequence of pulses can be decided, depending upon the required motion of the shaft

Winding arrangement of a stepper motor

 A Stepper motor Rotor

Interfacing stepper winding Wa

• The circuit for interfacing Wn with an I/O port is shown in the fig. Each of the windings
of a stepper motor need this circuit for its interfacing with the output port

• A typical stepper motor may have parameters like torque 3kg-cm, operating voltage 12
V, current rating 0.2 A and a step angle 1.8 0, i.e., 200 steps/revolution (number of rotor
teeth)

• A simple scheme for rotating the shaft of a stepper motor is called a wave scheme

• In this scheme, windings Wa, Wb, Wc, and Wd are applied with the required voltage
pulses, in a cyclic fashion.
• By reversing the sequence of excitation, the direction of rotation of the stepper motor
shaft may be reversed. Table below shows the excitation sequences for clockwise and
anticlockwise rotations.
3. a) Explain the BSR mode of operation of 8255 programmable peripheral interface.

Bit Set Reset (BSR) Mode

This mode is used to set or reset the bits of the Port-C only. For BSR mode always D7 will be 0.
The control register is looking like this:

 
The (D3, D2, D1) will be 000 to 111. In this mode it affects only one bit of Port C at a time.
When user set the bit, it remains set until user unset it. The user needs to load the bit pattern in
control register to change the bit.
 Input/ Output Mode
This mode is selected when the D7 bit of the control register is 1.
This mode has also three different modes. These modes are Mode 0 and Mode 1 and Mode 3.

Mode 0 – Simple or basic I/O Mode

In this mode all of the ports A, B and C can be used as input or output mode. The outputs are
latched, but inputs are not latched. This mode has interrupted handling capability.
Mode 1 – Handshake or Strobed I/O
In this mode the Port A and Port B can be used as input or output ports, the port C are used for
handshaking. In this mode the inputs and outputs are latched. This mode also has the interrupt
handling capability, and signal control to match the speed of CPU and IO devices.
Mode 3 – Bidirectional I/O
In this mode only Port A can work, and port B can either be in mode 0 or mode 1, and the port C
are used for handshaking. In this mode the inputs and outputs are latched. The control register is
looking like below in this mode:

 
 Bits Function

D7 1 for IO mode and 0 for BSR mode

D6 & These are used to set port A mode. for 00, it is m0 mode, for 01, it is m2 mode and 10 or
D5 11, it is m2 mode.

D4 1 when port A is taking input, 0 when port A is sending output.

D3 1 when higher nibble of port C is taking input, and 0 when higher nibble is sending
output.

D2 It tells the mode of Port B. For 0, it is m0 mode, and for 1, it is m1 mode.

D1 1 when port B is taking input, 0 when port B is sending output.

D0 1 when lower nibble of port C is taking input and 0 when lower nibble is sending output.

b) Write an assembly language program in 8086 to generate a symmetrical square wave

with 1 KHz frequency?

Ans:

Assume selected counter is Counter-1, Mode for Square wave is Mode-3, Address for Counter 1
is 82H
4. a) Interfacing of a two 4X4 PROM and two 8X4 RAM with 8086 CPU, draw the memory
map and interfacing diagram for it, the RAM address follows the ROM address.

Solution:
 The address of the RAM may be selected anywhere in the 1 MB address space of 8086,
but to make the address space continuous we would follow the given procedure.
 After reset the IP and CS are initialized to for address FFFF0H.
 We must first calculate the total number of address lines required for 8K bytes of
EPROM which is 13, as we have seen earlier that we have N2n hence we get 213= 8K
Decoded Map
 Address lines A13-A19 are used for decoding to generate the chip select.
 The BHE signal goes low when a transfer is at odd address or higher byte of data is to be
accessed.

 The memory system here contains in total four 4K X 8 memory chips.

 The two 4K X 8 chips of RAM and ROM are arranged in parallel to obtain 16-bit data
bus width. If A0 is 0 i.e. the address is even and is in RAM, then the lower RAM chip is
selected indicating 8-bit transfer at an even address
 If A0 is 1, i.e. the address is odd and is in RAM the BHE goes low, the upper RAM chip
is selected, further indicating that the 8-bit transfer is at an odd address.
 If the selected addresses are in ROM, the respective ROM chips are selected.
 If at a time A0 and BHE both are 0, both the RM or ROM chips are selected i.e. the data
transfer is of 16-bits.
 b) Explain the Interfacing of seven segment displays along with 8255 PPI

ALP program is shown below

5. a) Interface an 8255 with 8086 to work as a peripheral interface. Initialize its port A as
output port, port B as input port and port C as output port. Port A address should be
0740H.Writ a program to sense switch positions SW0 –SW7 connected at port B. The
sensed pattern is to be displayed in port A, to which 8 LEDs are connected, which the port
C lower displays number of ‘ON’ switches out of the total eight switches. (or Explain the
interface of LCD with 8086.)
 The 8255 is to be interfaced with lower order data bus; i.e. D0-D7.

 The A0 and A1 pins of 8255 are connected to A1 and A2 pins of the microprocessor
respectively. We will use absolute decoding scheme that uses all the 16 address lines.

 For deriving the device address pulse. Out of A0– A15 lines, two address lines A2 and
A1 are directly required by 8255 for three port and CWR address decoding. Hence only
A3 to A15 are used for decoding addresses.

 Circuit diagram, the 8086 is assumed to be in the maximum mode so that IORD and I
OWR are readily available.
 b) What is DMA? What are its advantages?

Ans:

 DMA controller definition is, an external device that is used to control the data transfer
between memory and I/O device without the processor involvement is known DMA
controller.
 This controller has the capacity to access the memory directly to read or write operations.
 DMA controller was implemented by Intel for having very fast data transfer with less
utilization of the processor.
 The direct memory access controller produces memory addresses and it covers numerous
hardware registers that can be read & written through the CPU.
 These registers mainly include a byte count, memory address & minimum of one or
above control registers.
 So based on the DMA controller features, these registers can select some combination of
source, destination, transfer direction, the transfer unit size & the number of bytes to
move within the single burst.

The advantages of the DMA controller include the following,

 It allows a peripheral device to read or write from memory without using the CPU.
 DMA controller increases the operations of the memory by avoiding CPU involvement.
 It reduces the overload work on the CPU.
 For every transfer, simply a few clock cycles are necessary.
 DMA decreases the required clock cycle to read/write a block of data.
 The disadvantages of the DMA controller include the following.
 DMA controller-based systems are expensive.
 Cache coherence troubles can occur while using DMA for transferring data.
 System price can be increased.

6. a) Discuss the applications of A-to-D and D-to-A converters.

The applications of ADC include the following.
 At present, the usage of digital devices is increasing. These devices work based on the digital
signal. An analog to digital converter plays a key role in such kind of devices to convert the
signal from analog to digital. The applications of analog to digital converters are limitless
which are discussed below.
 AC (air conditioner) includes temperature sensors to maintain the temperature within the
room. So this conversion of temperature can be done from analog to digital with the help of
ADC.
 It is also used in a digital oscilloscope to convert the signal from analog to digital to display.
 ADC is used to convert the analog voice signal to digital in mobile phones because mobile
phones use digital voice signals but actually, the voice signal is in the form of analog. So
ADC is used to convert the signal before sending the signal toward the transmitter of the cell
phone.
 ADC is used in medical devices like MRI and X-Ray to convert the images from analog to
digital before alteration.
 The camera in the mobile mainly used for capturing images as well as videos. These are
stored in the digital device, so these are converted to digital form using ADC.
 The cassette music can also be changed into a digital like CDS & thumb drives use ADC.
 At present ADC is used in every device because almost all devices available in the market are
in digital version. So these devices use ADC.

Applications of Digital to Analog Converter

DACs are used in many digital signal processing applications and many more applications. Some
of the important applications are discussed below.
Audio Amplifier
DACs are used to produce DC voltage gain with Microcontroller commands. Often, the DAC
will be incorporated into an entire audio codec which includes signal processing features.
Video Encoder
The video encoder system will process a video signal and send digital signals to a variety of
DACs to produce analog video signals of various formats, along with optimizing of output
levels. As with audio codecs, these ICs may have integrated DACs.
Display Electronics
The graphic controller will typically use a lookup table to generate data signals sent to a video
DAC for analog outputs such as Red, Green, Blue (RGB) signals to drive a display.
Data Acquisition Systems
Data to be measured is digitized by an Analog-to-Digital Converter (ADC) and then sent to a
processor. The data acquisition will also include a process control end, in which the processor
sends feedback data to a DAC for converting to analog signals.
Calibration
The DAC provides dynamic calibration for gain and voltage offset for accuracy in test and
measurement systems.
Motor Control
Many motor controls require voltage control signals, and a DAC is ideal for this application
which may be driven by a processor or controller.

Motor
Control Application
Data Distribution System
Many industrial and factory lines require multiple programmable voltage sources, and this can be
generated by a bank of DACs that are multiplexed. The use of a DAC allows the dynamic change
of voltages during operation of a system.
Digital Potentiometer
Almost all digital potentiometers are based on the string DAC architecture. With some
reorganization of the resistor/switch array, and the addition of an I2C compatible interface, a
fully digital potentiometer can be implemented.
Software Radio
A DAC is used with a Digital Signal Processor (DSP) to convert a signal into analog for
transmission in the mixer circuit, and then to the radio’s power amplifier and transmitter.
 b)  Write a program to make the stepper motor to rotate both clockwise and counter
clock wise direction. 

Assembly Code

For anticlockwise direction

7. a) Explain ADC 0809 with neat sketch and explain how can ADC 0809 interfaced with
8086?

Analog to Digital Converter (ADC)

• The ADC is an input device to microprocessor that sends an initializing signal to the
ADC to start the analog signal to digital conversion process. The start of conversion
signal is a pulse of a specific duration

• The process of analog to digital conversion is a slow process and the processor has to
wait for the digital data till the conversion is over.
• After the conversion, the ADC sends the End of Conversion (EoC) signal to inform the
processor about it and the result is ready at the output buffer of the ADC. The tasks of
issuing SOC pulse to ADC, reading EOC signal from the ADC and reading the digital
output of the ADC are carried out by the CPU using 8255 I/O ports

• The time taken by the ADC to calculate the equivalent digital data output from the
moment of the start of conversion is called conversion delay of the ADC

• It may range anywhere from a few microseconds, in case of fast ADCs, to even a few
hundred milliseconds in case of slow ADCs.

• Selection of ADC depends on the speed, resolution, cost etc

• The ADCs available in the market use different conversion techniques for the conversion.

• Successive approximation and dual slope integration techniques are the most popular
techniques used in the integrated ADC chips

• Irrespective of the techniques used for conversion, general algorithm for ADC
interfacing contains the following steps

1. Ensure the stability of analog input, applied to the ADC.

2. Issue Start of Conversion (SOC) pulse to ADC

3. Read End of Conversion (EOC) signal to mark the end of conversion process

4. Read digital data output of the ADC as equivalent digital output.

 The ADC chips 0808 and 0809 are 8-bit CMOS, successive approximation converters.
 Successive approximation technique is of the fastest technique used for the process of
analog to digital conversion.
 The conversion delay is 100μs at a clock frequency of 640 KHz, which is quite low as
compared to other converters.
 These converters internally have a 3:8 analog multiplexer so that at a time eight different
analog inputs can be connected to the chips.
 Out of these eight inputs only one can be selected for conversion by using address lines A,
B C..
Block Diagram of ADC 0808/0809
 b) Bring out the differences between static and dynamic RAM. Describe the procedure of
interfacing static memories with a CPU.

The general procedure of static memory interfacing with 8086 as follows:

 Arrange the available memory chips so as to obtain 16-bit data bus width.
 The upper 8-bit bank is called ‘odd address memory bank’ and the lower 8-bit bank is
called ‘even address memory bank’
  Connect available memory address lines of memory chips with those of the
microprocessor and also connect the memory RD and WR inputs to the corresponding
processor control signals. Connect the 16-bit data bus of the memory bank with that of
the microprocessor 8086.
 The remaining address lines of the microprocessor, BHE and A o are used for decoding
the required chip select signals for the odd and even memory banks.
 The CS of memory is derived from the output of the decoding circuit.
 As a good and efficient interfacing practice, the address map of the system should be
continuous as far as possible.

8. a) Explain the interfacing of 8255 to 8086 in memory mapped I/O mode.

Interfacing 8255 In Memory Mapped I/O:

Fig. 14.18 shows the interfacing of 8255 with 8085 in memory mapped I/C technique. Here RD
and WR signals are activated when 10/M signal is low, indicating memory bus cycle. To get
absolute address, all remaining address lines (A15 – A2) are used to decode the address for 8255.
Other signal connections are same as in I/C mapped I/O.
 b) Explain the important features of 8251USART.
8251 USART
• 8251 universal synchronous asynchronous receiver transmitter (USART) acts as a
mediator between microprocessor and peripheral to transmit serial data into parallel form
and vice versa.
• It takes data serially from peripheral (outside devices) and converts into parallel data.
• After converting the data into parallel form, it transmits it to the CPU.
• Similarly, it receives parallel data from microprocessor and converts it into serial form.
• After converting data into serial form, it transmits it to outside device (peripheral).
Block Diagram of 8251 USART –
Data bus buffer –
• This block helps in interfacing the internal data bus of 8251 to the system data bus.
• The data transmission is possible between 8251 and CPU by the data bus buffer block.
Read/Write control logic –
• It is a control block for overall device.
• It controls the overall working by selecting the operation to be done.
• The operation selection depends upon input signals as:

In this way, this unit selects one of the three registers- data buffer register, control register, status
register.
From the following table, we can see how to read or write data word, read the status word and
write control word.

A0 RD WR Task Port Address

0 0 1 Read Data Word 90H

0 1 0 Write Data Word 90H

1 0 1 Read Status 91H

Word

1 1 0 Write Control 91H

Word

Modem control (modulator/demodulator) –

 • A device converts analog signals to digital signals and vice-versa and helps the
computers to communicate over telephone lines or cable wires.
• The following are active-low pins of Modem.
– DSR: Data Set Ready signal is an input signal.
– DTR: Data terminal Ready is an output signal.
– CTS: It is an input signal which controls the data transmit circuit.
– RTS: It is an output signal which is used to set the status RTS.
• Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for
conversion into serial signal and further transmission onto the common channel.
– TXD: It is an output signal, if its value is one, means transmitter will transmit the
data.
Transmit control –
This block is used to control the data transmission with the help of following pins:
– TXRDY: It means transmitter is ready to transmit data character.
– TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
– TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
Receive buffer –
This block acts as a buffer for the received data.
– RXD: An input signal which receives the data.
Receive control –
This block controls the receiving data.
– RXRDY: An input signal indicates that it is ready to receive the data.
– RXC: An active-low input signal which controls the data transmission rate of
received data.
– SYNDET/BD: An input or output terminal. External synchronous mode-input
terminal and asynchronous mode-output terminal.