Paper ID No: 263

IEEE CS BDC Summer Symposium 2023, IEEE Computer Society Bangladesh Chapter, 26-27 May, 2023

Designing a 10-BIT 10.24 M-sample/sec ∆𝚺-ADC in 90 nm

Technology with 10.15 dB SNDR
Richard Victor Biswas
Department of Electrical and Electronics Engineering, Faculty of Engineering,
American International University-Bangladesh, Dhaka, Bangladesh
richard.biswas@aiub.edu

Extended Abstract:
Research Area: Signal Processing
Objectives: Further Optimization of the existing ADC Design, Generation of Layout, Post-Layout Extraction and
Fabrication

Due to high resolution and accuracy, moderate operating frequencies, high efficiency and larger supply headroom,
Delta-Sigma ADC (∆Σ-ADC) is being interfaced extensively with digital signal processing units. In the proposed
ADC running as low as a +/- 600mV power supply, an oversampling ratio of 1024 in the single-order modulator
section and noise filtering techniques in the digital filter (decimator) have been considered. A sample and hold
circuit with a sampling rate of 10.24 MHz, three-stage stable operational amplifiers (as a differential amplifier,
integrator, and comparator) with a Miller compensated capacitor (DC gain = 34.511 dB, Unity Gain Bandwidth
Product = 5.18 MHz, and phase margin = 83.7°), and 10-bit sequential counter as well as summing interval counter
have been simulated in Cadence Virtuoso Analog Design Environment using 90 nm process node. The Signal-to-
Noise-and-Distortion Ratio (SNDR), Spurious Free Dynamic Range (SFDR), and Effective Number of Bits (ENOB)
of our proposed ADC are 10.15 dB, 0.4647 dB, and 1.979, correspondingly.

Fig: Block Diagram and Waveforms (Sine, Ramp, & Modulator O/P) of the proposed 10-bit ∆Σ-ADC

References:
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https://doi.org/10.1007/978-981-13-7091-5_16
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