SACULLES, LHENARD G.
Step 1: (State T₁)
Lecture 2-1_The Instruction Cycle
Machine Cycle
Program Execution
1. Installation from source media (eg. CD-ROM)
2. Program installed onto hard drive
3. Program loaded into memory
4. Program executed by CPU
Saving of Data
1. Results obtained from CPU
2. Data stored in memory
3. Data saved to hard drive
4. Data possibly archived on external media
The instruction cycle is the cycle that the
central processing unit (CPU) follows from boot-up
until the computer has shut down in order to process
instructions.
Three Main Phases
 Fetch
The control unit looks at the program counter
register (PC) to get the memory address of the next
instruction. It then requests this instruction from
main memory and places it in the instruction
register (IR).
 Decode
The control unit checks the instruction that is
now stored within the instruction register (IR). It
looks at the instruction which is just a sequence of
0s and 1s and decides what needs to be done.
 Execute
The control unit sends the signals that tell the
ALU, memory, and other components signals to
cause them to perform the correct work.
MACHINE CYCLE
The time required by the microprocessor to
complete an operation of accessing memory or
input/output devices is called machine cycle. One
time period of frequency of microprocessor is called
t-state. A t-state is measured from the falling edge
of one clock pulse to the falling edge of the next
clock pulse.
Fetch cycle takes four t-states and
execution cycle takes three t-states.
Fetch Cycle in Step-by-Step Manner
In T₁ state, the 8085 places the contents of
program counter on the address bus. The high-order
byte of the PC is placed on the Ag-A15 lines. The
low-order byte of the PC is placed on the AD₁ -
AD, lines which stays on only during T₁. Thus,
microprocessor activates ALE (Address Latch
Enable) which is used to latch the low-order byte of
the address in external latch before it disappears.
In T₁, 8085 also sends status signals IO/M,
S₁, and S. IO/M specifies whether it is a memory or
I/O operation, S₁ status specifies whether it is
read/write operation; S₁ and S together indicates
read, write, opcode fetch, machine cycle operation,
or whether it is in HALT state. In opcode fetch
machine cycle status signals are: 10/M = 0, S₁ = 1,
So = 1.
Step 2: (State T₂)
In T₂, low-order address disappears from the
AD - AD, lines. (However, A - A, remain available
as they were latched during T₁). In T₂, 8085 sends
RD signal low to enable the addressed memory
location. The memory device then places the
contents of addressed memory location on the data
bus (AD - AD₂).
Step 3: (State T3)
During T3, 8085 loads the data from the
data bus in its Instruction Register and raises RD to
high which disables the memory device.
Step 4: (State T4)
In T4, microprocessor decodes the opcode,
and on the basis of the instruction received, it
decides whether to enter state T5 or to enter state T₁
of the next Machine Cycle of 8085 Microprocessor.
One-byte instructions those operate on eight bit data
(8 bit operand) are executed in T4.
Timing Diagram for Opcode Fetch
Machine Cycle 8085
Decode
Decoder interprets the encoded instruction
from instruction register.
The Instruction Decoder is a CPU
component that decodes and interprets the contents
of the Instruction Register, i.e., its splits whole
instruction into fields for the Control Unit to
interpret. The Instruction decoder is often
considered to be a part of the Control Unit.
The primary purpose of this decoder is to
allow a ‘cleaner’ instruction set representation. As
with the direct variant, each instruction still
represents a single machine function, but the use of
a decoder will often significantly reduce the number
of bits needed in the machine code word.
Execute
The fundamental sequence of steps that a
CPU performs. It is the process whereby a single
instruction is executed.
It consists of memory read (MR), memory
write (MW), input output read (IOR) and input
output write (IOW).
SUMMARY OF THE CYCLE
 The processor checks the program counter to see
which instruction to run next.
 The program counter gives an address value in
the memory of where the next instruction is.
 The processor fetches the instruction value from
this memory location.
 Once the instruction has been fetched, it needs
to be decoded and executed. For example, this
could involve taking one value, putting it into
the ALU, then taking a different value from a
register and adding the two together.
 Once this is complete, the processor goes back
to the program counter to find the next
instruction.
 This cycle is repeated until the program ends.

Interrupts
Interrupts are the signals generated by the
external devices to request the microprocessor to
perform a task.
Lecture 2-2_8085 Pin Configuration
8085 pin configuration and functions
Description of 8085 Pins 7 groups and functions
It is an 8-bit microprocessor designed by Intel in 1. Power supply and frequency signals
1977 using NMOS technology. 2. Data bus and address bus
Intel 8085 is fabricated as a 40-pin DIP IC 3. Control bus
stands for ‘dual inline package’ . 4. Interrupt signals
Intel manufactures 8085 in several versions, like 5. Serial I/O signals
8085 A, 8085 AH, 8085 AH-2, and 8085 AH -1. 6. DMA signals
7. Reset signals
Recommended internal clock frequencies

Type Recommended Clock

Frequency
8085A and 8085 AH 3 MHz
8085 AH-2 5 MHz
8085 AH-1 6 MHz

 8085A microprocessor is an 8 bit

microprocessor suitable for a wide of
applications.
 Status Signals
o S0 - It is pin number 29
o S1 – It is pin number 30
o IO/M - It is pin number 34 and indicates the
selection of a memory address or input-output
device. This shows whether the read/write operation
is to be carried out at the memory location or at the
I/O device.
Note: The low signal at this pin shows that operation is
 Power Supply and Frequency Signals performing over memory location. As against, a high
1. Vcc: it requires a single +5 v power supply. signal at this pin represents the operation at I/O.
2. Vss: ground reference.
 Clock signals
3. X1 and X2: a tuned circuit like LC, RC or
crystal is connected at these two pins.
4. CLK OUT: this signal is used as a system
clock for other devices. Its frequency is half
the oscillator frequency.
 Address Bus
- This category contains 8 pins.
- A15-A8, it carries the most significant 8-bits of
memory/IO address.  Interruption Signal
- contains the address of the desired memory Interrupt
location from where the data or instruction is to Interrupt is a mechanism by which an
be fetched. input/output devices can suspense normal execution
 Data Bus of any process. Generally, a particular task is
- This category contains 8 pins. assigned to that interrupt signal.
- AD7-AD0, it carries the least significant 8-bit In the microprocessor-based system the
address and data bus. interrupts are used for data transfer between the
- However, to reduce the number of bus lines peripheral devices and the microprocessor.
these 8-bit data bus lines are multiplexed with
the 8-bit address bus.
Classification of Interrupt
- contains the data or instruction that is needed to
1. Vectored Interrupt
be fetched from the memory.
In this type of interrupt, the interrupt address is
 Control and Status Signals
known to the processor.
These signals are used to identify the nature
of operation Example: RST 7.5, RST 6.5, RST 5.5, TRAP
Control Signals
o Read Control Signal (RD) Interrupt Vector Address
This signal indicates that the selected IO or TRAP (RST 4.5) 24 H
memory device is to be read and is ready for accepting RST 5.5 2C H
data available on the data bus. RST 6.5 34 H
o Write Control Signal (WR)
RST 7.5 3C H
This signal indicates that the data on the data bus
is to be written into a selected memory or IO
location.
2. Non-Vectored Interrupts
o Address Latch Enable (ALE)
It is a positive going pulse generated when a In this type of interrupt, the interrupt address
new operation is started by the microprocessor. is not known to the processor, so the interrupt
When the pulse goes high, it indicates address. address needs to be sent externally by the device
When the pulse goes down it indicates data. to perform interrupts.

Example: INTR
3. Maskable Interrupts
 In this type of interrupt, we can disable or DMA is a process of communication for
ignore the interrupt by writing some instructions data transfer between memory and I/O,
into the program. controlled by an external circuit called DMA
Example: RST 7.5, RST 6.5, RST 5.5 controller w/o the involvement of CPU.
4. Non-maskable Interrupt 8085 MP has two pins HOLD and HLDA
In this type of interrupt, we cannot disable or which are used for DMA Operation.
ignore the interrupt by writing some instructions
into the program. Operation:
Example: TRAP First, DMA Controller sends a request by
making Bus Request (BR) control line high. When
Priority on Interrupts MP receives high level signal to HOLD pin, it first
completes the execution of current machine cycle, it
TRAP takes few clocks and sends HLDA signal to the
Highest
RST 7.5 DMA Controller.
RST 6.5 Second, after receiving HLDA through Bus
RST 5.5 Grant (BG) pin of DMA Controller, the DMA
Lowest
INTR controller takes control over system bus and
transfers data directly between memory and I/O w/o
Execution of Interrupt involvement of CPU. During DMA operation, the
Two types of Interrupts according to Execution processor is free to perform next job w/c does not
o Software Interrupt need system bus.
An interrupt which is generated by software At the end of data transfer, the DMA controller
or instruction. terminates the request by sending low signal to
Examples: RST0, RST1, RST2, RST3, RST4, HOLD pin and MP regains control of system bus by
RST5, RST6, and RST7 making HLDA low.
o Hardware Interrupt
When microprocessors receive interrupt
signals through pins (hardware) of microprocessor.
Examples: TRAP, RST 7.5, RST 6.5, RST 5.5 and
INTA

Interrupt Vector Address

RST 0 00 H
RST 1 08 H
RST 2 10 H
RST 3 18 H
RST 4 20 H
 Reset Signals
RST 5 28 H Reset In:
RST 6 30 H A low in this pin
RST 7 38 H - Sets the program counter to zero (0000H)
- Resets the interrupt enable and HLDA flip-
 Serial I/O Signal flops.
The 8085 Microprocessor has Serial - Tri-states the data bus, address bus and control
Input/Output lines consisting of two pins as bus.
follows: - Affects the contents of processor’s internal
o Serial Output Data (SOD) registers randomly.
SOD line is used to SEND data serially. ----------------------------------------------------------
o Serial Input Data (SID) On reset, the PC sets to 000H which causes
SID line is used to RECEIVE data serially. 8085 to execute the first instruction from address
0000H. For proper reset operation, reset signal must
be held low for at least 3 clock cycles. The power-
on reset circuit can be used to ensure execution of
first instruction from address 0000H.
Reset Out:
This active high signal indicates that
processor is being reset. This signal is being
synchronized to the processor clock and it can be
 Direct Memory Access (DMA) Signals used to reset other devices connected in the system.