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    ARM Microcontroller & Embedded Systems

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    ARM Microcontroller a Embedded Systems @ AS PER VTU CHOICE BASED CREDIT SYSTEM SYLLABUS @ SEM VI (EC/TC) ARM MICROCONTROLLER & EMBEDDED SYSTEMS Iresh A. Dhotre ME. (Information Technology) ExFoculty, Sinhgad College of Engineering une Atul P Godse M. S, Software Systems (BITS Pilani) BE. Industrial Electronics Formerly Lecturer in Department of Electronics Engg. Vishwokarme Insitute of Technology, Pune °, - T remice as pi ‘An Up-Thrust for Knowledge Bi https://www.facebook.comvtechnicalpublications @ ARM MICROCONTROLLER & EMBEDDED SYSTEMS Semester « VI (EC / TC) Ft Eden February 2018 Ft Rept: bony £019 © Copyright with Authors All publishing rights [printed and ebook versior) reserved with Technical Publicotions. No port ofthis book should be reproduced in any form, Electronic, Mechanical, Phoocopy or any information storage and retrieval system without prior permission in writing, from Technical Publications, Pune, ad naan TECHNICAL 5 °s:":: PUBLICATIONS C=! sueeSichuonatetn sy Printer Yogen Peto & Baden Ro 1a. ‘Gh el Ene, Nanded Vile Rod {ir iec Dat Pane" 417081 Price :€ 140/- ISBN 978-93-332-1788-0 89. {|| vis 9789333217880 (1) “i PREFACE The importance of Arm Microcontroller and Embedded Systems 1s well known in various engineering fields. Overwhelming response to our books on various subjects inspired us to write this book The book is structured to cover the Rey aspects of the subject Arm Microcontroller and Embedded Systems. | | The book uses plain, lucid language to explain fundamentals of this subject. The book provides logical method of explaining various complicated concepts and stepwise methods to explain the important topics. Each chapter is well supported with necessary illustrations, practical examples and solved problems. All chapters in this book are arranged in a proper sequence that permits each topic to build upon earlier studies. All care has been taken to make students comfortable in understanding the basic concepts of this subject. Representative questions have been added at the end of each section to help the students in picking important points from that section The book not only covers the entire scope of the subject but explains the philosophy of the subject. This makes the understanding of this subject more clear and makes it more interesting. The book will be very useful not only to the students but also to the subject teachers. The students have to omit nothing and possibly have to cover nothing more. ‘We wish to express our profound thanks to all those who helped in making this book a eality. Much needed moral suppor and encouragement is provided on numerous occasions by my whole family. We wish to thank the Publisher and the entire team of Technical Publications who have taken immense pain to get this book in time with quality printing. Any suggestion for the improvement of the book will be acknowledged and well appreciated. Authors DLA. Dhotre AP.Godse Dedicated to God « | SYLLABUS Arm Microcontroller and Embedded Systems [15EC62] Module -1: ‘ARM-32 bit Microcontroller - Thumi-2 technology end applications of ARM. Archinectre of ARM Conex MS, Vacious Units in the archhectare. Debugging suppor. General Purpose Registers. Special Regisers. exceptions. imernupss. stack operation. reset sequence (Chapter - 1) Module -@: ‘ABM Cortex Ms Instruction Sets and Programming : Assembly basics, Instruction st end descripson. useful insructions. Memory mapping. Bus imeriaces and CMSIS. Assembly and C language Progremming (Chapter-2) Module - 5: Embedded System Components : Embedded Vs General computing system. Classification of Embedded sysiems. Major applications and purpose of ES. Core of an Embedded System including al |7pes of processor/controlier. Memory. Sensors. Actuators. LED. 7 segment LED display. Optocoupler. | felay. Piezo buzzer, Push bution switch. Communication Interface (onboard and extemal types). Embedded firmeare. Other sysiem components. (Chapter - 3) Module - 4: |_ Embedded System Design Concepts : Characteristics and Quality Atributes of Embedded Systems Operational end non-operational quality anrbutes. Embedded tion and Domain design and development (excluding C language). (Chapter - 4) Module - 5: RTOS and IDE for Embedded System Design : Operating System basics, Types of operating systems. Tash. process and threads (Only POSIX Threads with an example program). Thread preemption. Preemptive Tesk scheduling techniques, Task Communication, Task synchronization issues - Racing and Deadlock. Concept of Binary and counting semaphores (Muter example without any program). How to choose an RTOS. Integration and testing of Embedded hardware and firmware, Embedded system Development Environment - Block diagram (excluding Kel), Disassembler/decompiler. simulator. emulator and debugging techniques (Chapter - 5) Chapter-1 Arm 32-Bit Microcontroller | (1-1) t0 (4-42) 11 Inroduction.. ete? 12 Thumb2 Technology. 1-2 13 Cortex-M3 Processor Appli wis | 1A Arciteture of Contex-M3 Pocestor........1-3. | 15 Register .. . aes 15. RO-RI2: General-Purpose Register «....1-5 RI :StacePointers. ses Rig: The Link Register... 1s RIS: The Progam Counter as | Special Registers... erie 155.1 Progam Sts Registers P5Ra) ...1-6 | 1.352 PRIMASK, FAULTMASK and BASEPRI Registers. 1 1553 Consol Regsers.. La 16 Debugging Support “8 1.7 Exceptions and Interrupts 1-8 | L741 Exception Types 18 Stack Operation... 1.81 CortMG Stack Implementation ...... 1-10 182. Two-Stack Model inthe Cortex-M3..... 1-10 19 Reset Sequence eu TABLE OF CONTENTS Chapter-2 Arm Cortex M3 Instruction Sets and Programming (2 - 1) to (2 - 50) Sh pssehy ui aa ii ase age eect 23 22 Instruction List w2-2 | IR 2 nay abaa ust ela | o 23 25 26 ay 222 General Data Processing Instructions ..... 2-3 2.23, Multiply and Divide Instructions 2-3 224 Saturating Instructions 2-4 22.5. Bitfeld Instructions. 24 2.2.6 Branch and Control Instructions. : 2.2.7. Miscellaneous Instructions 2.28 Unsupported Instructions... Instruction Description Basics....... 2-5 23.1 Operands, iagvigasitae 25) 23.2. Restrictions When using the PC or SP ....2-5 233, Flexible Second Operand 2-5 23.4 Shift Operations naded 234.1 ASR: An Arithmetic Shift Right ..2-6 23.42 LSR:A Logical Shift Right .......2-6 2343 LSL:A Logical Shift Left 23.44 ROR: A Rotate Right... 234.5 RRX. 22 23.5 Address Alignment. 2-7 23.6 Conditional Execution .. 2-7 23.6.1 Condition Flags 2-7 23.62 Condition Code Suffixes..........2+7 Instruction Description ..... 2-8 24.1 Memory Access Instructions. . 2-8 242 General Data Processing Instructions. ...2 = 14 2.41 Multiply and Divide Instructions 2-20 2.44 Saturating Instructions . 2-21 24,5. Bitfield Instuctions 2-22 2.66 Branch and Control Instructions 24 2.4.7 Miscellaneous Instructions 22 Useful Instructions... 2-32 Memory Map aha 2-32 Bus Interfaces on the Cortex-M3 12-33 27.1 The -Code Bus... : vd 28 29 210 wt) 2.72 The D-Code Bus 2-34 3.2.2 Performance and Complexity ‘2.7.3 The System Bus 2-34 Carucups 2.74 The Extemal PPB 234 89 AE Gee em nd Purpose of cMsIs 2-34 3.3.1. Major Application Area 28.1 Areas of Standardization. 2-35 3.3.2 Purpose with Embedded System, 2.8.2 Organization of CMSIS 12-38 3.4 Elements of Embedded System. 283. Using CMSIS 2-35 | 3,8 Core of Embedded System . 284 Benefits of CMSIS 2-37 3.5.1. Microprocessor... Assenbly and Language Progamming..2-37 352. Microcontroller 29.1 Using ¢ 2-38 3.53 Embedded Processor 292 Example ofa Simple C Program Using 254. Single Purpose Processor. RealView Development Site 2-38 mt eee 355. Difference between Microcontroller 2.9.3 Compile the Same Srample Using Ke Keil and Microprocessor. MDK-ARM..... 0.0.66 62-4 oe 294 rane cee eee Registers in C 2-42 3.5.7. RISC and CISC processor. 295 Intrinsic Functions w23 | 3.8721 Diteence Between RISC 296 Embedded Assembler and | =o, falas Ausenbiie. rae, wads | 3.58 Von-Neumann Architecture and : a etl Harvard Architecture sian y* - ant | 3.5.8.1 Difference between Von-Neumann 2 tact Amenbty 2648 | ‘Architecture and Harvard 2.10.2 Structure of ARM assembly module, 2-45 | dachitec. eeatteemnencen acl 3.59 Big Endian vs Litle Endian processors 2.104 Fist Step in Assembly rogramming....2-46 16 notetiieee 2.10.5 Producing Outputs. 2-47 3.5.11 Application Specific Integrated Circuit 2.10.6 "Hello World” Example . 12-47 | 3.5.12 Programmable Logie Devices... 2.10.7 Using Data Memory .......-++ 12-50 3,5.12.1 Comparison of CPLD and FPGA ee 3.5.13 Commercial Off the Shelf Components Chapter-3 Embedded System Components 36 Memory....... (3-1) to (3-44) 361 ROM... “ 3a. 32 3-2 302 Embedded Vs General Computing System. . 3.1 Embeadded System Definition. 3.2 History. Classification of Embedded Systems . 3.2.1 Generation Based Classification... 3.62. Random-Access Memories 3.62.1 Static RAM . 3.62.2 Dynamic RAM 3.62.3 Difference between SRAM sand DRAM . 3.63. Memory According to the ‘Type of Interfuce.......+.- TTECHOVCAL PUBLICATIONS”. An wp hal Kowa 3. ya 3 32 3-12 3-0 Bold 34 3eIS 3.15 et 3-16 3-16 3.7 3.18 3.18 19 3-20 a7 39 3.10 3.64 Memory Shadowing 3-20 3.6.5 Memory Selection for Embedded System 3 -20 3.66 Difference between RAM and ROM |... 21 Sensors and Actuators 3-21 32.1, Sensors 3-21 3.72. Actuators... 3.21 3.7.3 VO Subsystem... 3-21 3.74 LED. i 3-2 3.78. Seven Segment LED Display 32 3.7.6 Optocoupler. sensed 28 3:77 Relay. 3-04 Piczo Buzzer 2304 Push Button Switch... 38 3.7.10 Keyboard... sed h 3.7.11 Programmable Peripheral Interface (PPI). 3-25 ‘Communication Interface ....... 3-27 3.8.1 On Board Communication Interface. ....3-27 BBLAPC.... 3-27 3.812 SPI. 3-29 3.8.13 UART. 3-31 3.8.14 L-wire Interface 3-31 3.8.15 Parallel Interface 3-22 3.82. Extemal Communication Interface .....3 33 382.1 RS-232, 3-33 3.822 USB 3-34 3.823 TEBE 1394 3-35 3824 Infrared «5... 3-36 3.825 Bluetooth 3-37 3.8.2.6 Wii 23-38 3.82.7 Zighee 3-39 Embedded Firmware. . 23-39 Other System Components .. oe 3-40 3.10.1 Reset Circuit 3-40 3.102 Brown-Out Protection Circuit. 3-40 3.103 Oscillator 23-40 | | 3.104 Real Time Clock 3-41 3.10.5 PCB and Passive Components 3-41 3.10.6 Watchdog Timer 3M Chapter-4 Embedded System Design 4d 42 43 4s 46 47 48 Concepts (4-1) to (4-16) Characteristics of Embedded System 4-2 Quality Attributes of Embedded System......4-2 42.1. Operational Quality Attributes 42 422 Non Operational Atibutes, 43 ‘Application Specific Embedded System ~ Washing Machine... 43 Domain Specific Embedded System - Automotive... 45 44.1 Internal Working of Automotive Embedded System... cece cece 4S 442 Automotive Communication Buses ......4-6 442.1 Conttoller Area Network 4-6 4422 Local Interooneet Network... .A=7 4423 Media Oriented System Transport (MOST) Bus 47 4424 Key Players of the Automotive Embedded Market 48 Eundamentl sues in Hardware Software Co-Design »---.- anohe8 Computational Models in Embedded System...4-9 Embedded Firmware Design and Development 4-1 47.1. Super Loop Based Approach 42 472 OS Based Embedded Firmware Sesign ..4- 12 Embedded Firmware Development Languages 4-12 48.1 Assembly Language Based Development. 4-13 482 High Level Language Based Development. 4-15 483 Mining Asembly and High Level Language... 4-15 484 C Language VIS Embedded C TECHCAL PUBLICATIONS". np trust ownage 4.85 Compiler vs Cross Compiler. cede 16 Rare ee Chapter-5 RTOS and IDE for Embedded System Design (5 - 1) to (5 - 32) S.1 Operating System Basics. . sueivaeeS AY 5.1.1 User and Supervisor Mode 533 S12 Keenll..cssceeeees fesere S28 5.13 Monolithic Kemel 5-5 5.14 Microkemel..... TaahS 36 5.2 Types of Operating System... sereeS27 52.1 General Purpose Operating System ......5-7 $2.2. Real Time Operating System . 5-7 S221 Real Time Remel oo... .0.0.5-8 5.2.2.2 Hard Real Time. +510 5.2.23 Soft Real Time. Sesceeaese S10 5.2.2.4 Difference between Hard and Soft Real Time System... SI 53 Task, Process and Threads s-1 S31 Process... cece se Sed 53.2 Process State and State Transition ......5-11 533 Thread... 5-12 $33.1 Concept of Mlitreding. 5-13 533.2 Thread Standards 25-3 5.3.3.3 Thread Preemption ..........0...5-14 5.3.3.4 Difference between Thread and Process... $-15 54 Preemptive Task Scheduling Techniques ..-.5- 15 5.4.1 Preemptive Shortest Job First..........$-16 5.42 Round Robin Scheduling .. S-17 5.43 Priority Based Scheduling. ...........5-18 55 57 es 5.10 SAL sz 53 sad sus A rat PLeLGATONS- Ann reat ce ‘Task Communication 5.1 Shared Memory. . 55.2 Pipes 55.3 Message Passing 5.53.1 Message Queves $53.2 Mailbox 5.5.3.3 Signalling .. $53.4 Socket. 5.53.5 RPC. - “Task Synchronization Issues: Racing 5.6.1 Deadlock....... Concept of Semaphores. $7.1 Binary Semaphore. 5.7.2 Busy Waiting. . 5.13 Drawbacks of Semaphore... How to Choose an RTOS Integration and Testing of Embedded Hardware and Firmware ....... 59.1 Out of Circuit Programming. 5.9.2 In System Programming Board Bring Up........... Embedded System Derepenact Environment . . S.L11 Integrated Development Environment . Disassembler/Decompiler . . ‘Simulator, Emulator and na Debuasing Techniques 7 5.13.1 Simulator. 5.13.2 Emulator . 5.13.3 Debuggers . ‘Target Hardware Debugging. . Boundary Scan ... Se15 5-2 5-2 3-23 5-4 215-4 5-25 5-25 5-26 5-26 5-25 5-27 $-27 $-27 5-28 5229 25-29 5-29 25-29 5-30 5-31 5-31 MODULE - 1 Arm 32-Bit Microcontroller Syllabus Thumb-2 technology and applications of ARM, Architecture of ARM Cortex M3, Various Units in the architecture, Debugging ‘support, General Purpose Registers, Special Registers, exceptions, interrupts, stack operation, reset sequence Contents 14 Introduction... 1.2 Thumbe Technology 1.3 Cortex-M3 Processor Applications... .. 1.4 Architecture of Cortex-M3 Processor... .. 15 Registers... 41.6 Debugging Support .. 41.7 Exceptions and Interrupts... 1.8 Stack Operation........ 1.9 Reset Sequence ..... ‘Asm Microcontroller and Embedded Systems [Et] introduction + The ARM Cortex M3 is a low-power processor that features low gate count, low interrupt latency, and low-cost debug, elt is intended for embedded applications that require fast interrupt response features. +The processor implements the ARM architecture v7. Features 1. 32-bit microprocessor 2 32-bit data path, 32-bit register bank and 32-bit memory interfaces 3. Harvard architecture - Separate instruction bus and data bus. 3-stage pipeline with branch speculation ARMV7M architecture ‘Thumb-2 processing core sae Hardware division and single cyde multiply instructions Low gate count, suitable for low power designs. 9. Maximum of 240 external interrupts can be configured. Configurable Nested Vector Interrupt Controller vic. Memory Protection Unit (MPU) Operation Mode Selection - User and privilege modes. Low-cost debug optimized for microcontroller applications Mix of 16 and 32 bit instructions for very high code density 15, Complete thumb compatible «+ With these features the ARM Cortex M3 processor is able to address the following requirements of the 32-bit embedded systems. 1, Greater performance efficiency 2. Low power consumption to longer battery life 3. Make sure that critical tasks and interrupts are serviced in quick time. 4. Improved code density 10. 1 12. B. 4 2 Fete Arm 2:BItMicrcantty 5. Provide easier programmability and debugging 6. Lower cost 7. Wide choice of development tools Processor Modes «# The Cortex:M3 processor supports two modes «Handler mode + Processor operates in handle mode when it is running an exception handler + Thread mode : Processor operates in thread mode when it is running a main program. ‘+The Cortex-M3 processor supports two privilege levels « Privileged level : When the processor is running in thread mode, it can be in either the privileged co user level. User level : When the processor is running in handler mode, it can only be in the privileged level. «Code can execute as privileged (Privileged level) ot unprivileged (User level). Unprivileged execution limits or excludes access to some resources Privileged execution has access to all resources, Operating states «The processor can operate in one of two operating states ‘+ Thumb State : This is normal execution running 16-bit and 32-bit halfword aligned. Thumb and ‘Thumb-2 instructions = Debug State : This is the state when in halting debug, Review Questions, 1 List the fertures of ARM Cortex M3 processor. 2 List the requirements of the 32-bit embedded systens satisfied by ARM Cortex M3 processor. | 3. state the operating modes end operating states of ARM L__ Cortex M3 processor. 4.2 ‘Thumb? Technology ‘*The Thumb-2 technology extended the Thumb Instruction Set Architecture (ISA) into a high efficient and powerful instruction set. + Variable-length instructions “TECHRCAL PUBLICATIONS" Anup tat or wade ‘Arm Microcontroller and Embed Systems ‘Arm 32-8it Microcontroller 4.3 ] CortexM3 Proc: ‘or Applications ‘Thumb 2 tedrnology 32 and 16-bit ‘Thumb inevucion set Corter-M3.ARMV7-M architecture 16-08 Thumb instuston 9. 1.21 Relationship betwoan thumb technology and * ARM instructions are a fixed length of 32 bits * Thumb instructions are a fixed length of 16 bits *Thumb-2 instructions can be either 16-bit or 32-bit. + Improvement in code density over ARM ‘Improvement in performance over thumb ‘It allows more complex operations to be carried out in the thumb state rather than ARM state. This allows higher efficiency by reducing the number of states, + The Cortex-M3 processor can execute almost all the 16-bit thumb instructions, including all 16-bit thumb instructions supported on ARM7 family processors, making application porting easy. ‘+The thumb-2 instruction set adds important features such as «Hardware divide instruction + Number of multiply instructions. ‘The Cortex-M3 processor also supports unaligned data accesses. +The Cortex-M3 processor is not backward ‘compatible with traditional ARM processors. Thus, We cannot run a binary image for ARM? processors fon the Cortex-M3 processor. Review Question 1. Write a note on thumb2 technology. +The Cortex-M3 processor is specifically designed to develop high-performance low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors. Consumer products : Low power and high efficiency features makes it suitable for consumer products from toys:to electrical appliances. +Automotive body systems : Ideal for highly integrated and cost-sensitive automotive applications + Real-time systems : High-performance efficiency and low interrupt latency allows it to be used in real-time systems. + Data communications : Low power and high efficiency features along with the support of instructions in Thumb-2 for bitield manipulation, ‘make the Cortex-M3 ideal for many communications applications, such as Bluetooth and ZigBee. ‘Industrial control : Processor’s interrupt feature, low interrupt latency, and enhanced fault-handling features makes it suitable for industrial control applications where simplicity, fast response, and reliability are the key factors Review Question 1L_List the applications of Cortex-M3 processor 1.4 | Architecture of Cortex-M3 Processor + Fig 14.1 shows the architecture of Cortex-M3 Processor. The processor core implements the ARMV7-M architecture. It is a Harvard architecture, Which means that it has a separate instruction bus and data bus. + This allows instructions and data accesses to take place simultaneously thus increasing the Performance of the processor. However, the instruction and data buses share the same memory space (a unified memory system). ¥ "EPR rw ma ene ‘Arm Microcontroller and Embedded Systems + The Cortex™M3 is a 32-bit microprocessor. It has a 32-bit date path, 2 32-bit ALU (Arithmetic and Logic Unit), 2 32-bit ‘register bank, and 32-bit memory interfaces. «Registers : The processor contains 13 general Purpose 32-bit registers, Link Register (LR), Program Counter (PC), Program Status Register and two banked SP registers. + Memory Protection Unit (MPU) : The Cortex:M3 processor has an optional Memory Protection Unit (MPU), and it is possible to use an external cache. Debug System and Interface : The Cortex:M3 Processor includes a number of fixed intemal debugging components. These components provide debugging operation supports and features, such as breakpoints and watch-points.. In addition, optional components provide debugging features, such as instruction trace, and various types of debugging Ls 7 Arm 2.3 Micon latency interrupt processing. The main feature, include + Can configurable number of extemal interrup, from 1 t0 240 + Can configurable number of bits of priority, from three to eight bits + Supports level and pulse interrupt + Supports dynamic reprioritization of interrupts + Supports priority grouping + Supports for tailchaining of interrupts + Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. «Bus Interconnet : The bus interconnet connects the processor and debug interface to the external buses It interfaces to extemal buses such as ICode, DCode, system bus and Private Peripheral Bus (PPB). aes avi Outon spi Be acter f Ck +Neved Vere Intemupt Contller exvic) + || Behn he nits of Nested Vectored Interrupt Controller (NVIC) closely Integrated with the proctor ce 1 achieve lv ‘Cortex-M3 | i TET ve" a —n Ht xc || sil onete| LET onsen TY ree rieots[ — Yee sr ' gee [) se aw |é ‘Memory interface vo Ky | Memory t | tmonctentel |, Lowe | | ‘unit i | | aay ewig |[yueomenal| es | oe, || mempgiene |] cae, - | orton TECHNICAL PUBLICATIONS". Anup trot erie 1444 Architecture of Cortex-M3 Processor ‘Arm Microcontroller and Embedded Systems Rogisters + The processor has the following 42-bit registers : ‘#13 general-purpose registers, r0-r12 ‘+113 (the stack pointer) is banked, with only one copy of the r13 visible at a time. Link register, r14 Program counter, 115 '* One program status register, xPSR. 1.8.1 | RO-R12 : General-Purpose Registers + RO-R12 are 32-bit general-purpose registers for data operations + Low registers: Registers RO-R7 are accessible by alll instructions that specify general-purpose register. “High registers; Registers R8-RI2 are accessible by all 32-bit instructions that specify a general-purpose register. Registers R8-R12 are not accessible by all 16-bit instructions, 1.5.2] R13 : Stack Pointers +The Cortex-M3 contains two stack pointers (R13). ‘They are banked so that only one is visible at a time Low registers High registers AY Link regis Ta Program counter | R15 Program status register L___>PSR. Pi 184 Rogie oganizaton of Caracas Poceator rT TECHNICAL PUBLICATIONS” An up tt fr towlecs ‘Arm 22:4 Microcontroller += The two stack pointers are as follows + Main Stack Pointer (MSP) : The default stack pointer, used by the operating system (QS) kernel and exception handlers Process Stack Pointer (PSP) : application code ‘+ The lowest 2 bits of the stack pointers are always 0, which means they are always word aligned. Used by user 4.5.3 | R14 : Tho Link Register + Register r14 is the subroutine Link Register (LR); it is used to store the return address of the subroutine, + The LR is also used for exception return. At all other times, we can use RId as a general-purpose register. 1.54] R15 : The Program Counter +The program counter holds the address of the ‘current instruction to be executed. Bit [0] is always 0, so instructions are always Aligned to word or half-word boundaries. [Focess slack pore} rogram status rogietere Interrupts mask Special registers registers Conti register He : ‘Arm 328i Micocontoty 1554 Special Registers + The Cortex-M3 processor also has a number of special registers. They are as follows : + Program Status registers (PSRs) + Interrupt Mask registers (PRIMASK, FAULTMASK, and BASEPRI) * Control register (CONTROL) + Special registers can only be accessed via MSR and MRS instructions; they do not have memory addresses : MRS , ; Read special register MSR , ; write to special register Program Status Registers (PSRs) + Processor status at the system level breaks down into three categories + Application PSR (APSR) : Read/Write ‘Interrupt PSR (IPSR) : Read Only « Execution PSR (EPSR) : Read Only +The three PSRs can be accessed together or separately using the special register access instructions MSR and MRS. Examples MRS RO, APSR ; Read Flag state into RO MSR APSR, RO ; Write Flag state from RO MRS RO, IPSR ; Read Exception/Interrupt state into RO MRS RO, EPSR ; Read Execution state into RO + When they are accessed as a collective item, the name xPSR is used. Examples MBS RO, PSR ; Read the combined program status word into RO MSR PSR, RO ; Write combined program state word from RO — —— ae we [eet [oa [5 [eee] oor [a Fig. 1.5.2 Program Status Registers (PSRs) in the Cortex-M3. 7 “PPP wa |u| aw [aw lel> [es] WSR NZ amr | tom Expection number Fig. 1.5.3 Combined Program Status Registers (xPSR) in the Cortex-M3 IN: Negative or less than flag + 1 = result negative or less than = 0 = result positive or greater than. po eee eee ea ea TECHNICAL PUBLICATIONS". Anu tu owedpe ‘Arm Microcontroller and Embedded Systems Z : Zero flag : | +1 result of 0 + 0= nonzero result. + Carry/borrow flag: +1 = cary or borrow #0 = no carry or borrow. Overflow flag | «1 = overflow: | #0 = no overflow Q : Sticky saturation flag ICIAT ; Interrupt-Continuable Instruction (ICI) bits, IF-THEN instruction status bit. T: Thumb state, always 1; trying to clear this bit will ‘cause a fault exception. Exception number : Indicates which exception the Processor is handling, 4.52] PRIMASK, FAULTMASK and BASEPRI Registors +The PRIMASK, FAULTMASK, and BASEPRI registers are used to disable exceptions “PRIMASK : A L-bit register, when this is set, disables (maskes) all interrupts except the on-maskable interrupt (NMI) and hard fault. ‘sFAULTMASK : A L-bit register, when this is set, disables (maskes) all interrupts except the NMI * BASEPRI : A register of up to 8 bits (depending on the bit width implemented for priority level) It defines the masking priority level. When this is set, it disables (maskes) all interrupts of the same or lower level (larger priority value). +The PRIMASK and BASEPRI registers are useful for temporarily disabling interrupts in timing - critical tasks, ‘+ An OS uses FAULTMASK to temporarily disable fault handling when a task has crashed to prevent interruption by other faults caused by the crashed | process. + Usually the device driver libraties provide functions to access the PRIMASK, FAULTMASK, and BASEPRI registers. For example, TECHNICAL PUBLICATIONS” 7 ‘Arm 32.5 Microcontroller = _got PRIMARK); _// Read PRIMASK register set PRIMASK(s), 11 Sec naw value for PRIMASK = _get FAULTMASK); // Read FAULTMASK register set FAULTMASK(2); _// Sot now value for FAULTMASK, 2= get BASEPRIQ; // Road BASEPRI register set BASEPRI(3); 11 Set new valve for BASEPRI —Alisable_irq0: 11 Clear PRIMASK, enable TRO able_iraQ); 1/ Set PRIMASK, disable IRQ + In assembly language, the MRS and MSR instructions are used to access the PRIMASK, FAULTMASK, and BASEPRI registers. For example : MRS RO, PRIMASK _; Read PRIMASK register into RO MRS RO, FAULTMASK ; Read FAULTMASK register into RO MRS RO, BASEPRI _; Read BASEPRI register into RO MSR PRIMASK, RO; Write PRIMASK register from RO (MSR FAULTMASK, RO ; Write FAULTMASK registor fram RO ‘MSR BASEPRI, RO: Write BASEPRI register from RO +The PRIMASK, FAULTMASK, and BASEPRI registers cannot be set in the user access level. [1553] contro! Registers ‘+The control register is used to define the privilege level and the SP (Stack Pointer) selection, It has 2 bits CONTROL{I] and CONTROL{0} ‘+ CONTROL{1] : Stack status +1 Alternate stack (PSP) is used "0 = Default stack (MSP) is used ‘If it is in the thread or base level, the alternate stack is the PSP. There is no altemate stack for hhandler mede, so this bit must be 0 when the Processor is in handler mode. = CONTROL|0] ‘+0 = Privileged in thread mode 1 = User state in thread mode "If in handler mode, the processor operates in privileged mode. Review Questions 1. Draw and explain the repister organization of Corter-M3 Procesor Expltin the se of stack pointer, link register and rogram counter in Cortex-M3 Processor. 2 Au rst er tenn ‘Anm Microcontroller and Embedded Systems 18 Arm 32Bit Microccnnte 3. List the special registers supported by Cortex-M3 Processor. 4. Write « note on Program Status Registers (PSRS). 5. Draw the bit pattern of PSR. 6. Write a note on control register. 4.6 | Debugging Support + The Cortex-M3 processor contains several system debug components that facilitate program execution controls, including halting and stepping, instruction breakpoints, data watch-points, registers and ‘memory accesses, profiling, and traces. « The system debug components are : + Flash Patch and Breakpoint (FPB) Unit: It is used to implement breakpoints and code patches [4 atch is a software update comprised code inserted (or patched) into the code of an executable rogram|. It provides builtin support for six breakpoints * Data Watch-point and Trace (DWT) Unit : It is used to implement watch-points, trigger resources, and system profiling, The data watch-point function can be used to stop the processor (or trigger the debug monitor exception routine) or to generate data trace information. When data trace is used, the traced data can be output via the Trace Port Interface Unit (TPIU). + Instrumentation Trace Macrocell (ITM) : It provides a new way for developers to output data to a debugger. By writing data to register memory in the ITM, a debugger can collect the data via a trace interface and display or process them. + Embedded Trace Macrocell (ETM) : It is used for instruction trace. The processor is supported in versions with and without the ETM. + All the debug components exist on the intemal Private Peripheral Bus (PPB) and can be accessed using privileged code. Review Question 1. Write a note on debugging support provided by Cortex-M3 Processor. [Ez] exceptions and Interrupts "The Cortex-M3 processor supports interrupts and system exceptions. The processor and the NVIC prioritize and handle all exceptions. An exception changes the normal flow of software contro. The processor uses Handler mode to handle all exceptions except for reset «The Cortex-M3 supports a number of exceptions including a fixed number of system exceptions and 2 umber of interrupts, commonly called IRQ. The number of interrupt inputs on a Cortex\8 rricrocontroller depends on the individual design. The typical number of interrupt inputs s 16 o 3. « Besides the interrupt inputs there is also a non-maskable interrupt (NMI) input signal. The actual se of NMI depends on the design of the mictocontroller system. In most cases, the NMI could be connected to @ watchdog timer or a voltage-monitoring block that warns the processor when the voltage drops below a certain level. TECHNICAL PUBLICATIONS". An ptt or knowadoe ‘Arm Microcenrli nd Embedded Systems 19 ‘Arm 32-0 Micrconrller 3, highest xoncanene Invoked on power up of «warm ret m2 xencon00s Now-MashableInterupt (NMD can be signalled by a peripheral or tggered by software rr 00000006 ‘Oceary because of en eror during exxption Prosesing Configurable xc0020010 Memory management curs bacuse of | protection related ful cused by | MPU'velabon or inva scenes, 15) Bostault Configurable ncoconots us error enused by an instrcton prefetch cee | 16) VeageFantt ——Contigursble 300000018 ‘Occurs because of a fault related to instrcon ‘execution. This inclides: an undeined Instruction, an illegal unaligned access, invalid state on instruction execution oF an error On I j : Spon een 17.210) Reserved z z ‘511 Svea Contigurable “Teigered by the SVC (Service Call) natrvcton ft249) Revved ee us] Penasy Configurable yor000088 interuptsriven pendabe raquest fr system service 15) SysTiek Condigurble ———_oxpemenp9c Ste wk ter generate exception when 00000040 q ‘IRQ input #0-239 : exception signalled by a ae Uo pened by eee Table 1.74 Proportion ofthe afferent exception types +The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler mode. Processor state is automatically stored to the stack on an exception, and automatically restored ffom the stack at the end of the Interrupt Service Routine (IR). Review Question 1 Write ante on inkeraplsanexeptons supported by CorterM3 Prose 4.8 ] Stack Operation + Stack is a part of RAM in which data will store temporary during execution of program. Stack ‘operations are memory write or read operations, with the address specified by an Stack Pointer, SP. ‘+ PUSH operation saves data in registers into stack memory and POP operation restores data from stack into register. During these operations SP is adjusted automatically so that multiple data PUSH will not cause old stacked data to be erased. + Stack works as a first-in/last-out buffer. Fig. 1.8.1 shows the operation of stack co TECHCAL PUBLICATIONS” An pt ope ‘Arm Microcontoler and Embedded Systems 110 Push Operation tages | See i ‘ood | push | | Dateprcessing | eal 1 _ (origi oe 1 oases ee SP — 001H yee _—s pet > am I Tso 10034 a : ‘SP decrements before PUSH operation ‘SP increments aft POP operation Fig. 1.8: Stack PUSH and POP operation +The SP points to the last data pushed to the stack ‘memory, and the SP decrements before a new PUSH operation. + For POP operations, the data is read from the ‘memory location pointer by SP, and then, the SP is | ‘incremented. 4.8.4 Cortex-M3 Stack Implementation + In Cortex M3 processor registers are 32-bit. Thus, each PUSH/POP operation transfers 4 bytes of data | (cach register contains 1 word, or 4 bytes), the SP decrements/increments by 4 at a time or a multiple of 4 if more than 1 register is pushed or popped. ‘This is illustrated in Fig. 182. \as2.8i= “In the Cortex-M3, R13 is defined as the SP. ‘Two-Stack Model in the Cortex-M3 +The Cortex MB has two SPs : the MSPS and th PSP. The SP register to be used is controlled by th control register bit 1. CONTROL = 0 «When CONTROL] is 0, the MSP is used for bot thread mode and handler mode, In this case, the rain program and the exception handlers share th same stack memory region, as shown in the Fig. 183. (See Fig, 183 on next page) «This is the default setting after power-up. ( Push Operation POP Operation ) | ; Resieter | Regiser Memory ! Wemey fants corer co restr Date processing | | ee (orginal register | | “0008 ccntnts dstoyes) | | | see soos} 4 | | sore |] T | | sooe|——I} | i | i i | | ' ! | | } ‘SP decrements by 4 before PUSH operation Fg. 1.8.2 Stack PUSH ar ‘SP increments by 4 after POP operation POP operation in the Cortex.M3 TECHNGCAL PLBLCATONS™ An up tt ope ‘Arm Microcontroller and Embed Sytem an Arm 32-it Microcontroller / isa ism ( Bega El ) | tomt sren email routine Se) ot | Main reorem Resting roumvaderss i 1 Time Trveadmode | Hendeemode | “vend made (use MSP) 1 (use MSP), 1 (use MSP) \ i i J Fig, 183 CONTROL[1] = 0: Both thread lovel and handler use main stack CoNTROLIt] = 4 Review Questions When the CONTROL{I] is 1, the PSP is used in| | 1. What sack ? thread mode. In this case, the main program and 2. Explain the PUSH and POP eperatons with the help of the exception handler can have separate stack eat diagram, memory regions, a shown in Fig. 184. This can | | 3 Enh option of ck the Carter Prevent a stack error in a user application from cna ai eh ur nll damaging the stack used by the OS. 1.9 | Reset Sequence Here, the automatic stacking and unstacking | : mechanism will use PSP, whereas stack operations | *After the processor exits reset, it will read two inside the handler will use MSP. ‘words from memory from the specific address +t is possible to perform read/write operations ‘From address 0x00000000 : It reads starting value directly to the MSP and PSP, without any confusion | oF RIS (the SP) of which 13 we are eerang to. In privileged "Pom address OxO00004 : Reset vector: reads level, we can access MSP and PSP values using the starting address of program execution; LSB lpia eee seid sae deta | shouldbe set to 1 to indicate Thumb state HA isk Begin | 1 iwrptsenice ‘Storing retum address Restoring return address | Time Thread mode (use PSP) ) | Twesamode | Handermode (use PSP) ' Fig, 1.84 CONTROL{(] = 1: Thread level uses process stack and handler uses main stack ¥ "Rom LEONE ‘Arm MlcrocontollerandEmtedded Systems = In case of RESET, the program execution address is read from the RESET vector location. Thus by putting branch instruction at’ the vector location we can put RESET exception handler in another location in memory. +Since the initial value for the MSP is put at the beginning of the memory map, stack memory space ‘can be relocated anywhere in the memory map. ‘+ Because the stack operation in the Cortex-M3 is a full descending stack, the initial SP value should be set to the first memory after the top of the stack region. For example, if we have a stack memory Fange from 30007CO0H to 30007FFFH (1 KB), the initial stack value should be set to 30008000H. «The vector table starts at 00000004H, initial SP value. The first vector is the reset vector In the CortexM3, vector addresses in the vec, table should have their LSB set to 1 to indicate th they are Thumb code. Here, reset vector has addr 00000201H. After the reset vector is fetched, 4, processor starts execution of the program (Bg code) from the reset vector address. ‘* Usually, Boot code start with the initialization of sp because some of the exceptions (such as NMI) cx occur right after reset, and the stack memory cou) be required for the handler of those exceptions Review Question 1. Explain reset sequence with the help of memory map Omer nano nim gene | sotcsoo i 5 a doormen | eae ourered [ie cox | oe 30007C00H | 1 ‘Other memory | ; | | ai | | (00000200H | ogg |) | gan agi | 00000061 HT ooo002074 fed oe | 00000000H 30008000H. TECHNICAL PUBLICATIONS”. Arp that or oud oad MODULE - 2 2 Arm Cortex M3 Instruction Sets and Programming Syllabus Assembly basics, Instruction list and description, useful instructions, Assembly and C language Programming Contents 241 Assembly Basics. 2.2 Instruction List. 2.3 Instruction Description Basics... 26 Instruction Description .. 2.5 Useful Instructions. . 2.6 Memory Map... 2.7 Bus Interfaces on the Cortex-M3. .... 28 (WSIS ....... 2.9 Assembly and C Language Programming, 210 Using Assembly... eee eeeeee eal cratala ‘Arm Microcontroller and Embeded Systems 24 Assembly Basics 244 ‘Assembler Language : Basic Syntax + Generally, assembler code comprises fou ficlds 1. Label field 2. Operation field 3. Operands field 4. Comment field In assembler code, these fields are arranged in a specific sequence to give the following instruction format : Label opcode operandi, operand2, ..; Comments DR Fig, 2.4.4 Examples of syntax of the ARM Cortexi2 sembly Instructions, + Label : The label is optional. It is used to provide a symbolic memory reference, such as a branch instruction’s address or a symbol for a constant +A label must be located at the first column and started in the first character position in the instruction line. The length of each label is limited to 15 characters, which include upper- or lower-case letters (az), digits 0-9, the period, dollar sign and underscore. The first character must be alphabetic, a period or an underscore. A label may end with a colon. *Opcode : Opcode is an operation code which decides the operation to be performed by processor. + This field is also called mnemonic field. + Operand : The opcode is followed by a number ‘operands. The operands field contains the data an address for its corresponding instruction to ‘operated or performed. of be | | | | | | | | | TECHNICAL PLBICATIONS™. Ano ret or montage ‘A Cate M3 tation Stand Progra, «The number of operands in an instruction de con the type of instruction. Normally, the fin ‘operand is the destination ofthe operation. «Comment : This field enables users to place som comments for each instruction to illustrate th, function or purpose of the related instruction line ‘All comments must start with the semicolon (), «+ An assembly directive is a piece of information thy appears word-for-word in the listing and which ig supplied by the assembler to give the construction rules of the executable. + These lines in the source file, though an integry part of the listing and necessary for its coherence, do not correspond directly to any line of code. +A number of data definition directives are available for insertion of constants inside assembly code. + For examples : + EQU defines constants = DCT directive allocates two or four-byte aligned ‘memory and defines the initial runtime conten; of the memory, + DCB directive allocates one or more bytes of ‘memory and defines the initial runtime conten of the memory. + DCD directive allocates one or more words o ‘memory, aligned on four-byte boundaries and defines the initial runtime contents of te memory. ‘Immediate data are usually in the form ¢number Review Question 1, Explain the assembly language syntax 2.2 | Instruction List The instructions “supported by the Cortef processor can be categorized as : «+ Memory access instructions + General data processing instructions + Multiply and divide instictions + Saturating instructions + Bitfield instructions ‘Arm Microcontrlle and Embed Systems + Branch and control instructions + Miscellaneous instructions 224 Memory Access Instructions Table 2.2.1 shows the memory access instructions. ‘Mnemonic ADR CLREX LDM (mode) EDR (type LDR itypel LDR type T UDR (type) ‘UDRD LLDREX (typet FOP PUSH STM (mode) STR (type) STR {type} STR {type} T STREX (om) 2.2.2 Ger Brief Deseription Lead Frater Ce exe | Lond mall pte Load ger mained fe Eclnce wey eres] od reper th unplpe se Load register using PC-relative address | Load register using PCreltive adres (wo wou Tae es Tans ‘Push registers onto stack | Se Sone Se Sic va aa ee Sue Table 2.2.1 Momory access instructions ral Data Processing Instructions SUB. SEM TEQ 1st | [bas Table 22.2 shows the data processing instructions. aa Brief Description instructions Add wi PRL ADC Add with any z ADD Aad eee | | | xa’ ADDW Add o | | aND Logical AND | oa | Mu. | ASR Anthmetic sit ight i | | Bic Bit clear ogial AND one vale with sow the complement of another vale) ||| gag) ap az. Count leading zeros | 2 Sram renee, ae aan ey | Logical shift right iy Tice aera Logical OR NOT cae oe ein ees Reverse byte in each halfword Reverse byte order in bottom halfword, and sign extend Rotate right | Rotate right with extend _ Reverse subtract ot with oa Test equivalence Test | Tablo 2.2.2 General data processing instructions Multiply and Divide Instructions 223° shows the multiply and divide Bilef Desciption ‘Multiply with accumulate, 32-bit result Multiply, 32-bit result Signed divide Signed muliply with accumulate =| Mulipty and subracy, 52-bit result © a 32 + 68), Obit result ‘Aan Microcontroller and Embedded Syteas SMULL Signed multiply (32 « 32), oLbit result | | UDIV Unsigned divide ‘Unsigned multiply with accumulate __G2¥32 + 68), bit result Unsigned multiply (2 = bit rosll ‘Table 2.2.3 Multiply and divide instructions 2.2.4 | Saturating Instructions Table 2.24 shows the saturating instructions, Mnemonic Brief Description [SAE Soret se USAT Unsigned saturate Table 2.2.4 Saturating instructions 2.2.5 | Bitfield Instructions Table 2.25 shows the instructions that operate on adjacent sets of bits in registers or bitficlds Bret Description Table 2.2.5 Bitfield instructions 2.2.6 | Branch and Control instructions. Table 2.2.6 shows the branch and control instructions, ‘Mnemonic ‘Brief Description F B Branch BL Branch with ink BLX Branch indiget wit ink ‘Am Cove M0 ston Se Poy aaa | eE ceccaneas | eee | coz Compare and branch t zero | eS a : 4 Table 2.2.6 Branch and control instructions 2.27 | Miscellaneous Instructions Table 2.27 shows .the remaining Cortex instructions Tet Descipton | | ont atepont eas | cPSID Change processor state, disable | i interrupts | [caste Change proceso sit onabe | nee [2M Dim menory bene | [= | 138 Instruction synchronization I fete Ces ear register | eae | ae | oP No operon | sev ‘Send event — | WWrE Wa for even WE Wal for berapt | ‘Table 2.2.7 Miscellaneous instructions Unsupported Instructions * Table 2.28 lists the number of Thumb instruction are not supported in the Cortex-M. TECHNICAL PUBLICATIONS". Anup trees ‘Arm Microcontroller and Eabedded Systems Unsupported | Function instruction | BL able ‘This is branch with ink and exchange Sue In format wah meine at | BUX ah {AEM sate, Beenss the CortecMS doesnot Support the ARM state, instructions ike tis one that attempt to switch to the ARM state will result ina fault | cexpection called usage fault This Thumb instruction introduced in axclutecrure ve, switches the endian contiguration during run time Since the Cortex does not support dynamic endian using the SETEND instruction wil ressifin'a fault | exception. Bae) Table 22.8 +The CortexM3 processor does not have any coprocessor support. + The Change Process State (CPS) instructions are also not supported in the Cortex-M3, Review Questions ] 1. List the various types of instructions supported by | Cortex M3 processor. 2. List any four memory acess instructions supported by Cortex M3 processor. 3. List ony four general date. processing instructions supported by Cortes M3 processor. 4. List multiply and vide instructions supported by Cortex M3 processor. 5. List saturating instructions supported by Corer M3 processor 6. List any four bitfield instructions supported by Cortex M3 procesor. 7. List any four branch and control instructions by Cortex M3 processor 8. List any four miscellaneous instructions supported by Cortex M3 processor 2.3 Instruction Description Basics 2.3.4 Operands ‘An instruction operand can be an ARM Cortex-M3 register, a constant, or another instruction-specific parameter. ‘Instructions act on the operands and often store the result in a destination register. rT TECHNICAL PUBLICATIONS". Ar op hut row ‘Arm Cortex M3 Instruction Sets and Programming When there is a destination register in the instruction, it is usually specified before the operands, [2.3.2 | Restrictions When using the PC or SP * Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack Pointer (SP) for the operands or destination register, + Bit{0] of any address you write to the PC with a BX, BLX, LDM, LDR or POP instruction must be 1 for correct execution, because this bit indicates the required instruction and the CortexM3 processor only supports Thumb instructions. 23.3, Many general data processing instructions have a flexible second operand. This is shown as operand? in the descriptions of the syntax of each instruction. *Operand2 can be a constant or a register with optional shift Flexible Second Operand Register with optional shift ‘You specify an Operand2 register in the form Rm {, shift} where Rm Is the register holding the data for the second operand, ‘shift : Is an optional shift to be applied to Rm, It can be one of © ASR wn : Avithmetic shift right n bits 1 RE. R10, Ra, R1,R5 ——; Multiply with accumulate, RIO = (R2 x Rt) + RB, MULS RO, RZ, FZ ‘Multiply with fag update, RO = R2 Xx R2, MULLT Fz, RS, Ra + Conditionally multipy, R2 = R3 x R2, MLS __R4,R5,R6,R7__; Multiply with subtract, R4 = R7~(R5 x RE) 1 RdPl, Rdlo : Aro the destinstion registers For UMLAL and SMLAL they also hold the accumula value. Re, Rm: Ato registers holding the operands, aa TEOWICAL PUBLICATIONS Anu rat rope : ‘Arm Cortex MG Intruction Ses and Programming | operation: ‘The UMULL instruction interprets tho valuos from Rn and Rim as unsigned integers, ft multiplies theoo| | {integers and places the least - significant 32 bits of the result in RdZo, and the mest-sigaificant 32 bits of | the result in RdH ‘The UMLAL, instruction interprets the values ffom Rn and Am 4s unsinged integers. It multiplies these! fntegors, adds the 64-bit result to the 6i-bit unsigned contained in RdFli and AdLo, and writes the recule Deck to Aditi and Rao. ‘The SMULL instruction interprets the values trom An and Rm as two's complement signed integers. tt | multiplies these integers and places the least-significant 32 bite of the regult in RdLo, and. tho! mostsigniicant 32 bits of the result in Rd ‘The SMLAL instruction interprets the values from Rn and Rm es two's complement signed integers. It rmukiplies these integers, adds the 64-bit result to the 64-bit signed integer contained aH and Rao, and’ ‘writes the result back to Rai and Rdlo, Condition Flags : These instructions do not affect the fags, Examples UMULL —RO,R4.RE,RE —_; Unsigned (R4, RO) = RS x RE, SMLAL Rt, R5,R3,R8_; Signed (RS, Ré) = (RE, Ré) + R x RE. |SDIV and UDIV : Signed Divide and Unsigned Divide ‘ wart SDIV { cond } { Ra, } Ro, Rm UDIV { cond } ( Ré, } Ra, Ren cond Is an optional condition code, "Fd: Is the destination register. If Rd is omitted, the destination register is Rn. = Rn: Is the register holding the value to be divided, = Rm_: Is a register holding the divisor, Operation: SDIV performs a signed integer division of the value in Rn by the value in Rm, UDIV performs an unsigned integer division of the value in An by the value in Rim. For both instructions, if tho valuo in Ra 48 not divisible by the value ia Rm, the result is rounded towards zero, | Condition Flags : These instructions do not change the flags Examples : SDIV RO,R2R4 —_; Signed divide, RO = R2/ RA DIV _R8ROR1 _; Unsigned divide, RS = RO/ RA. 2.4.4 | Saturating Instructions Syntax : op { cond } Ra, #a, Rm {, shift #2} +0 1s one of | SSAT : Saturate a signed value to a signed range. | USAT; Saturate a signed value to an unsigned range, ‘cond _: Is an optional condition code, ¥ TEGAMCAL PUBUEATIONS. An pha wage ‘Anm Microcontroller and Embedded Stes Examples : USATNE Syntax + [BEC and BRT; Bit (eld Clear and Bit Field Invert Anca hn Se ag Fd: Is the destination rogister an Spvcitis the bit position to saturate to 2 ranges tom 1 to 92 for SSAT ‘ranges trom 0 to 3t for USAT Rm Is the register containing the value to saturate, ‘shit # 5: Is an optional shit applied to Rm before saturating. It must be one of the folowing + ASR # 2: Where # is in the range 1 t0 31 1 ESt # §: Whore sis in the range 0 t0 31 ‘These instructions saturate to sigued of unsigned r-bit valu, ‘The SSAT instruction applies the specified shit, then saturates to the signed range 2°!

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