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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2020.2978670, IEEE
Transactions on Power Electronics

Fault Detection and Localization for Cascaded

H-Bridge Multilevel Converter with Model
Predictive Control
Merlin Chai, Member, IEEE, Naga Brahmendra Yadav Gorla, Member, IEEE, and
Sanjib Kumar Panda, Senior Member, IEEE
Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117581

Abstract—The cascaded H-bridge (CHB) multilevel converter io,1

has been used in various applications, such as the STATCOMs
and solid-state transformers. Due to its modular structure, fault Rs Ls S11 S31
vH1 Co,1 Zo,1
tolerance can be incorporated in the CHB multilevel converter. vo,1
H-bridge cell 1
In this manuscript, a model predictive control (MPC)-based fault is S21 S41
detection and localization (FDL) scheme is proposed for the CHB
multilevel converter that utilizes the already-installed AC current H-bridge cell 2
measurement and does not require additional sensors. The vs vCHB
proposed FDL scheme can detect single or multiple open-circuit io,n
switch faults in the CHB multilevel converter by comparing the
predicted states of the MPC controller with the actual measured S1n S3n
states. The detected fault(s) is(are) further localized through a vHn Co,n Zo,n
H-bridge cell n vo,n
fault localization matrix which narrows down the faulty switch
using historical fault data. The proposed scheme is shown to S2n S4n
complete the FDL process for both single or multiple open-switch
faults within a fundamental cycle period, even during low-load
conditions. It has also been shown that the proposed scheme is
immune to system dynamics such as load and voltage variations, Fig. 1. Topology of a (2n+1)–level cascaded H-bridge multilevel converter.
and have been validated experimentally for various open-circuit
fault scenarios.
Index Terms—fault detection, fault localization, model predic-
tive control, cascaded H-bridge, multilevel converter

I. I NTRODUCTION
With increasing voltage-blocking and current-carrying ca-
pabilities of power semiconductor devices, particularly SiC
switching devices, there has been recent interest in high-power
power electronic converters, especially multilevel topologies
[1]. In particular, the cascaded H-bridge (CHB) multilevel
converter [2], as shown in Fig. 1, has been widely used in
industry for various applications, such as static synchronous
compensator (STATCOM) [3], automotive motor drives [4],
and PV systems [5]. The CHB multilevel converter has also
been developed for traction transformer applications [6], [7].
A recently popular topic which utilizes the CHB multilevel
converter is the solid-state transformer (SST), which has been
researched and developed by both research and commercial
entities to be used in distribution systems [8]–[10]. Various
control techniques have been proposed for the CHB multilevel
converter, such as conventional cascaded two-loop control [11]
and sliding mode control [12] to control the AC source current
and H-bridge cell DC voltages. Voltage balancing issues of
the individual H-bridge cells have also been addressed using
power flow management [13] and model predictive control
[14].
The use of model predictive control (MPC) has also been
proposed for the CHB multilevel converter and other multi-
Fig. 2. Timeline of expected power electronic converter behaviour during
fault occurrence.
level topologies, as it appears promising for these topologies
with good steady-state performance and superior dynamic
response compared to the conventional cascaded two-loop con-
trol methods [15]. Finite control set-model predictive control
(FCS-MPC) with the main control objectives of sinusoidal
source current and control of the DC voltages to their set-
points has been detailed in [16]. Power balancing in the
individual H-bridge cells of the CHB multilevel converter
has been addressed using FCS-MPC [17]. Additional control
objectives such as reducing the average switching frequency
for loss minimization [18] and reducing the computational
burden [19] using FCS-MPC in CHB multilevel converters
have also been proposed.
A timeline of the expected behaviour of a power electronic

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Transactions on Power Electronics
converter when a fault occurs is shown in Fig. 2. It can
be seen that in an ideal situation, any fault that occurs
should be quickly detected, localized, and isolated. Fault-
tolerant operation for the CHB multilevel converter has been
well-researched and various solutions have been proposed. In
standalone applications for the CHB multilevel converter, such
as static synchronous compensator (STATCOM), the use of a
modified selective harmonic elimination technique for fault-
tolerant operation has been proposed [20]. A method for power
generation sharing capability is also proposed for large-scale
PV applications [21]. In terms of hardware, redundant modules
can be activated after a fault is detected [22]. These redundant
modules can also be used in normal operation to improve
the output voltage harmonic performance [23]. A modified
cascaded H-bridge multilevel converter structure has also been
proposed to improve its post-fault operation and reliability
[24]. For SSTs, in which the CHB multilevel converter forms
the first stage, the second stage of the SST can also be used
to maintain voltage levels to enable fault tolerance [25]. After
the occurrence of faults, the new converter reliability and
mean time to failure can also be estimated [21]. For these
techniques, it has been assumed that fast fault detection and
localization (FDL) schemes have been implemented so that
the proposed software and hardware fault-tolerance schemes
can be activated rapidly.
In a review of fault diagnosis and protection schemes for
IGBTs in power converters, it has been shown that 38% of
faults in power converters are caused by failures in semi-
conductor devices [26]. These faults can be broadly divided
into two types: short-circuit and open-circuit switch faults.
In terms of severity, short-circuit switch faults are fast-acting
and destructive, as it commonly damages the complementary
switch when the fault occurs [27]. As they are fast-acting,
short-circuit fault detection and protection circuitry typically
use hardware solutions, and many gate drivers available in
the market include short-circuit protection mechanisms built-
in [28].
On the other hand, an open-circuit switch fault is typically
caused by failure in the gate drive circuit or wire bond lift-
off in the switch module [29]. These faults do not incur any
damage immediately, but results in distortions in the source
current and multilevel voltage waveforms. However, these
distortions can then lead to cascading failures in the converter
due to power imbalances and high charging currents if no
action is taken to isolate the faulty switch or module.
A general overview of open-circuit fault detection and lo-
calization techniques for CHB multilevel converters is detailed
in [30], and a technique based on the zero-voltage switching
states and the slope of the AC current is proposed [31].
However, this method is slow, as it requires three fundamental
cycles to detect and localize the faulty switch. There have
been voltage-based methods proposed in which the terminal
voltage vCHB [32] or H-bridge cell DC voltages vHi [33] are
measured and compared against the applied switch state, di ,
but these require the installation of additional voltage sensors,
increasing the cost. The use of historical mean voltage values
has also been proposed [34], but can only localize the switch
pair and not the exact faulty switch with the measurement of
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vCHB . To localize the exact faulty switch using the normalized
mean values, additional voltage sensors for vHi measurements
are required [35]. A state estimator and current residual-based
fault diagnosis technique for the CHB multilevel converter has
been proposed [36], however, it does not account for dynamic
conditions. The use of principal component analysis with the
help of a multiclass relevance vector machine is proposed
[37], but this method also requires the measurements of vHi .
Artificial neural networks has also been used in conjunction
with the vCHB measurement, but is unable to localize the
exact faulty switch [38].
As the use of MPC techniques become more prevalent, there
has been recent interest in incorporating fault detection algo-
rithms into the MPC control loop. The main advantage of this
integration is that the MPC algorithm already predicts the fu-
ture states in its optimization process, which can then be used
to compare against the actual state for fault detection without
the need for extra additional sensors. Fault detection with MPC
has been presented for modular multilevel converters [39]
and matrix converters [40]. However, for the CHB multilevel
converter, each H-bridge cell always has two switches turned
on simultaneously for all switch states that complicates fault
localization; hence the previously proposed methods cannot be
readily adapted for use in the CHB multilevel converter.
This manuscript proposes an FCS-MPC-based technique to
perform fast FDL of an open-circuit switch fault in the CHB
multilevel converters. The proposed scheme does not require
installation of additional sensors, and only requires the AC
current measurement, which typically is already available for
control purposes, to detect and localize open-circuit switch
fault. The proposed FDL scheme directly utilizes the predic-
tions made by the FCS-MPC controller, and minimal com-
parisons and calculations are performed to detect and localize
the open-circuit switch fault. It is therefore straightforward to
implement the proposed FDL scheme into existing FCS-MPC
controllers for the CHB multilevel converter. This manuscript
is structured as follows: Section II presents a general overview
of MPC for the CHB multilevel converter; Section III details
the various open-circuit switch fault scenarios in the CHB mul-
tilevel converter; Section IV then presents the proposed MPC-
based FDL scheme, which is then validated experimentally in
Section V, and Section VI concludes the manuscript with a
summary of the proposed MPC-based FDL scheme.
II. M ODEL P REDICTIVE C ONTROL FOR CHB M ULTILEVEL
C ONVERTER
A. Model of the CHB Multilevel Converter
Conventional FCS-MPC, for the single-phase (2n + 1)-
level CHB multilevel converter shown in Fig. 1 is used in
this manuscript. This FCS-MPC method is thereafter referred
simply as MPC in the rest of the manuscript for brevity.
For this MPC method, the optimal switch state for the CHB
multilevel converter is found and then applied in each sampling
period. It should be noted that for a (2n + 1)-level CHB
multilevel converter, there exists a finite set of 3n possible
switch states, from which one optimal switch state is applied
during every sampling period. This results in the effective
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Transactions on Power Electronics

TABLE I multilevel converter increases, the corresponding increase in

P OSSIBLE SWITCH STATES FOR A SINGLE H- BRIDGE CELL computational burden can pose an issue. This can be can
be addressed through methods in which the number of iter-
Switch state di S1i S2i S3i S4i Cell voltage vHi State
ations required is minimized through multistep or multistage
+1 1 0 0 1 +Vo,i Active
0U 1 0 1 0 0 Zero
algorithms [42], [43]. It should be noted that the proposed
0L 0 1 0 1 0 Zero
FDL technique only requires if statements to determine fault
−1 0 1 1 0 −Vo,i Active conditions, hence it is not as computationally intensive as
the main MPC control loop. Therefore, the optimization and
reduction of the MPC search space is not considered in
switching frequency of the CHB multilevel converter being this manuscript. Using the receding horizon policy [44], the
lower than the sampling frequency. controller sampling delay is compensated using the prediction
Assuming that the capacitor values in each H-bridge are of states at the time step (k + 2) for (3) and (4). This means
equal, i.e. Co,1 = Co,2 = ... = Co,n = Co , the equations for that the prediction at the time step (k + 1) is first performed
the AC source current, is , and the capacitor DC voltages, vo,i , using the known state of di (k), which was optimized during
in each H-bridge cell are: the previous sampling period. The (k + 2)th prediction is
" n
# subsequently made and the optimal switch state is applied in
dis 1 X the next control interval.
= vs − Rs is − di vo,i (1)
dt Ls i=1
For the CHB multilevel converter, the aforementioned main
control objectives can be fulfilled through the objective func-
dvo,i 1 tion for the CHB multilevel converter:
= [di is − io,i ] (2)
dt Co 2
J =λIs (Is∗ − Is (k + 2))
where i = 1, 2, ..., n for a (2n + 1)-level CHB multilevel n
converter, di = S1i S4i − S2i S3i is the switch state in the ith
X 2
+ λV o (Vo∗ − Vo,i (k + 2))
cell, vs is the AC source voltage and io,i is the load current i=1 (5)
of the i-th H-bridge cell. The filter inductance and parasitic Xn
2
resistance are Ls and Rs , respectively. + λbal (Vo,i (k + 2) − Vo,ave )
With MPC, the model of the CHB in (1) and (2) are used to i=1
predict the values of is and vo,i in the next sampling interval. where λIs , λV o , and λbal are the weighting factors. In this
The differential equations of (1) and (2) are discretized and manuscript, the reference set-point for all CHB cell DC
obtained as (3) and (4): ∗
voltages are assumed to be equal, i.e. vo,1 ∗
= ... = vo,N = vo∗ .
In the objective function, the sum of square of errors is used,
 
Rs Ts Ts
Is (k + 1) = 1 − Is (k) + Vs (k) i.e. 2-norm. This is chosen for stability purposes, as proven in
L Ls
" sn # (3) [45].
Ts X For unity power factor operation, the AC source current, is ,
− di (k)Vo,i (k)
Ls i=1 should be sinusoidal and in-phase with the source voltage, vs .
The magnitude of the AC source current, can be calculated
Ts Ts using energy conservation principles [41], and is reproduced
Vo,i (k + 1) = Vo,i (k) + di (k)Is (k) − Io,i (k) (4)
Co Co below as (6):
where Ts is the sampling period or control interval of the
s
2 2
P P
∗ Vs,pk Vs,pk 2 Vo,i Io,i + Co ∆vo,i
MPC. In the discrete form, Vo,i (k) is the measurement of the Is,pk = ± − (6)
variable Vo,i at the time step, k . 2Rs 4Rs2 Rs
The load current Io,i is obtained using an extended Lu-
B. MPC Design enberger observer, whose derivation is shown in [14]. The
In this manuscript, the method proposed in [14], [41] is reference AC source current, Is∗ , is multiplied with the sine of
used. In this method, there are three main objectives for the the source phase angle, θs , for unity power factor:
control of the CHB multilevel converter: maintaining CHB Is∗ = Is,pk
∗
sin (θs + φs ) (7)
cell DC voltages at the reference voltage level; controlling the
AC source current to be sinusoidal with a specific displace- A leading or lagging phase shift can also be created by
ment power factor, typically unity; and perform DC voltage setting a non-zero value to φs in (7). In this manuscript,
balancing for the H-bridge cells. Equations (3) and (4) are this scenario is not considered and only unity power factor
used to predict the AC current and H-bridge cell DC voltages operation, i.e. φs = 0, is analysed. The weighting factors,
at the time step (k + 1), i.e. Is (k + 1) and Vo,i (k + 1). ΛIs , ΛV o , and Λbal , are included in (5). To account for
Each H-bridge cell has four switch state combinations, i.e. the differences in units, a normalization process as proposed
di ∈ {−1, 0U , 0L , 1}, as listed in Table I. As the zero states, in [46] is performed, which uses the nominal voltages and
0U and 0L , are redundant states, 3n number of iterations are currents of the system.
required to evaluate the cost function for every possible switch ΛIs ΛV o Λbal
state combination. As the number of H-bridge cells in the CHB λIs = ; λV o = ; λbal = (8)
Is,nom Vo,nom Vo,nom

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Fig. 3. MPC control diagram for the CHB multilevel converter with the
proposed fault detection and localization method.
The block diagram in Fig. 3 shows the MPC method im-
plemented in this manuscript with the proposed FDL method.
A secondary model is used in [14] to calculate the required
AC reference current for faster dynamic response. In MPC
methods, there exists a time delay between the sampling of
the measurements and the application of the new switch state.
This can be compensated by adding a prediction step, i.e. at
time step k, the previously selected switch state is used to
predict the converter states at time step (k + 1) using (3)
and (4) with the Is (k) and Io,i (k) measurements. All possible
switch states are enumerated for time step (k + 2) and the
switch state that results in the minimal cost function is then
applied to the CHB converter in the next control interval. This
delay compensation is therefore able to improve the closed-
loop performance without an additional iteration of all possible
switch states. It should be noted that while a simple form of
MPC is implemented in this manuscript, other cost functions,
such as reduced switching frequency [18], can be included.
This does not affect the outcome of the proposed FDL method
as it only relies on the final states selected by MPC.
III. O PEN -C IRCUIT S WITCH FAULT IN H-B RIDGE C ELL
The CHB converter has a modular structure in which
individual H-bridge cells are connected in series. Due to this,
the CHB converter voltage, vCHB , is obtained asP the sum
of
P individual H-bridge cell voltages, i.e. vCHB = vHi =
di vo,i . Therefore, analysis of the open-circuit fault in the
CHB converter can be simplified by first analysing the open-
circuit fault in a single H-bridge cell. As such, the subscript
i to indicate the cell number is omitted for the analysis in
this section. The state of each H-bridge cell is of the form
d ∈ {−1, 0U , 0L , +1}, with the terminal voltage of each H-
bridge cell vH being a function of the H-bridge cell switch
state and its DC voltage, vH = d · vo . It should be noted
that there exists two possible zero states for the H-bridge cell,
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(a) (b)
Fig. 4. Example of an open-circuit switch fault during active switch state:
The current path and H-bridge cell voltage (a) in normal operation and (b)
open-circuit fault in switch S4 with the applied state d = +1. The shaded
switch numbers S1 and S4 indicate they are turned on.
(a) (b)
Fig. 5. Example of an open-circuit switch fault during zero switch state:
The current path and H-bridge cell voltage (a) in normal operation and (b)
open-circuit fault in switch S1 with the applied state d = 0U . The shaded
switch numbers S1 and S3 indicate they are turned on.
(a) (b)
Fig. 6. Example of an undetectable open-circuit switch fault: The current path
and H-bridge cell voltage in normal operation with applied states (a) d = 1
and (b) with open-circuit fault in switch S3 . The shaded switch numbers S2
and S3 indicate they are turned on.
0U and 0L ; 0U being the case in which both top switches
S1 and S3 are turned on simultaneously, and 0L being the
case in which both bottom switches S2 and S4 are turned
on simultaneously. There are three open-circuit fault scenarios
that can occur in a H-bridge cell during normal operation:
1) Detectable fault during an active switch state, i.e. d ∈
{−1, +1};
2) Detectable fault during a zero state, i.e. d ∈ {0U , 0L };
and
3) Undetectable fault.
In the following analysis, a single open-circuit switch fault
is assumed for ease of analysis. Likewise, the same logic can
be easily extended for cases in which multiple open-circuit
switch faults occur.
Fig. 4(a) shows the application of an active switch state,
d = +1, during the normal operation of a single H-bridge
cell with a negative current direction, is < 0. In this mode,
the voltage that appears across the H-bridge cell is the DC
voltage, vH = d · vo = +vo . In the event of an open-circuit
fault in the switch S4 , as shown in Fig. 4(b), the current path
of is has to flow through the anti-parallel diode of the switch
S3 , resulting in a zero voltage appearing across the H-bridge
cell terminals. The apparent switch state then becomes 0U .
It should be noted that if an open-circuit fault were to occur
in the switch S1 instead, the voltage across the H-bridge cell
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TABLE II
D ETECTABLE FAULT SCENARIOS FOR SINGLE H- BRIDGE CELL

Switch State d Expected Voltage v̂H Faulty Switch Sj Current Direction Actual Voltage vH Error εvH = |v̂H − vH |
S1 0 vo
+1 +vo is < 0
S4 0 vo
S1 is <0 −vo vo
0U 0
S3 is >0 +vo vo
S2 is >0 +vo vo
0L 0
S4 is <0 −vo vo
S2 0 vo
−1 −vo is > 0
S3 0 vo

terminals, vH , will also be zero as the current conducts through as given by (3) and (4), are then compared with the measured
S4 and the anti-parallel diode of S2 . However, the new current values. This can then be used to detect and localize open-
path of is is through the anti-parallel diode of the switch S2 , circuit switch faults in the CHB converter.
with the apparent switch state being 0L . Fig. 7 shows the overall methodology of the proposed
Fig. 5(a) shows the application of a zero switch state, d = FDL scheme with the fault detection and fault localization
0U , during normal operation with a negative current direction, subroutines. The fault detection subroutine is continuously
is < 0. Hence, zero voltage appears across the H-bridge cell running during the operation of the CHB multilevel converter
terminals, i.e. vH = d · vo = 0. Fig. 5(b) shows an open- until a fault is detected, after which the fault localization
circuit fault occurring in the switch S1 , which then forces the subroutine is run to localize the faulty switch(es).
current to flow through the anti-parallel diode of the switch
S2 instead. The voltage that now appears across the H-bridge
cell terminals is −vo . A. Fault Detection
Fig. 6(a) shows the application of an active switch state,
There are two methods by which a fault can be detected
d = −1 during the normal operation of a single H-bridge cell.
in the CHB converter, based on the predictions made in (3)
It can be observed that despite the switch S3 being turned on,
and (4) for the MPC technique. As previously concluded,
the actual current path of is flows through the anti-parallel
the occurance of an open-circuit switch fault in an H-bridge
diode of S3 . Therefore, when an open-circuit fault occurs
cell results a discrepency in the expected and actual terminal
in the switch S3 , the operation of the H-bridge cell remains
voltages, i.e. εvH = vo . For the CHB converter, the same result
unaffected, with the current flow continuing through the anti-
occurs for an open-circuit switch fault, i.e. εvCHB = εvH = vo ,
parallel diode of S3 and the terminal voltage is maintained at
for a single-switch fault.
vH = −vo .
For MPC in the CHB converter, the prediction of the
It can therefore be concluded from the previous analysis that
source current as shown in (3) is dependent on the measured
for a fault to be detected, the current path of is in the original
source current, Is (k), the measured source voltage, Vs (k),
operation mode must flow through the body of the switch
the measured DC voltages of the H-bridge cells, Vo,i (k), and
itself, and not through its anti-parallel diode. A summary of
the switch function of the individual H-bridge cells, di (k).
all open-circuit fault possibilities is presented in Table II. It
As previously analyzed, an open-circuit fault in any of the
can be observed that only two open-circuit switch faults can
switches in the CHB converter results in (9). In the context of
be detected for each switch state, and the direction of the AC
(3), the variable that is affected is the switch function, di (k).
source current, is , must be such that it flows through the body
This leads to the switch function mismatch:
of the faulty switch. Assuming no conduction losses, the error  
between expected and actual H-bridge cell terminal voltage, εdi = dˆi (k) − di (k) = 1

εvH , when an open-circuit fault occurs is:
εvH = |v̂H − vH | = vo
where v̂H is the expected H-bridge cell terminal voltage, vH
is the actual H-bridge cell terminal voltage, and vo is the DC
voltage of the H-bridge cell. This phenomenon is used as the
basis of the FDL scheme proposed in this paper.
IV. MPC- BASED FAULT D ETECTION AND L OCALIZATION
The basic principle of MPC is to predict the future states of
the plant so that the optimal switch state can then be selected
(10)
(9) where dˆi (k) is the expected switch function that is applied,
and di (k) is the actual switch function that is applied during
open-circuit fault conditions. The occurence of an open-circuit
fault does not result in a change in the switch function that is
more than one level, i.e. di (k) cannot change from +1 to −1,
or vice versa.
As deduced in (10), only the third term in (3) varies during
an open-circuit fault as it contains the di (k) term. Therefore,
the error between the predicted and actual source current can
be derived as:
and applied in the future control interval. The predicted AC   Ts
εIs = Iˆs (k + 1) − Is (k + 1) = Vo,i (k) (11)
 
source current and/or the predicted H-bridge cell DC voltages, Ls

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MPC Prediction, Operation and Measurement

FDL Subroutine
Selection

Start Fault Detection Start Fault Localization

𝑇𝑠 False (Normal) False (Normal)

𝑇𝑠
𝜀𝐼𝑠 ≥ 𝑉𝑜,𝑖 (𝑘) 𝜀𝐼𝑠 ≥ 𝑉𝑜,𝑖 (𝑘)
𝐿𝑠 𝐿𝑠

True (Faulty) True (Faulty)

True
𝑆𝑗,𝑖  conducting

Increase 𝑘𝑐𝑜𝑢𝑛𝑡 Decrease 𝑘𝑐𝑜𝑢𝑛𝑡

Update Fault Localization Matrix Γ𝑓𝑎𝑢𝑙𝑡

False

False
𝑘𝑐𝑜𝑢𝑛𝑡 ≥ 𝑘𝑑𝑒𝑡

False
True (Fault Detected) {𝛾𝑗,𝑖 ∈ Γ𝑓𝑎𝑢𝑙𝑡 } == 1

End
Generate Fault Localization Matrix Γ𝑓𝑎𝑢𝑙𝑡 True End

Start Fault Localization Fault Detected and Localized

Fig. 7. Flowchart for the proposed FDL scheme with the fault detection (shaded in red) and fault localization (shaded in orange) subroutines.

Similarly, the error between the predicted and actual DC respective rated values:
voltage in each H-bridge cell can be derived using (10) in (4): Ts Vo,i (k)
ε̃Is = (13)
Ls Is,rated
  Ts
εVo,i = V̂o,i (k + 1) − Vo,i (k + 1) = Is (k) (12)
Co
These two error signals derived from the MPC predictions,
εIs and εVo,i can be used to detect the presence of an
open-circuit switch fault in the CHB converter. However,
considerations have to be made to take into account the
measurement noise that arises during real operation of the
converter. Therefore, the error signal that has the higher signal-
to-noise ratio (SNR) is selected for the proposed FDL scheme.
This can be determined by normalizing the two error signals
and comparing their magnitudes. The normalized errors, ε̃Is
and ε̃Vo,i , are obtained by dividing (11) and (12) with their
Ts Is (k)
ε̃Vo,i = (14)
Co Vo,i,rated
In a typical distribution network, the voltage values are
orders of magnitude higher than the current values, due to
the need to reduce i2 R conduction losses. Therefore, the
value of ε̃Is will typically result in a higher value, as its
numerator is the voltage value and the denominator is the
rated current, while ε̃Vo,i is the inverse of that. Using the
hardware parameters listed in Table III as an example, the
absolute values of the error signals can be approximated to
be εIs = 0.8 and εVo,i = 0.12 during operation at rated
conditions. If normalized to their respective rated values, the

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relationship is met:
Ts
εIs ≥
Vo,i (k) (15)
Ls
This is assuming that the DC voltages in the individual H-
bridge cells converge to the same reference value in steady-
state conditions, i.e. vo,1 = vo,2 = ... = vo,n . It is also as-
sumed that the ADC sampling and dead-time delays comprise
an insignificant amount of time compared to the sampling
interval and therefore neglected. For the relation of (15) to be
true, the ADC, voltage and current sensors must also be able
measure the AC source current is and CHB cell DC voltage
vo,i accurately. These assumptions are normally true for MPC
methods. However, random and uncontrollable measurement
noise, margins of error between the expected and actual values
of Ls , or a combination of both may fulfill the relationship
Fig. 8. Error magnitudes of εIs and εVo in percentage terms of their
respective rated values for the experimental setup. in (15) even during healthy operating conditions. To prevent
false triggering, consecutive fault events should be detected
before confirming the fault occurrence. A fault counter, kcount
TABLE III
is used to count the number of consecutive fault events. A
H ARDWARE P ROTOTYPE PARAMETERS FOR CHB M ULTILEVEL threshold, kdet , is to be set to a value so that false positives
C ONVERTER of the proposed fault detection scheme can be avoided.
Parameter Value
B. Fault Localization
Number of CHB cells 2
AC rms voltage Vs 110 V While the relation in (15) is able to detect the presence of an
AC frequency fs 50 Hz open-circuit switch fault in the CHB converter, there is a need
Filter inductor Ls 5 mH for further refinements to localize the exact switch and the
Leakage resistance Rs 0.1 Ω H-bridge cell that has suffered the fault so that redundancy
DC capacitor Co 1.98 mF measures can be activated and the affected H-bridge cell is
Sampling time Ts 50 µs isolated.
Nominal AC current Is,nom 5A This can be achieved by using a fault localization variable
Nominal DC cell voltage Vo,nom 80 V for each of the switches in the CHB multilevel converter,
AC current weighting factor ΛIs 1 i.e. switch Sj,i has an associated fault localization variable
DC voltage weighting factor ΛV o 1
γj,i . These fault localization variables are then stored in a
Voltage balancing weighting factor Λbal 0.5
fault localization matrix Γf ault of size n × 4. It should be
Fault detection threshold kdet 3
noted that each variable in Γf ault is independently linked to a
Difference constant δf ault 0.33
single switch in the converter; in the event of multiple faults,
multiple fault localization variables, γj,i , will be incremented
independently until they indicate the localization of a fault in
their respective switch.
error signals ε̃Is and ε̃Vo,i constitutes 16% and 0.16% of the Once a fault has been detected by the fault detection
rated values, respectively. For load variations from no-load to subroutine, the fault localization routine is initiated. The fault
full-load and DC voltage variation of ±10%, the normalized localization matrix, Γf ault , is:
magnitudes of ε̃Is and ε̃Vo,i are shown in Fig. 8. The error
magnitude of ε̃Is is always higher than ε̃Vo,i from low-load to S1 S2 S3 S4
γ γ21 γ31 γ41  Cell 1
full-load conditions, with a minimum value of 12% occurring 11
at the lowest DC voltage and no-load conditions. This is still  γ12 γ22 γ32 γ42  Cell 2
Γf ault = . .. .. ..  (16)
significantly higher than the sub-1% error values obtained from  .
. . . .

ε̃Vo,i . As shown in Fig. 8, εIs has higher SNR due to its γ1n γ2n γ3n γ4n Cell n
higher normalized value for all operating conditions, hence it
is less prone to false error signals and is therefore selected
where γj,i is the fault localization variable for switch j of cell
for the proposed FDL scheme. Also, as the value of ε̃Is is
i in the CHB converter.
also dependent on Ts , its value increases when the sampling
To localize the fault(s), the possible scenarios are first
frequency is low, thus improving the SNR. It should be noted
examined, as summarized in Fig. 9. There are six scenarios
that the non-normalized error signal εIs is used in the proposed
of fault localization, in which two scenarios (Scenarios 1–2)
FDL method to minimize the number of computation steps.
require no updates to each fault localization variable γj,i in the
To detect the presence of an open-circuit switch fault using fault localization matrix and four scenarios (Scenarios 3–6) do
εIs , a fault is determined to have occurred if the following require updates.

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Fig. 9. Fault localization scenarios for updates to the fault localization
variable, γj,i .
Scenario 1: No fault is detected and the switch Sj,i is not
conducting as it is turned off – not possible to deduce the
fault location hence no update to the corresponding γj,i .
Scenario 2: No fault is detected and the switch Sj,i is not
conducting although it is turned on – not possible to deduce
the fault location hence no update to the corresponding γj,i .
Scenario 3: No fault is detected and the switch Sj,i is
conducting – not likely that the fault occurred in Sj,i hence
the corresponding γj,i is decreased.
Scenario 4: Fault is detected but the switch Sj,i is not
conducting as it is turned off – not likely that the fault occurred
in Sj,i hence the corresponding γj,i is decreased.
Scenario 5: Fault is detected but the switch Sj,i is not
conducting although it is turned on – not likely that the fault
occurred in Sj,i hence the corresponding γj,i is decreased.
Scenario 6: Fault is detected and the switch Sj,i is turned on
and conducting – likely that the fault occurred in Sj,i hence
the corresponding γj,i is increased.
In operating conditions, several switches may be turned
on when a fault is detected; however, it is incorrect to then
surmise that they are all faulty. Also, in real-world conditions,
the presence of measurement noise may lead to incorrect
conclusions. As summarized in Fig. 9, the proposed method
therefore uses the fault localization variable, γj,i , which in-
creased or decreased depending on the identified scenario. The
update of the fault localization matrix Γf ault in Fig. 7 refers
to the update of each γj,i for their respective switch Sj,i based
on the scenarios in Fig. 9. A fault is localized in switch Sj,i
only when the corresponding γj,i == 1.
In the proposed method, the magnitude of the incre-
ment/decrement to each γj,i is defined as the difference
constant δf ault . The saturation limit of γj,i is defined as 1,
which leads to the requirement of 0 < δf ault ≤ 1. The
higher the value of δf ault , the faster the value of γj,i saturates.
The selection of δf ault therefore has to take into account the
presence of measurement noise and tuned to a value in which
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(a) (b)
Fig. 10. Fault localization process for the proposed FDL scheme after fault
detection with (a) confirmed fault localization and (b) no fault localization in
switch Sj,i .
false fault detections and localizations do not occur.
The proposed fault localization method is shown by example
in Fig. 10. As the CHB multilevel converter operates, different
switch states are selected for different sampling intervals.
When an open-circuit switch fault occurs, there exists the pos-
sibility of Scenario 6 being identified for some switches (either
because they are the faulty switch, or they are conducting at
the same time as the faulty switch). For the faulty switch, only
Scenarios 1, 2, and 6 are possible; hence γj,i can only remain
constant or increase by δf ault , as shown in Fig. 10(a). For
the non-faulty switch, all Scenarios 1–6 are possible; hence
γj,i can increase or decrease by δf ault , as shown in Fig.
10(b). When a fault occurs, the expected behaviour of γj,i is
shown in Fig. 10(a), while γj,i for all other non-faulty switches
should resemble Fig. 10(b). For multiple open-circuit switch
faults, the same fault localization method applies – the fault
localization variable γj,i for each of the faulty switches will
resemble Fig. 10(a), although they may saturate at different
intervals.
It can be deduced from Fig. 10 that fault localization can
occur with a higher sampling frequency, as the rate at which
the current is experiences transitions will increase. However,
it should be noted the change in current magnitude between
sampling periods will decrease due to the decrease in Ts . This
reduces the SNR of the current is , which leads to a poorer
tolerance to noise for the FDL scheme. Thus, the sampling
frequency is chosen appropriately.
Therefore, it is straightforward to tune the sensitivity and
speed of the proposed fault localization scheme by changing
the value of δf ault . A higher value of δf ault results in faster
fault localization, but may be less accurate. Conversely, a lower
value of δf ault is slower, but has a higher degree of accuracy.
An optimized choice would be appropriate.
V. E XPERIMENTAL R ESULTS
The proposed FDL scheme is validated experimentally using
the experimental setup shown in Fig. 11 with the parameters
in Table III, with the exception of Fig. 16, in which 30%
of the nominal load conditions is used for low-load tests.
The switching devices are CREE C2M0080120D 1200 V SiC
MOSFETS with C4D20120D SiC anti-parallel diodes, and are
controlled using dSPACE MicroLabBox to implement both
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Fig. 13. Operation of the CHB converter during normal operation with no
triggered faults.

Fig. 11. Experimental setup for the experimental validation of the proposed
FDL scheme with (1) CHB multilevel inverter hardware, (2) dSPACE Micro-
LabBox, (3) computer, and (4) oscilloscopes.

(a)

Fig. 12. Linear change in detection time tdet with increasing detection
threshold kdet .

the conventional MPC and the proposed FDL scheme. The

proposed FDL technique is demonstrated with power flow
from a single-phase AC source to individual resistive loads
on each H-bridge cell. However, the power flow is irrelevant
in the proposed FDL technique; as long as the predicted value
of Is can be obtained, the FDL technique will function as
described. A number of different open-circuit fault scenarios
are emulated by disabling the gate signal to the switch on
which the open-circuit fault is to be emulated. (b)
In the experimental setup, it is found that the fault detection Fig. 14. Operation of the proposed FDL scheme with single open-circuit
threshold, kdet , provides accurate detection of faults when set faults triggered in (a) S11 and (b) S22 .
to a value of 3. Due to measurement noise and Ls model
inaccuracy of up to ±10%, there may be occasions in which
false positives may occur. As can be seen in the blue fault i.e. kdet = 3. With higher values of kdet , the detection time
detection traces shown in Fig. 14 to 17, the measurement tdet increases linearly, as shown in Fig. 12. In the local-
noise profile in the experimental setup is such that single false ization process of the proposed FDL scheme, the difference
positives occur occasionally, two consecutive false positives constant, δf ault , provides good performance when set to a
occur rarely, while three consecutive false positives do not value between 0.2 and 0.4. As previously noted, a higher
occur. Hence, it has been decided that a fault is said to be value provides faster localization, while a lower value is more
detected after three consecutive detections in this manuscript, accurate in localizing the faulty switch. A final value of

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(a)
(a)

(b)
(b)
Fig. 16. Operation of the proposed FDL scheme with open-circuit faults
Fig. 15. Operation of the proposed FDL scheme with two simultaneous open- triggered in (a) S11 only, and (b) both S21 and S32 simultaneously at low-
circuit faults triggered in (a) S11 and S31 , and (b) S21 and S32 respectively. load conditions.

0.33 is selected for δf ault so that the proposed FDL scheme
provides the best performance for the experimental setup while
maintaining its accuracy in fault localization.
As previously concluded in Table II, open-circuit faults in
S1 and S4 can only be detected when is < 0, while open-
circuit faults in S2 and S3 can only be detected when is > 0.
For the ease of comparison and analysis, the open-circuit faults
in the experimental validation are triggered at the beginning
of positive half cycle of the source current is , i.e. θs = 0. As a
result, the time taken to fully detect and identify the fault can
be easily compared for different cases. The results in Fig. 14–
17 demonstrate the validity and speed of the proposed FDL
method for various scenarios. In these figures, the individual
traces are: AC current error εIs (red), threshold for fault
event detection (Ts /Ls )Vo,i (orange), AC current (green), AC
voltage (yellow), fault trigger signal (pink), fault event counter
kcount (blue), and 8 logic signals indicating the localized faults
(dark blue). Each logic signal is used to indicate fault status
of a single switch, i.e. from top to bottom: S11 , S21 , ..., S12 ,
... S42 .
In Fig 14(a) and (b), single open-switch faults are triggered
in S11 (detectable in negative half cycle) and S22 (detectable in
positive half cycle) respectively. For the fault in S11 , the pro-
posed FDL method detects the fault in 10.9 ms, and localizes
the fault correctly an additional 0.55 ms later. Experimental
results with faults triggered in other switches show similar
times for tdet and tloc,Sji , and are not shown for brevity. This
means that the detection time, tdet , is typically less than 2 ms,
while the localization time, tloc,Sji , takes an additional 1 ms
or less.
The proposed FDL method can also detect and localize
multiple simultaneous open-switch faults, as shown in Fig. 15.
In Fig. 15(a), simultaneous open-switch faults are triggered
in S11 and S31 , i.e. two faults in the same H-bridge cell.
Similar to the cases in which a single open-switch fault
occurs, the detection time is 1 ms. As S11 and S31 are
detectable in different half cycles, their individual localization
times, tloc,S11 and tloc,S31 , differ by approximately half a
fundamental period, i.e. 10 ms. Fig. 15(b) demonstrates a
case in which two open-switch faults occur simultaneously
in different H-bridge cells, where faults are triggered in S21
and S32 at the same time. Regardless of which H-bridge cell
they reside, faults in both S21 and S32 are detectable in the
positive half cycle. Hence, the proposed FDL method functions
in a similar manner to the single open-circuit switch fault case
shown in Fig. 14(b), in which tdet ≈ 1 ms, and tloc,Sji ≈ 1

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(a)
(b)
Fig. 17. Demonstration of robustness of proposed FDL scheme with (a) step-
changes of vo,i between 80V and 90V, and (b) step-changes of load between
low-load (30%) and full-load (100%) conditions.
ms.
Fig. 16 demonstrates the performance of the proposed
FDL method during low load conditions, which leads to the
magnitude of the AC current, is , being low. In this case, the
load is reduced to 30% of the nominal value. Open-switch
faults are then triggered in S11 only, and in both S21 and S32
simultaneously, as shown in Fig. 16(a) and (b) respectively.
Comparing the single-switch fault scenario for the same switch
in Fig. 14(a) and 16(a), it can be observed that both tdet and
tloc,Sji has increased. The same two simultaneous open-circuit
fault scenario from Fig. 15(b) is repeated in Fig. 16(b), albeit
at low-load conditions. It can also be observed that the fault
detection and localization times have also increased at low
load conditions. For both cases, it should be noted that the
proposed method is still able to complete the FDL process
within one fundamental cycle.
The accuracy of any FDL method is of key importance to
prevent false positives or negatives. Overcoming the issue of
false negatives is shown in Fig. 16, when the AC current is
has low values. The injected fault is still able to be detected
and localized quickly and accurately by the proposed method.
On the other hand, the issue of false positives can arise due
to changes in operating conditions. As the proposed FDL
method primarily relies on the H-bridge cell voltage, vo,i ,
and AC current, is , for fault calculations, any unexpected
changes in these values may result in false fault detection
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and/or localization. In Fig. 17, the DC voltages and load
power undergo step changes. In Fig. 17(a), where the DC
voltages stepped up/down, the AC current is increase/decrease
correspondingly. In Fig. 17(b), where the load power is varied,
the DC voltages are maintained by the MPC controller while
the AC current is varies to account for the load change. In
both cases, although measurement noise occassionally results
in kcount being increased, it does not reach kdet even over
a number of cycles. Hence, it can be seen that the proposed
FDL method does not falsely detect or localized faults, demon-
strating its robustness in the face of dynamically changing
operating conditions.
VI. C ONCLUSIONS
This manuscript proposes an MPC-based FDL method for
the CHB multilevel converter to improve its reliability. This
scheme only utilizes the inbuilt AC current measurement, and
does not require additional voltage or current sensors, unlike
other FDL schemes proposed in literature. Single or multiple
open-circuit switch faults can be detected by comparing the
predicted AC source current from the MPC controller with
the actual measurement value. Detected fault(s) can then be
further localized through the use of a fault localization matrix
that stores the historical fault detections so that the faulty
switch can be localized exactly. The proposed FDL scheme
is shown to be able to detect both single and multiple open-
circuit switch faults within a fundamental period at both rated
and low load conditions. The proposed FDL scheme has also
been shown to be immune to system dynamics such as load
changes or voltage reference variations. Experimental results
have validated the performance of the proposed FDL scheme
in a 5-level CHB multilevel converter.
ACKNOWLEDGMENT
This research is supported by the National Research Foun-
dation, Prime Minister’s Office, Singapore under its study on
Solid State Transformer for Grid 2.0.
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Transactions on Power Electronics

Merlin Chai Merlin Chai (M’15) received the B.E.

degree in electrical and electronic engineering from
the University of Canterbury, Christchurch, New
Zealand, in 2010 and the Ph.D. degree from the
University of New South Wales, Sydney, Australia,
in 2015.
He was a Research Fellow at the National University
of Singapore from 2015 to 2019. Since 2019, he
has been a Senior R&D Engineer at Lite-On Sin-
gapore, designing high-efficiency and high-power-
density power supplies. His current research interest
includes solid-state transformers, LLC resonant converters, matrix converters,
energy storage integration in the utility grid, with classical control methods
and model predictive control.

Naga Brahmendra Yadav Gorla Naga Brahmendra

Yadav Gorla (M19) received the B.Tech. degree in
electrical and electronics engineering from Acharya
Nagarjuna University, India, in 2010, the M.S. de-
gree (by research) in electrical engineering from
the Indian Institute of Technology Madras, Chennai,
India, in 2013, and the Ph.D. degree in electrical en-
gineering from the National University of Singapore,
Singapore, in 2019.
He was with the Electrical and Electronics Depart-
ment, Singapore Polytechnic as a Research Engineer
between October 2013 and December 2015. Since April 2019, he has been
a Research Fellow with the Sembcorp-NUS Corporate Laboratory, National
University of Singapore, Singapore. His research interest include power
quality improvements in grid-connected inverters and rectifiers, fault detection
and localization in multilevel and multiphase converters, and fault tolerance
and resilience in grid-connected systems.

Sanjib Kumar Panda Sanjib Kumar Panda (S’86-

M’91-SM’01) received the B.Eng. degree from the
South Gujarat University, Surat, India, in 1983, the
M.Tech. degree from the Indian Institute of Tech-
nology, Banaras Hindu University, Varanasi, India,
in 1987, and the Ph.D. degree from the University
of Cambridge, Cambridge, U.K., in 1991, all in
electrical engineering.
Since 1992, he has been holding a Faculty Position
in the Department of Electrical and Computer En-
gineering, National University of Singapore, Singa-
pore, and currently serving as an Associate Professor and the Director of the
Power & Energy Research Area. He has published more than 200 peer re-
viewed research papers, coauthored one book and contributed to several book
chapters, and six patents. His research interests include high-performance
control of motor drives and power electronic converters, condition monitoring
and condition based maintenance, building energy efficiency, etc.
Dr. Panda received the Cambridge-Nehru Scholarship and M. T. Mayer
Graduate Scholarship during his Ph.D. study (1987-1991). He is serving
as an Associate Editor of several IEEE Transactions and the Editor of the
Journal of Power Electronics, South Korea. He has served in various capacities
for the two key conferences IEEE Power Electronics and Drive Systems
Conference and IEEE International Conference on Sustainable Energy Tech-
nologies Conference series organized and managed by the IEEE Joint Industry
Applications Society/ Power Electronics Society (PELS) Society Chapter,
Singapore Section. He has served the IEEE Section Congress 2014 as a
member of the Program Committee. He is serving as the IEEE R-10 Asia
Pacific Liaison Officer for the IEEE PELS. He has received the IEEE Third
Millennium Medal, the IEEE Singapore Section Outstanding Volunteer Award
in 2010, and the IEEE Region-10 Outstanding Volunteer Award in 2014.

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Authorized licensed use limited to: University College London. Downloaded on May 24,2020 at 12:24:14 UTC from IEEE Xplore. Restrictions apply.