Chapter 2 Digital Components CA-401-402-2

Computer Architecture
Fundamentals of Computer Architecture

(From here session 3)
Amir Mahdi Hosseini Monazzah

Room 332,
School of Computer Engineering,
Iran University of Science and Technology,
Tehran, Iran.
monazzah@iust.ac.ir
Spring 2023
*Parts of slides are adopted from prof. David Brooks lectures, Department of Electrical Engineering and Computer Science, Harvard University
Amir Mahdi Hosseini Monazzah – IUST

Outline
Instruction Set Architecture (ISA)
Definition
Different computer architectures
Basic (Mano’s) computer elements
Instruction codes
Registers
Bus
Computer instruction
Timing and control
Instruction cycle
CISC vs. RISC
Classification
CISC architecture examples
Comparison
Destiny
A simple processor prototype
Patterson execution engine
MIPS/RISC V
Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 2

Instruction Set Architecture (ISA) Definition
Instruction Set Architecture (ISA)
“Instruction Set Architecture is the structure of a

computer that a machine language programmer (or a
compiler) must understand to write a correct (timing
independent) program for that machine.”
IBM, Introducing the IBM 360 (1964)
The ISA defines:
Operations that the processor can execute
Data Transfer mechanisms + how to access data
Control Mechanisms (branch, jump, etc)
“Contract” between programmer/compiler + HW
Instruction Set Architecture (ISA) Different computer architectures
Classifying ISAs
The type of internal storage: the most basic

differentiation of different ISAs in a processor
The major choices are
Stack
An accumulator
A set of registers
Operands may be named explicitly or implicitly
The general-purpose register architectures have only
explicit operands
• Either registers or memory locations

Classifying ISAs

Stack
Architectures with implicit “stack”

Acts as source(s) and/or destination, TOS is implicit
Push and Pop operations have 1 explicit operand
Example: C = A + B
Push A // S[++TOS] = Mem[A]
Push B // S[++TOS] = Mem[B]
Add // Tem1 = S[TOS--], Tem2 = S[TOS--] , S[++TOS] =
Tem1 + Tem2
Pop C // Mem[C] = S[TOS--]
x86 FP uses stack (complicates pipelining)
Accumulator
Architectures with one implicit register

Acts as source and/or destination
One other source explicit
Example: C = A + B
Load A // (Acc)umulator <= A
Add B // Acc <= Acc + B
Store C // C <= Acc
Accumulator implicit, bottleneck?
x86 uses accumulator concepts for integer

Register
Most common approach

Fast, temporary storage (small)
Explicit operands (register IDs)
Example: C = A + B
Register-memory load/store
• Load R1, A Load R1, A
• Add R3, R1, B Load R2, B
• Store R3, C Add R3, R1, R2
• Store R3, C Register-memory computers
IBM 360,
All RISC ISAs are load/store Intel x86,
Motorolla 68K

Common addressing modes for recent processors

Basic (Mano’s) computer elements Instruction codes
Negotiation with computers?

The user of a computer can control the process by means of a program
A program is a set of instructions that specify the operations, operand, the
sequence (control)
A instruction is a binary code that specifies a sequence of microoperations
Instruction codes together with data are stored in memory (= stored program
concept)
Instruction The computer reads each instruction from memory and places it in a control register. The
Cycle control then interprets the binary code of the instruction and proceeds to execute it by issuing a
sequence of microoperations.
Instruction code
A group of bits that instruct the computer to perform a specific operation
It is usually divided into parts
• Operation code:
– The most basic part of an instruction code
– A group of bits that define such operations as add, subtract, multiply, shift, and complement (bit 12-15 : 24 = 16
distinct operations)
• Address:
– Identifies the place(es) that is (are) affected by the operation conde Instruction Format
15 12 11 0
Op. Code Address

Negotiation with computers?

Stored program (accumulator) organization. 5-1
The simplest way to organize a computer
• One processor register: AC (Accumulator)
– The operation is performed with the memory operand and
the content of AC
• Instruction code format with two parts: Op. Code +
Address
– Op. Code: specify 16 possible operations (4 bit)
– Address: specify the address of an operand (12 bit)
– If an operation in an instruction code does not need an
operand from memory, the rest of the bits in the instruction
(address field) can be used for other purpose (Therefore, use
more than 16 instructions: Tab. 5-2, total of 25 instructions)
• Memory: 12 bit = 4096 word (Instruction and Data are
stored) Example: Clear AC,
Increment AC,
– Store each instruction code (program) and operand (data) in
16-bit memory word Complement AC, ...

Negotiation with computers? (Up to/from here session 3/4)

Addressing modes
Immediate operand address:
• The second part of an instruction code (address field) specifies an operand
Direct operand address: Fig. 5-2(b)
• The second part of an instruction code specifies the address of an operand
Indirect operand address: Fig. 5-2(c)
I=0 : Direct, • The bits in the second part of the instruction designate an address of a memory
I=1 : Indirect word in which the address of the operand is found (used as pointer)
One bit of the instruction code is used to distinguish between a direct
and an indirect address: Fig. 5-2(a)
Effective address
The operand address in computation-type
instruction or the target address in a branch-type
instruction

Basic (Mano’s) computer elements Registers
The nearest storage to the processors!

List of registers for the basic computer: Tab. 5-1
Basic computer registers and memory: Fig. 5-3
Data Register (DR): hold the operand (data) read from memory (16 bit)
Accumulator Register (AC): general purpose processing register (16 bit)
Instruction Register (IR): hold the instruction read from memory (16 bit)
Temporary Register (TR): hold a temporary data during processing (16 bit)
Address Register (AR): hold a memory address (12 bit)
Program Counter (PC): (12 bit)
• Hold the address of the next instruction to be read from memory after the current
instruction is executed.
• Instruction words are read and executed in sequence unless a branch instruction is
encountered
– A branch instruction calls for a transfer to a nonconsecutive instruction in the program
– The address part of a branch instruction is transferred to PC to become the address of the
next instruction
• To read instruction, memory read cycle is initiated, and PC is incremented by one (next
instruction fetch)
Input Register (INPR): receive an 8-bit character from an input device
Output Register (OUTR): hold an 8-bit character for an output device

Basic (Mano’s) computer elements Bus
Common bus system

A more efficient scheme for
s2
s1 Bus
s0
transferring information in a
Memory unit
7
4096× 16 Address
system with many registers is Write

AR
Read
1
to use a common bus (in Sec. LD INR CLR
4-3) LD INR
PC
CLR
2
The basic computer has eight DR

3
registers, a memory unit, and Adder E

LD INR CLR
a control unit (in Sec. 5-4) and

logic
LD INR
AC
CLR
4
Paths must be provided to INPR
transfer information from one

register to another and LD
IR 5
between memory and TR

6
registers LD
OUTR
INR CLR
Clock
LD
16-bit common bus

Common bus system

s2
The connection of the registers and s1
s0
Bus
memory of the basic computer to a Memory unit

4096× 16 Address
7
common bus system : Fig. 5-4 Write Read
The outputs of seven registers and AR

1
memory are connected to the LD INR CLR
common bus PC 2
The specific output is selected by mux LD INR
DR
CLR
3
(S0, S1, S2) : LD INR CLR
• Memory(7), AR(1), PC(2), DR(3), AC(4),

E
IR(5), TR(6) Adder
and AC 4
• INPR and OUTR are not selected logic
LD INR CLR
because input/output to/from external

device is possible through AC INPR
• When the mux is selected, data is

retrieved from memory or register and IR 5
placed on the bus LD
– When LD (Load Input) is enable, the TR

6
particular register receives the data LD INR CLR
from the bus
OUTR
Clock
LD
16-bit common bus

Common bus system

s2
• Control Input: LD, INC, CLR, Memory unit

s1
s0
Bus
7
Write, Read 4096× 16 Address
Write Read
• Address Register: Separate AR

1
address bus is not required LD INR
PC
CLR
(simultaneous processing of LD INR CLR
DR
address and data by one LD INR CLR
3
bus) Adder
and
E
AC 4
– AC can only read memory

logic
LD INR CLR
via DR (See LDA command INPR
on p. 146)
IR 5
– AC can directly write to LD
memory ( See STA TR

6
LD INR CLR
command on p. 147) OUTR
Clock
LD
16-bit common bus

Common bus system

• Accumulator (AC): 3 types of s2
s1
s0
Bus
input path Memory unit

4096× 16 Address
7
– 1) Register microoperation: Write Read

clear AC, shfit AC,… AR
1
– 2) Data Register: add DR to LD INR CLR
AC, and DR to AC ( The PC 2
result of the operation is LD INR CLR
stored in AC and depending DR

3
on the result, End carry bit LD INR CLR
set/reset), memory READ Adder

and
E
AC 4
(only via DR) logic
LD INR CLR
– 3) INPR: Input data from

external device (No need to INPR
go through Adder & Logic) IR 5

• Note) Two microoperations LD
can be executed at the same TR

6
time LD INR CLR
OUTR
DR  AC : s2 s1s0 = 100(4), DR(load ) LD

Clock
16-bit common bus

AC  DR : DR → Adder & Logic → AC (load )

Basic (Mano’s) computer elements Computer instruction
Types of instructions (Up to/from here session 4/5)

Hex C ode
Three instruction code formats: S ym bol I= 0 I= 1 D escription
AN D 0xxx 8xxx And m em ory w ord to AC
Fig. 5-5 AD D 1xxx 9xxx Add m em ory w ord to AC
Memory-reference instruction LD A 2xxx Axxx Load m em ory w ord to AC
S TA 3xxx B xxx S tore content of AC in m em ory
• Opcode = 000  110 BUN 4xxx C xxx B ranch unconditionally
– I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx BSA 5xxx D xxx B ranch and S ave return address
I=0 : Direct, 15 14 12 11 0 IS Z 6xxx Exxx Increm ent and skip if zero
I=1 : Indirect C LA 7800 C lear AC
I Opcode Address C LE 7400 C lear E
CM S 7200 C om plem ent AC
CM E 7100 C om plem ent E
Register-reference instruction C IR 7080 C irculate right AC and E
• 7xxx (7800 ~ 7001) : CLA, CMA, …. C IL 7040 C irculate left AC and E
15 14 12 11 0 IN C 7020 Increm ent AC
SPA 7010 S kip next instruction if AC positive
0 1 1 1 Register Operation SNA 7008 S kip next instruction if AC negative
S ZA 7004 S kip next instruction if AC zero
S ZE 7002 S kip next instruction if E is 0
HLT 7001 Halt com puter
Input-Output instruction IN P F800 Input character to AC
• Fxxx (F800 ~ F040) : INP, OUT, ION, O UT F400 O utput character from AC
SKI, …. S KI F200 S kip on input flag
15 14 12 11 0 S KO F100 S kip on output flag
IO N F080 Interrupt O n
1 1 1 1 I/O Operation IO F F040 Interrupt O ff

Basic (Mano’s) computer elements Computer instruction
What is completeness of an instruction set?
Instruction set completeness

Arithmetic, logical, and shift: CMA, INC, ..
Moving information to and from memory and AC: STA, LDA
Program control: BUN, BSA, ISZ
Input/output: INP, OUT
If the computer includes a

sufficient number of instructions in
each of the above categories

Basic (Mano’s) computer elements Timing and control
Clock pulses
A master clock generator controls the timing for all
registers in the basic computer
The clock pulses are applied to all FFs and registers in
system
The clock pulses do not change the state of a register
unless the register is enabled by a control signal
The control signals are generated in the control unit: Fig.
5-6
The control signals provide control inputs for the multiplexers in
the common bus, control inputs in processor registers, and
microoperations for the accumulator

Control unit
Two major types of control organization
Hardwired control
• The control logic is implemented with gates, FFs, decoders, and other
digital circuits
• + Fast operation, - Wiring change (if the design has to be modified)
Microprogrammed control
• The control information is stored in a control memory, and the control
memory is programmed to initiate the required sequence of
microoperations
• + Any required change can be done by updating the microprogram in
control memory, - Slow operation
Will be covered in details later!

Control unit (Up to/from here session 5/6)
Control unit = Control logic gate

Instruction register (IR)
15 14 13 12 11 - 0
+ 3X8 decoder + instruction 3× 8

decoder
Other inputs
7 6 5 4 3 2 1 0
register + timing signal I D0

.
.
D7 . Control
Control
Timing signal = 4X16 decoder +

outputs
logic
gates
T 15
.
4-bit sequence counter

.
T0 .
.
.
.
15 14 1 0
.
.
.
4× 16
decoder
Example) control timing: Fig. 5-7

Increment(INR)
4-bit
Sequence counter is cleared sequence

counter
(SC)
Clear(CLR)
Clock
when D3T4 = 1: D T : SC  0
3 4
• Memory R/W cycle time > Clock

cycle time
– You must add a wait cycle.

RTL statement (at a glance!)
Example) Register Transfer Language (RTL) statement

A transfer of the content of PC into AR if timing signal T0 is
active T : AR  PC
0
• 1) During T0 active, the content of PC is placed onto the bus (S S S ) 2 1 0
• 2) LD (load) input of AR is enabled, the actual transfer occurs at the

next positive transition of the clock (T0 rising edge clock)
• 3) SC (sequence counter) is incremented
0000(T0 ) → 0001(T1 )
T0 : Inactive
T1 : Active

Basic (Mano’s) computer elements Instruction cycle
Instruction engine
Instruction Cycle
1) Instruction fetch from Memory
2) Instruction decode
3) Read effective address (if indirect addressing mode)
4) Instruction execution
5) Go to step 1) : Next Instruction [PC + 1]
Continue
indefinitely
unless HALT
instruction is
encountered

Fetch
Instruction fetch: T0, T1

T0 = 1 T0 : AR  PC
• 1) Place the content of PC

onto the bus by making the
bus selection inputs
S2S1S0=010
• 2) Transfer the content of
the bus to AR by enabling
the LD input of AR

Fetch
Instruction fetch: T0, T1

T1 = 1 T1 : IR  M [ AR], PC  PC + 1
• 1) Enable the read input

memory
• 2) Place the content of
memory onto the bus by
making S2S1S0= 111
• 3) Transfer the content of
the bus to IR by enable the
LD input of IR
• 4) Increment PC by enabling
the INR input of PC

Decode
Instruction decode: T2 Instruction register (IR)

15 14 13 12 11 - 0
T2 : D0 ,...., D7  Decode IR(12 − 14), AR  IR(0 − 11), I  IR(15) 3× 8 Other inputs

decoder
Op.code Address Di/Indirect 7 6 5 4 3 2 1 0
I D0
.
.
D7 . Control
IR(12-14) controls D0 - D7 Control

logic
gates
outputs
outputs! T 15
.
.
T0 .
.
.
.
15 14 1 0
.
.
.
4× 16
decoder
Increment(INR)
4-bit
sequence
Clear(CLR)
counter
(SC)
Clock

Execute (Up to/from here session 6/7)
Instruction execution: T3,

T4, T5, T6 IR (12 − 14)
= 111
D7=1: Register (I=0) D7I’T3 (Execute) Read effective

I/O (I=1) D7IT3 (Execute) Address
D7=0: Memory Ref. Indirect (I=1) D7’IT3( AR  M [AR] )

Direct (I=0) nothing in T3
Register and I/O

instructions are executed
in T3

Execute

T4, T5, T6
Memory reference
• Effective Address is read in
T3.
• Based on the type of
memory command it
requires T4, T5, and T6ig. 5-9

Execute

T4, T5, T6
Flowchart for instruction
cycle (initial configuration)

Execute

T4, T5, T6
Flowchart for instruction
cycle (initial configuration)
Register ref. instruction
• r = D7I’T3 : Common for all reg. inst.
• IR(i) = Bi IR(0 -11)
By not used
• B0 - B11 : 12 Register Ref. address field
Instruction

Memory-reference instructions
IR(12,13,14)
= 111
3X8 D7 : Register or I/O = 1
Decoder D6 - D0 : 7 Memory ref. instruction
D0T4 : DR  M [ AR]
AND to AC D0T5 : AC  AC  DR , SC  0
D1T4 : DR  M [ AR]
ADD to AC D1T5 : AC  AC + DR , E  Cout , SC  0
 M [ AR]
LDA: memory read DD TT :: DR 2 4
AC  DR , SC  0
2 5
Memory r/w cycle time > clock cycle time

You must add a wait cycle
PC = 10 0 BSA 135
STA: memory write D T : M [ AR]  AC, SC  0
3 4 PC = 12 next instruction
BUN: branch unconditionally D T : PC  AR, SC  0 135 12(return address)

4 4
PC = 137
BSA: branch and save return address Subroutine
D5T4 : M [ AR]  PC, AR  AR + 1 1 BUN 135

D5T5 : PC  AR, SC  0
Return address: save return address ( 135 21 )

D T : M [135]  21( PC ), 136( AR)  135 + 1
Subroutine call: Fig. 5-10 5 4
D T : 136( PC )  136( AR), SC  0

5 5
ISZ: increment and skip if zero

D6T4 : DR  M [ AR]
D6T5 : DR  DR + 1
D6T6 : M [ AR]  DR , if ( DR = 0) then ( PC  PC + 1), SC  0

Control flowchart
Flowchart for the 7
memory reference
instruction
• The longest instruction: ISZ
(T6)

Control flowchart
Flowchart for the 7
memory reference
instruction
• Therefore, it can be
implemented as 3 bit
sequence counter (currently
4 bits are prepared for
expansion)

Question

Answer

Input-output and interrupt (Up to/from here session 7/8)

Input-output configuration: Fig. 5-12
Input register (INPR), output register (OUTR)
• These two registers communicate with a communication interface
serially and with the AC in parallel
• Each quantity of information has eight bits of an alphanumeric code
Input flag (FGI), output flag (FGO)
1 : Ready • FGI: set when INPR is ready, clear when INPR is empty
0 : Not ready • FGO: set when operation is completed, clear when output device is in
the process of printing
Input-output instruction: Tab. 5-5
p = D7IT3: Common part Not used for
address
IR(i) = Bi IR(6 -11)
B6 - B11: 6 I/O Instruction

Input-output and interrupt
CPU I/O device

/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop
INPR  new data, FGI  1
AC  INPR, FGI  0
loop: If FGO = 1 goto loop
/* Output */ /* Initially FGO = 1 */
loop: If FGO = 0 goto loop consume OUTR, FGO  1
OUTR  AC, FGO  0

Input-output and interrupt

Program interrupt Instruction cycle =0
R
=1 Interrupt cycle
I/O transfer modes

• 1) Programmed I/O Fetch and decode
instruction
Store return address
in location 0
• 2) Interrupt-initiated I/O M[0] PC
=0
• 3) DMA Execute
instruction
IEN
• 4) IOP (IO Processor) =1

Branch to location 1
PC 1
• Here we consider interrupt-initiated I/O method is used =1
FGI
– If FGI or FGO is 1: Interrupt is enabled! =0
– Maskable Interrupt =1
FGO
IEN
R
0
0
» Interrupt mask is enabled with ION =0
» Interrupt mask is disabled with IOF

R 1
Interrupt cycle. 5-13

During the execute phase, IEN is checked by the control
• IEN = 0: the programmer does not want to use the interrupt, so control continues with the next
instruction cycle
• IEN = 1: the control circuit checks the flag bit, if either flag set to 1, R F/F is set to 1
At the end of the execute phase, control checks the value of R
• R = 0: enter the normal instruction cycle
• R = 1: enter the interrupt cycle

Input-output and interrupt (Up to/from here session 8/9)

Demonstration of the interrupt cycle: Fig. 5-14
The memory location at address 0 as the place for storing the
return address
Whenever an interrupt occurs branch to memory location 1
Always set IEN=0 in interrupt cycle (Therefore, in order to receive
interrupt after running ISR, the ION instruction must be executed
at the end of ISR)
The condition for R = 1 0 256(return address)
T T T ( IEN )( FGI + FGO) : R  1
' ' '
0 1 2 PC = 1 0 BUN 1120
Modified fetch phase for interrupts Interrupt 255

Main Program
Modified fetch and decode Phase Here 256
Save Return RT0 : AR  0, TR  PC

Address (PC) at 0 1120 Interrupt
RT1 : M [ AR]  TR, PC  0
Service Routine
Jump to 1(PC=1) RT2 : PC  PC + 1, IEN  0, R  0, SC  0 1 BUN 0

Complete computer description

The final flowchart of the instruction cycle
The control function and microoperation

CISC vs. RISC Classification
Introduction
RISC (Reduced Instruction Set Computer)

CISC (Complex Instruction Set Computer)
Debate raged from early 80s through 90s
Now it is fairly irrelevant
Despite this Intel (x86 => Itanium) and DEC/Compaq
(VAX => Alpha) have tried to switch
Research in the late 70s/early 80s led to RISC
IBM 801 -- John Cocke – mid 70s
Berkeley RISC-1 (Patterson)
Stanford MIPS (Hennessy)
CISC vs. RISC CISC architecture examples
VAX
32-bit ISA, instructions could be huge (up to 321

bytes), 16 GPRs
Operated on data types from 8 to 128-bits, decimals,
strings
Orthogonal, memory-to-memory, all operand modes
supported
Hundreds of special instructions
Simple compiler, hand-coding was common
CPI was over 10!

CISC vs. RISC CISC architecture examples
x86
Variable length ISA (1-16 bytes)

FP operand stack
2 operand instructions (extended accumulator)
Register-register and register-memory support
Scaled addressing modes
Has been extended many times (as AMD has recently
done with x86-64)
Intel, instead (?) went to IA64

CISC vs. RISC Comparison
RISC vs. CISC arguments
RISC
Simple Implementation
Load/store, fixed-format 32-bit instructions, efficient
pipelines
Lower CPI
Compilers do a lot of the hard work
• MIPS = Microprocessor without Interlocked Pipelined Stages
CISC
Simple Compilers (assists hand-coding, many addressing
modes, many instructions)
Code density
CISC vs. RISC Comparison
MIPS/VAX comparison

CISC vs. RISC Destiny
After the dust settled!
Turns out it doesn’t matter much

Can decode CISC instructions into internal “microISA”
This takes a couple of extra cycles (PLA implementation) and
a few hundred thousand transistors
In 20 stage pipelines, 55M tx processors this is minimal
Pentium 4 caches these micro-Ops
Actually may have some advantages
External ISA for compatibility, internal ISA can be tweaked
each generation (Transmeta Crusoe)

A simple processor prototype Patterson execution engine
Abstract implementation

A simple processor prototype MIPS/RISC V
Final implementation (MIPS/RISC V data path)

Writeback

(Up to here session 9)

Chapter 2 Digital Components CA-401-402-2

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Chapter 2 Digital Components CA-401-402-2

Uploaded by

Copyright:

Available Formats

Computer Architecture

Fundamentals of Computer Architecture

Amir Mahdi Hosseini Monazzah

Amir Mahdi Hosseini Monazzah – IUST

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 2

Instruction Set Architecture (ISA)

“Instruction Set Architecture is the structure of a

The type of internal storage: the most basic

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 4

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 5

Architectures with implicit “stack”

Architectures with one implicit register

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 7

Most common approach

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 8

Common addressing modes for recent processors

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 9

Negotiation with computers?

Op. Code Address

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 10

Negotiation with computers?

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 11

Negotiation with computers? (Up to/from here session 3/4)

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 12

The nearest storage to the processors!

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 13

Common bus system

system with many registers is Write

The basic computer has eight DR

registers, a memory unit, and Adder E

a control unit (in Sec. 5-4) and

Paths must be provided to INPR

transfer information from one

between memory and TR

16-bit common bus

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 14

Common bus system

memory of the basic computer to a Memory unit

common bus system : Fig. 5-4 Write Read

The outputs of seven registers and AR

memory are connected to the LD INR CLR

The specific output is selected by mux LD INR

• Memory(7), AR(1), PC(2), DR(3), AC(4),

because input/output to/from external

• When the mux is selected, data is

– When LD (Load Input) is enable, the TR

16-bit common bus

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 15

Common bus system

• Control Input: LD, INC, CLR, Memory unit

• Address Register: Separate AR

address bus is not required LD INR

(simultaneous processing of LD INR CLR

– AC can only read memory

via DR (See LDA command INPR

memory ( See STA TR

command on p. 147) OUTR

16-bit common bus

Amir Mahdi Hosseini Monazzah – IUST Computer Architecture Spring 2023 16

Common bus system

input path Memory unit

– 1) Register microoperation: Write Read