PINCUSION CORRECTION –PIECE WISE LINEAR IMPLEMENTION

Assumptions
 The CRT display plane is (assumed square) split into 128 blocks (i.e. 64 blocks in each quadrant) for
the purpose of pincushion correction. This should provide sufficient pincushion correction.
 The pincushion correction is centrally symmetrical.
 Correction factor is as those mentioned in the literature i.e x(x2 + y2) and y(x2 + y2) for each x and y
respectively.

Implementation Approach
In view of first assumption, the values of correction factors should be based on the 6 MSBs (as we have 12
bit resolution). The values of correction factor would be determined at regular intervals and stored in the
memory. These become our break points. The correction factor for coordinates within those breakpoints is
determined by the linear approximation.

Implementation

Correction factor is determined for x and y for one quadrant

Storing & Retrieving the correction factor
The concatenated values are stored in the Block ROM. The ROM would be addressed as shown and
correction factor is determined as shown below.

Y11
X11 } These bits are used to determine the quadrant
D15 – D8 CorrY
Y10 – Y5
Block RAM

(Single Dimensional Array having CorrX

D7 – D0
X10 – X5 64K locations each one of 16 bits )

Getting the Error Corrected Display

The pincushion correction factor obtained from the above table defines the correction factor for one
quadrant. The correction factor is given due amplification (through the tuneable parameter). The amplified
correction factors are added or subtracted based on the position of the pixel to the uncorrected pixel
position to get the pincushion corrected display

Y11

Y11 – Y0
Adder / 12 bit data Corrected Y*
Subtractor
CorrY (D15 – D8) 12 bit data

k (D3 – D0)

The process followed for X is also similar to the above one

The Deficiencies
The display obtained after applying above correction looks as following on the CRO. Where the orange is the
uncorrected square and blue one is the corrected display. It may be seen that the curves overlap at the axis.
To correct this, second order corrections need to be applied.

Figure 1
Implementaion of Second Order Distortion
The overlap region corresponds to the difference between the correction values along diagonals and the
axis. Therefore, the intension is to pull all the quadrants away by half of the magnitude of overlap.

Table for Applying Second Order Error Correction

The following table is used to apply correction which is intended to do away with the overlap seen in the
above figure.

In this table, the difference of values of correction along diagonal and axis as computed in the previous table
is recorded.

X=0 X=X Correction Correction Correction

X (Axix) (Diagonal) Fact Along Axis Along Diagonal (16*Difference) Bit Pattern
0 0 0 2048 0 0 0 00000000
1 0 1 2048 0 0 0 00000000
2 0 2 2048 0 0 0 00000000
3 0 3 2048 0 0 0 00000000
4 0 4 2048 0 0 0 00000000
5 0 5 2048 0 0 0 00000000
6 0 6 2048 0 0 0 00000000
7 0 7 2048 0 0 0 00000000
8 0 8 2048 0 0 0 00000000
9 0 9 2048 0 0 0 00000000
10 0 10 2048 0 0 0 00000000
11 0 11 2048 0 1 16 00010000
12 0 12 2048 0 1 16 00010000
13 0 13 2048 1 2 16 00010000
14 0 14 2048 1 2 16 00010000
15 0 15 2048 1 3 32 00100000
16 0 16 2048 2 4 32 00100000
17 0 17 2048 2 4 32 00100000
18 0 18 2048 2 5 48 00110000
19 0 19 2048 3 6 48 00110000
20 0 20 2048 3 7 64 01000000
21 0 21 2048 4 9 80 01010000
22 0 22 2048 5 10 80 01010000
23 0 23 2048 5 11 96 01100000
24 0 24 2048 6 13 112 01110000
25 0 25 2048 7 15 128 10000000
26 0 26 2048 8 17 144 10010000
27 0 27 2048 9 19 160 10100000
28 0 28 2048 10 21 176 10110000
29 0 29 2048 11 23 192 11000000
30 0 30 2048 13 26 208 11010000
31 0 31 2048 14 29 240 11110000

The bit pattern as shown in the last column is stored in the ROM.

Further implementation is following

co

Corrected X/Y*

Block
Sec_level_corr Pin Corr X/Y
X/Y (10 – Y6) RAM

(Single
Dimensional
Array having
32 locations k (D3 – D0)
each one of
8 bits )
Code
-------------------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
--------------------------------------------------------------------------------------------------------------------------------------------------

entity pin_top is
Port ( x_dac_out : out std_logic_vector (11 downto 0);
y_dac_out : out std_logic_vector (11 downto 0);
clk_in : in std_logic;
z : out std_logic;
clk_dac1 : out std_logic;
clk_dac2 : out std_logic;
wr_dac1 : out std_logic;
wr_dac2 : out std_logic;
sw : in std_logic;
sw11 : out std_logic
-- k : in std_logic_vector(3 downto 0)

);
end pin_top;

Architecture Behavioral of pin_top is

component square
port(
clk_in : in std_logic; --- 54 MHZ
sw1 : out std_logic;
z : out std_logic;
x_dac_out : out std_logic_vector(11 downto 0);
y_dac_out : out std_logic_vector(11 downto 0);
clk_in1 : out std_logic
);
end component;

component pin_mem
port (
clka : in std_logic;
addra : in std_logic_VECTOR(11 downto 0);
douta : out std_logic_VECTOR(15 downto 0));
end component;

component corr_2ndodr
port (
clka : in std_logic;
addra : in std_logic_VECTOR(4 downto 0);
douta : out std_logic_VECTOR(7 downto 0));
end component;

----------------------------------Signal Declaration----------------------------------------------------------------------------------------------

signal cnt_20ms : std_logic_vector(24 downto 0);

signal x_dac_out_sig : std_logic_vector(11 downto 0);
signal y_dac_out_sig : std_logic_vector(11 downto 0);
signal x_dac_out_sig1 : std_logic_vector(11 downto 0);
signal y_dac_out_sig1 : std_logic_vector(11 downto 0);
signal x_dac_out_pin : std_logic_vector(11 downto 0);
signal y_dac_out_pin : std_logic_vector(11 downto 0);
signal x_dac_out1 : std_logic_vector(11 downto 0);
signal y_dac_out1 : std_logic_vector(11 downto 0);
signal x_sig : std_logic_vector(7 downto 0);
signal y_sig : std_logic_vector(7 downto 0);
signal k : std_logic_vector(3 downto 0):="0000";
signal sw1 : std_logic;
signal clk_in1 : std_logic;
signal addra : std_logic_vector(11 downto 0);
signal addrb : std_logic_vector(4 downto 0);
signal addrbx,addrby : std_logic_vector(4 downto 0);
signal douta : std_logic_vector(15 downto 0);
signal doutb : std_logic_vector(7 downto 0);
signal sel : std_logic_vector( 1 downto 0):="00";
signal second_level_corr : std_logic_vector( 7 downto 0);
signal second_level_corr_mem : std_logic_vector( 7 downto 0);
signal x_dac_out_sig11 : std_logic_vector(11 downto 0);
signal y_dac_out_sig11 : std_logic_vector(11 downto 0);
signal k_reg : std_logic_vector(3 downto 0):="0000";
signal sw_reg : std_logic:='0';
signal sw_reg1 : std_logic:='0';
signal clk20ms : std_logic;
------------------------------------------------------------------------
begin
sw11<='1';
process(clk_in1) --Generation of 20 ms pulse
begin
if(clk_in1'event and clk_in1='1')then
if(cnt_20ms="110011011111111001100000")then
clk20ms<='1';
cnt_20ms<=(others=>'0');
else
cnt_20ms<=cnt_20ms+'1';
clk20ms<='0';
end if;
end if;
end process;

process(clk_in1) -- Debouncing module for switch

begin
if(clk_in1'event and clk_in1='1')then
sw_reg<=sw;
end if;
end process;

process(clk20ms) -- Internally generated value of k for testing. This is incremented after some interval
begin
if(clk20ms'event and clk20ms='1')then
sw_reg1<=sw_reg;
k_reg<=sw_reg1+k_reg;
end if;
end process;

process(clk20ms)
begin
if(clk20ms'event and clk20ms='1')then
if(k_reg>="1000")then
k<="0000";
else
k<=k_reg;
end if;
end if;
end process;

--------------- Generate the Square for Testing: Instantiation (actual code follows later) -------------------------------------
dut_pin: square
port map(
clk_in =>clk_in, --- 54 MHZ
sw1 =>sw1,
z =>z,
x_dac_out =>x_dac_out_sig1,
y_dac_out =>y_dac_out_sig1,
clk_in1 =>clk_in1
);
-------------------------------------------------------------------------- PIN CUSION CORRECTION MODULE: BEGINS ------------------------------------------

process(clk_in1) -- Determine polarity of X for determining quadrant and addr generation for 1 st level corr mem
begin
if(clk_in1'event and clk_in1='1')then
if(x_dac_out_sig1>2047)then
x_dac_out_sig(10 downto 5)<= x_dac_out_sig1(10 downto 5); --determine the addr of block ram for FIRST order corr
if (y_dac_out_sig(10 downto 0)<x_dac_out_sig(10 downto 0))then
addrbx<= x_dac_out_sig1(10 downto 6); --determine the addr of block ram for SECOND order corr
end if;
else
x_dac_out_sig(10 downto 5)<= not x_dac_out_sig1(10 downto 5); --determine addr of block ram for FIRST order corr

if (x_dac_out_sig(10 downto 0)>=y_dac_out_sig(10 downto 0))then

addrbx<= not (x_dac_out_sig1(10 downto 6)); --determine the addr of block ram for SECOND order corr
end if;
end if;
end if;
end process;

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------

process(clk_in1) -- Determine polarity of Y for determining quadrant and addr generation for 1 st level corr mem
begin
if(clk_in1'event and clk_in1='1')then
if(y_dac_out_sig1>2047)then
y_dac_out_sig(10 downto 5)<= y_dac_out_sig1(10 downto 5); --determine the addr of block ram for FIRST order corr
if (y_dac_out_sig(10 downto 0)<x_dac_out_sig(10 downto 0))then
addrby<= y_dac_out_sig1(10 downto 6); --determine the addr of block ram for SECOND order corr
end if;
else
y_dac_out_sig(10 downto 5)<= not y_dac_out_sig1(10 downto 5); --determine addr of block ram for FIRST order corr

if (y_dac_out_sig(10 downto 0)>=x_dac_out_sig(10 downto 0))then

addrby<= not (y_dac_out_sig1(10 downto 6)) ; --determine the addr of block ram for SECOND order corr
end if;
end if;
end if;
end process;

---The second order correction is applied to remove the overlapping as shown in Figure 1, section “Implementation of Second Order Distortion”
process(clk_in1)
begin
if(clk_in1'event and clk_in1='1')then
if(y_dac_out_sig(10 downto 0)> x_dac_out_sig(10 downto 0))then
addrb<=addrby; --determine the addr of block ram for SECOND order corr
else
addrb<=addrbx;
end if;
end if;
end process;
-------------------------------------------------------- Block ROM mapped for 1st level correction-------------------------------------------------------------
pin_corr : pin_mem
port map (
clka => clk_in1,
addra => addra,
douta => douta
);
--------------------------------------------------------- Block ROM mapped for 2nd t level correction---------------------------------------------------------------

corr_2nd: corr_2ndodr
port map (
clka => clk_in1,
addra => addrb,
douta => second_level_corr_mem);
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
addra<=y_dac_out_sig(10 downto 5)& x_dac_out_sig(10 downto 5); -- addr for block ram for first level corr mem
y_sig<=douta(15 downto 8);
x_sig<=douta(7 downto 0);
sel<=x_dac_out_sig1(11)&y_dac_out_sig1(11);
---------------------------------------------------------------------------------------------

process(clk_in) -- 1st level correction accounting for k i.e. x_corr =x + kx(x*x + y*y) ; y_corr =y + ky(x*x + y*y)
begin
if(clk_in1'event and clk_in1='1')then
case (k) is
when"0000" =>
x_dac_out_pin<="0000"&x_sig; -- k=1
y_dac_out_pin<="0000"&y_sig;
when"0001" =>
x_dac_out_pin<=x_sig+("000"&x_sig(7 downto 3)); --k=1.125 = 1 + 1/8
y_dac_out_pin<=y_sig+("000"&y_sig(7 downto 3));
when"0010" =>
x_dac_out_pin<=x_sig+("00"&x_sig(7 downto 2)); --k=1.25 = 1 + 1/4
y_dac_out_pin<=y_sig+("00"&y_sig(7 downto 2));
when"0011" =>
x_dac_out_pin<=x_sig+("11"*("000"&x_sig(7 downto 3))); --k=1.375= 1+3/8
y_dac_out_pin<=y_sig+("11"*("000"&y_sig(7 downto 3)));
when"0100" =>
x_dac_out_pin<=x_sig+("0"&x_sig(7 downto 1)); --k=1.5 = 1+1/2
y_dac_out_pin<=y_sig+("0"&y_sig(7 downto 1));
when"0101" =>
x_dac_out_pin<=x_sig+("101"*("000"&x_sig(7 downto 3))); --k=1.625= 1+5/8
y_dac_out_pin<=y_sig+("101"*("000"&y_sig(7 downto 3)));
when "0110" =>
x_dac_out_pin<=x_sig+("110"*("000"&x_sig(7 downto 3))); --k=1.75= 1+6/8
y_dac_out_pin<=y_sig+("110"*("000"&y_sig(7 downto 3)));
when"0111" =>
x_dac_out_pin<=x_sig+("111"*("000"&x_sig(7 downto 3))); --k=1.875 = 1+7/8
y_dac_out_pin<=y_sig+("111"*("000"&y_sig(7 downto 3)));
when others=>
x_dac_out_pin<=x_sig+x_sig; --k=2
y_dac_out_pin<=y_sig+y_sig;
end case;
end if;
end process;

process(k) -- 2nd level correction factor based on k

begin
case (k) is
-- k = 1 implies Just read values out from the block men and that gives the correction factor
when"0000" => second_level_corr <= second_level_corr_mem(7 downto 0); --k=1
-- k = 1.125 implies read values out from the block mem, divide it by 8 (rotate right thrice) and
-- add to the value read from the block mem, this gives the correction factor (1.25 = 1 + 1/8)
when"0001" => second_level_corr <=second_level_corr_mem+("000"& second_level_corr_mem(7 downto 3)); --k=1.125 = 1 + 1/8
when"0010" => second_level_corr <=second_level_corr_mem+("00"&second_level_corr_mem(7 downto 2)); --k=1.25 = 1 + 1/4
when"0011" => second_level_corr <=second_level_corr_mem+("11"*("000"&second_level_corr_mem(7 downto 3))); --k=1.375= 1+3/8
when"0100" => second_level_corr <=second_level_corr_mem+("0"&second_level_corr_mem(7 downto 1)); --k=1.5 = 1+1/2
when"0101" => second_level_corr <=second_level_corr_mem+("101"*("000"&second_level_corr_mem(7 downto 3))); --k=1.625= 1+5/8
when"0110" => second_level_corr <=second_level_corr_mem+("110"*("000"&second_level_corr_mem(7 downto 3))); --k=1.75= 1+6/8
when"0111" => second_level_corr <=second_level_corr_mem+("111"*("000"&second_level_corr_mem(7 downto 3))); --k=1.875 = 1+7/8
when others=>second_level_corr <= second_level_corr_mem+second_level_corr_mem; --k=2 = 1+1
end case;
end process;

process(sel) -- apply (add/subtract) 2nd level corrections to the 1st level corrected values
begin
case(sel)is
when "10"=>x_dac_out1<=x_dac_out_sig1-x_dac_out_pin+second_level_corr; --Quadrant 2
y_dac_out1<=y_dac_out_sig1+y_dac_out_pin- second_level_corr;
when "11"=>x_dac_out1<=x_dac_out_sig1-x_dac_out_pin +second_level_corr; --Quadrant 3/1
y_dac_out1<=y_dac_out_sig1-y_dac_out_pin +second_level_corr;
when "00"=>x_dac_out1<=x_dac_out_sig1+x_dac_out_pin - second_level_corr; --Quadrant 1/3
y_dac_out1<=y_dac_out_sig1+y_dac_out_pin - second_level_corr;
when others=>x_dac_out1<=x_dac_out_sig1+x_dac_out_pin - second_level_corr; --Quadrant 4/2
y_dac_out1<=y_dac_out_sig1-y_dac_out_pin + second_level_corr;
-- when others=> NULL;
end case;
end process;
x_dac_out <=x_dac_out1; --Pincushion Xcorr
y_dac_out <=y_dac_out1; --Pincushion Ycorr
clk_dac1 <=clk_in1;
clk_dac2 <=clk_in1;
wr_dac1 <=clk_in1;
wr_dac2 <=clk_in1;
end Behavioral;
----------------------------------------------------------- PIN CUSION CORRECTION MODULE : ENDS -----------------------------------------
-- Actual square generation code ( which is included in the top module above )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity square is
port(
clk_in : in std_logic; --- 54 MHZ
sw1 : out std_logic;
z : out std_logic;
x_dac_out : out std_logic_vector(11 downto 0);
y_dac_out : out std_logic_vector(11 downto 0);
clk_in1 : out std_logic
);

end square;

Architecture Behavioral of square is

signal x_sig : std_logic_vector(11 downto 0):="001100101000";

signal x_sig1 : std_logic_vector(11 downto 0);
signal y_sig1 : std_logic_vector(11 downto 0);
signal z_sig : std_logic;
signal rst : std_logic;
signal clk : std_logic;
signal y_sig : std_logic_vector(11 downto 0):="001100101000";
signal cnt : std_logic_vector(23 downto 0):=(others=>'0');
signal cnt1 : std_logic_vector(3 downto 0):=(others=>'0');
signal cnt2 : std_logic_vector(3 downto 0):=(others=>'0');
signal a :std_logic;
signal b :std_logic;
signal c :std_logic;
signal z1 :std_logic;
signal clk1 :std_logic;
signal clk3 :std_logic;
signal clk27 :std_logic;
signal sw1_sig :std_logic:='0';
signal sel :std_logic:='0';
signal sel1 :std_logic:='0';
signal sel2 :std_logic:='0';
signal x_sig_s : std_logic_vector(11 downto 0):="010110010100";
signal y_sig_s : std_logic_vector(11 downto 0):="010110010100";
signal z_sig_s : std_logic;
signal x_sig_sm : std_logic_vector(11 downto 0):="011100100100"; --1828
signal y_sig_sm : std_logic_vector(11 downto 0):="011100100100";
signal z_sig_sm : std_logic;
signal x_sig_l : std_logic_vector(11 downto 0):="000110011010"; --600
signal y_sig_l : std_logic_vector(11 downto 0):="000110011010";
signal z_sig_l : std_logic;
signal x_sig_o : std_logic_vector(11 downto 0):="001100110100"; --300
signal y_sig_o : std_logic_vector(11 downto 0):="001100110100";
signal z_sig_o : std_logic;
signal x_sig_so : std_logic_vector(11 downto 0):="010001011110"; --1118
signal y_sig_so : std_logic_vector(11 downto 0):="010001011110";
signal z_sig_so : std_logic;

begin
clk1<=clk_in; --54 MHz

process(clk1)
begin
if clk1'event and clk1='1' then --divide by 4 circuit
cnt1<=cnt1+'1';
if 0<=cnt1 and cnt1<=1 then
clk3<='1';
elsif 2 <= cnt1 and cnt1 <=3 then
clk3<='0';
end if;
if cnt1= 3 then
cnt1<=(others=>'0');
end if;
end if;
end process;

process(clk3)
begin
if clk3'event and clk3='1' then
cnt<=cnt+'1';
if cnt= 0 then
rst<='1';
else
rst<='0';
end if;
if 1 <= cnt and cnt <=9930 then --- for onr square
sel <='0';
sel1 <='0';
sel2 <='0';
z_sig <='1';
z_sig_s <='0';
z_sig_l <='0';
z_sig_so<='0';
elsif (cnt>=9931 and cnt<=19862)then
sel <='1';
sel1 <='0';
sel2 <='0';
z_sig <='0';
z_sig_s <='1';
z_sig_l <='0';
z_sig_so<='0';
elsif (cnt>=19863 and cnt<=31448)then
sel <='0';
sel1 <='1';
sel2 <='0';
z_sig <='0';
z_sig_s <='0';
z_sig_l <='1';
z_sig_so<='0';
elsif (cnt>=31449 and cnt<=45435)then
sel <='1';
sel1 <='1';
sel2 <='0';
z_sig <='0';
z_sig_s <='0';
z_sig_l <='0';
z_sig_o <='1';
z_sig_so<='0';

elsif (cnt>=45436 and cnt<=53000)then

sel <='1';
sel1 <='1';
sel2 <='1';
z_sig <='0';
z_sig_s <='0';
z_sig_ l<='0';
z_sig_o <='0';
z_sig_so<='1';

else
z_sig <='0';
z_sig_s<='0';
z_sig_l<='0';
z_sig_o<='0';
z_sig_so<='0';
end if;
if cnt=270270 then
cnt<=(others=>'0');
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------------

clk_in1 <=clk3;

process(clk3)
begin
if clk3'event and clk3='1' then
if rst='1' then
----------------------------------------------Smallest Square-------------------------------------------

x_sig_s<="010110010100"; ---1428
y_sig_s<="010110010100";
elsif z_sig_s='1' then
if (x_sig_s>=1428 and x_sig_s<=2668) and y_sig_s= 1428 then
x_sig_s<= x_sig_s+'1';
y_sig_s<="010110010100"; ---1428
elsif x_sig_s= 2669 and (y_sig_s>= 1428 and y_sig_s<=2668) then
x_sig_s<="101001101101"; ---2669
y_sig_s<=y_sig_s+'1';
elsif (x_sig_s<=2669 and x_sig_s>1428) and y_sig_s=2669 then
x_sig_s<=x_sig_s-'1';
y_sig_s<="101001101101"; --2669
elsif x_sig_s=1428 and (y_sig_s <= 2669 and y_sig_s >=1428) then
x_sig_s<="010110010100"; ---1428
y_sig_s<=y_sig_s-'1';
end if;
end if;
end if;
end process;

process(clk3)
begin
if clk3'event and clk3='1' then
if rst='1' then
x_sig_so<="010001011110"; ---1118
y_sig_so<="010001011110";
elsif z_sig_so='1' then
if (x_sig_so>=1118 and x_sig_so<=2978) and y_sig_so= 1118 then
x_sig_so<= x_sig_so+'1';
y_sig_so<="010001011110"; ---1118
elsif x_sig_so= 2979 and (y_sig_so>= 1118 and y_sig_so<=2978) then
x_sig_so<="101110100011"; ---2979
y_sig_so<=y_sig_so+'1';
elsif (x_sig_so<=2979 and x_sig_so>1118) and y_sig_so=2979 then
x_sig_so<=x_sig_so-'1';
y_sig_so<="101110100011"; --2979
elsif x_sig_so=1118 and (y_sig_so <= 2979 and y_sig_so >=1118) then
x_sig_so<="010001011110"; ---1118
y_sig_so<=y_sig_so-'1';
end if;
end if;
end if;
end process;

------------------------------------------Bigger square--------------------------------------------------
process(clk3)
begin
if clk3'event and clk3='1' then
if rst='1' then
----------------
x_sig<="001100101000"; ---808
y_sig<="001100101000";
elsif z_sig='1' then
if (x_sig>=808 and x_sig<=3288) and y_sig= 808 then
x_sig<= x_sig+'1';
y_sig<="001100101000"; --808
elsif x_sig= 3289 and (y_sig>= 808 and y_sig<=3288) then
x_sig<="110011011001"; --3289
y_sig<=y_sig+'1';
elsif (x_sig<=3289 and x_sig>808) and y_sig=3289 then
x_sig<=x_sig-'1';
y_sig<="110011011001"; --3289
elsif x_sig=808 and (y_sig <= 3289 and y_sig >=808) then
x_sig<="001100101000"; --808
y_sig<=y_sig-'1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------------------

process(clk3)
begin
if clk3'event and clk3='1' then
if rst='1' then
x_sig_l<="001001011000"; ---600
y_sig_l<="001001011000";
elsif z_sig_l='1' then
if (x_sig_l>= 600 and x_sig_l<=3496) and y_sig_l= 600 then
x_sig_l<= x_sig_l+'1';
y_sig_l<="001001011000"; ---600
elsif x_sig_l= 3497 and (y_sig_l>= 600 and y_sig_l<=3496) then
x_sig_l<="110110101001"; ---3497
y_sig_l<=y_sig_l+'1';
elsif (x_sig_l<=3497 and x_sig_l>600) and y_sig_l=3497 then
x_sig_l<=x_sig_l-'1';
y_sig_l<="110110101001"; --3497
elsif x_sig_l=600 and (y_sig_l <= 3497 and y_sig_l >=600) then
x_sig_l<="001001011000"; ---600
y_sig_l<=y_sig_l-'1';
end if;
end if;
end if;
end process;

process(clk3)
begin
if clk3'event and clk3='1' then
if rst='1' then
x_sig_o<="000100101100"; ---300
y_sig_o<="000100101100";
elsif z_sig_o='1' then
if (x_sig_o>=300 and x_sig_o<=3796) and y_sig_o= 300 then
x_sig_o<= x_sig_o+'1';
y_sig_o<="000100101100"; ---300
elsif x_sig_o= 3797 and (y_sig_o>= 300 and y_sig_o<=3796) then
x_sig_o<="111011010101"; ---3797
y_sig_o<=y_sig_o+'1';
elsif (x_sig_o<=3797 and x_sig_o>300) and y_sig_o=3797 then
x_sig_o<=x_sig_o-'1';
y_sig_o<="111011010101"; --3797
elsif x_sig_o=300 and (y_sig_o <= 3797 and y_sig_o >=300) then
x_sig_o<="000100101100"; ---300
y_sig_o<=y_sig_o-'1';
end if;
end if;
end if;
end process;

process(clk3)
begin
if clk3'event and clk3='1' then
if (sel='0' and sel1='0' and sel2='0')then
x_dac_out <= x_sig;
y_dac_out <= y_sig;
z <= z_sig;
elsif (sel='1' and sel1='0' and sel2='0')then
x_dac_out <= x_sig_s;
y_dac_out <= y_sig_s;
z <= z_sig_s;
elsif (sel='0' and sel1='1' and sel2='0')then
x_dac_out <= x_sig_l;
y_dac_out <= y_sig_l;
z <= z_sig_l;
elsif (sel='1' and sel1='1' and sel2='0')then
x_dac_out <= x_sig_o;
y_dac_out <= y_sig_o;
z <= z_sig_o;
elsif (sel='1' and sel1='1' and sel2='1')then
 x_dac_out <= x_sig_so;
y_dac_out <= y_sig_so;
z <= z_sig_so;
else
x_dac_out <= (others=>'0');
y_dac_out <= (others=>'0');
z <= '0';
end if;
end if;
end process;

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process(cnt)
begin
if(cnt=270270) then
sw1_sig<=not sw1_sig;
end if;
sw1<=sw1_sig;
end process;
-----------------------------------------------------------------------------------------------------------------------------------------

end Behavioral;

-----------------------UCF for Pincushion testing--------------------------------------------------

NET "clk_in" LOC = K14;

NET "clk_dac1" LOC = AA13;
NET "clk_dac2" LOC = Y13;
NET "wr_dac1" LOC = AE13;
NET "wr_dac2" LOC = AF13;
NET "x_dac_out<0>" LOC = Y9;
NET "x_dac_out<1>" LOC = W9;
NET "x_dac_out<2>" LOC = AF3;
NET "x_dac_out<3>" LOC = AE3;
NET "x_dac_out<4>" LOC = AF4;
NET "x_dac_out<5>" LOC = AE4;
NET "x_dac_out<6>" LOC = AD6;
NET "x_dac_out<7>" LOC = AC6;
NET "x_dac_out<8>" LOC = W10;
NET "x_dac_out<9>" LOC = V10;
NET "x_dac_out<10>" LOC = AE6;
NET "x_dac_out<11>" LOC = AF5;
NET "y_dac_out<0>" LOC = AA10;
NET "y_dac_out<1>" LOC = Y10;
NET "y_dac_out<2>" LOC = U11;
NET "y_dac_out<3>" LOC = V11;
NET "y_dac_out<4>" LOC = AB7;
NET "y_dac_out<5>" LOC = AC8;
NET "y_dac_out<6>" LOC = AC9;
NET "y_dac_out<7>" LOC = AB9;
NET "y_dac_out<8>" LOC = W12;
NET "y_dac_out<9>" LOC = V12;
NET "y_dac_out<10>" LOC = AF8;
NET "y_dac_out<11>" LOC = AE8;
NET "sw" LOC = V24;
NET "sw11" LOC = V23;
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