"CMOS VLSI DESIGN:

A COMPREHENSIVE GUIDE TO
INTEGRATED CIRCUIT DESIGN AND
ANALYSIS"
Outline
Delay Definitions
RC Delay Model
Resistance Model of a MOSFET
Capacitance Model of a MOSFET
RC equivalent of an Inverter
Transient Analysis of CMOS circuits using RC delay model
Estimation of logical effort, branch effort, and path effort
Design of Multi-Stage Circuits for Minimum Delay
Loading effect by High Capacitance of I/O Pads & Bond
Wires
Buffer Design to Increase Driving Capability
Basic Delay Definitions:
 Propagation delay time, tpd = time difference of the input crossing 50% and
the output crossing 50% of its maximum stable value for worst case
 Contamination delay time, tcd = time difference for the input crossing 50%
and the output crossing 50% of its maximum stable value for best case
 Rise time, tr = time for a waveform to rise from 10% to 90% of its steady-
state value
 Fall time, tf = time for a waveform to fall from 90% to 10% of its steady-state
value

Propagation delay = (tphl + tplh) / 2

For both the worst or best case,

propagation delay can be determined
from the corresponding values of tphl
and tplh for that case.
RC delay Model for MOSFET
 Resistance R and Capacitance C of
MOSFETs are very important to decide
the transient performance of MOS
circuits
 RC model for a single nMOS, of k times
than unit size, is show in figure

 Here, 𝑅𝑛 is channel resistance of nMOS which is a function of biasing voltage

𝑽𝑫𝑺
and given as: 𝑹𝒏 =
𝑰𝑫
 But for the linear region of nMOS,
𝑉𝐺𝑆 > 𝑉𝑇𝑛 and 𝑉𝐷𝑆 > 0 but very small:
𝑊
Then, 𝐼𝐷 = µ𝑛 𝐶𝑜𝑥 𝐿 (𝑉𝐺𝑆 − 𝑉𝑇𝑛 )𝑉𝐷𝑆
𝑾
 Hence, 𝑹𝒏 = 𝟏/ µ𝒏 𝑪𝒐𝒙 (𝑽𝑮𝑺 − 𝑽𝑻𝒏 )
𝑳

 For the triode region of nMOS,

𝑉𝐺𝑆 > 𝑉𝑇𝑛 and 0 < 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇𝑛
𝑊 𝑉𝐷𝑆 2
Then, 𝐼𝐷 is given as: 𝐼𝐷 = µ𝑛 𝐶𝑜𝑥 𝐿 [ 𝑉𝐺𝑆 − 𝑉𝑇𝑛 𝑉𝐷𝑆 − ]
2
 𝑾
 Hence, 𝑹𝒏 = 𝟐/{µ𝒏 𝑪𝒐𝒙 𝟐 𝑽𝑮𝑺 − 𝑽𝑻𝒏 − 𝑉𝐷𝑆 }
𝑳

 The saturation region of nMOS is given as:

𝑉𝐺𝑆 > 𝑉𝑇𝑛 and 𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑇𝑛
1 𝑊
Then, 𝐼𝐷 = µ 𝐶 [ 𝑉𝐺𝑆 − 𝑉𝑇𝑛 2 ]
2 𝑛 𝑜𝑥 𝐿
𝑾 2
 Hence, 𝑹𝒏 = 𝟐𝑉𝐷𝑆 / µ𝒏 𝑪𝒐𝒙 𝑉𝐺𝑆 − 𝑉𝑇𝑛
𝑳

 The generalized model of channel

resistance, independent of its
operating region for nMOS is given
as:

𝑹𝒏 = 𝟏/ 𝜷𝒏 (𝑽𝑫𝑫 − 𝑽𝑻𝒏 )
𝑾
- where, 𝜷𝒏 = µ𝒏 𝑪𝒐𝒙
𝑳

 The similar method is applied for the

pMOS device resistance modelling.
Resistance dependence with sizing and voltage
 In general, the channel resistance for the nMOS and pMOS dependent on the
gate to source voltage can be written as:

𝑾
𝑹𝒏 ∝ 𝟏/ µ𝒏 𝑪𝒐𝒙 (𝑽𝑮𝑺 − 𝑽𝑻𝒏 )
𝑳 𝒏

𝑾
𝑹𝒑 ∝ 𝟏/ µ𝒑 𝑪𝒐𝒙 (𝑽𝑺𝑮 − |𝑽𝑻𝒑 |)
𝑳 𝒑

Approximate channel resistance of MOS

ε𝑜𝑥
where, 𝐶𝑜𝑥 = is a process constant which is oxide capacitance per unit
𝑡𝑜𝑥
area (F/cm2).

 From the above equations it is clear that:

- 𝑹𝒏 ∝ 𝟏/𝑾 (hence, higher the width lesser would be the resistance)
- Also, the resistance varies with the gate voltage as shown in the figure.
- If we assume 𝑾𝒏 = 𝑾𝒑 and 𝑽𝑻𝒏 = |𝑽𝑻𝒑 |, then 𝑹𝒏 < 𝑹𝒑
- It is so because, µ𝒏 > µ𝒑
- Therefore, to match the resistance we have to increase 𝑊𝑝
Capacitance for RC model
 Here we develop the basic idea of capacitance value of nMOS for the RC
modelling.
 Basically the capacitance is divided in to two parts:
 Gate oxide related capacitance (𝐶𝐺𝑆 , 𝐶𝐺𝐷 )
 Junction capacitance (𝐶𝐷𝐵 , 𝐶𝑆𝐵 )

 Gate oxide capacitance (𝐶𝐺 ): It is developed due to

the overlap of gate electrode and channel charge.
ε𝑜𝑥
𝑪𝑮 = 𝑪𝒐𝒙 𝐖 𝐋 where, 𝐶𝑜𝑥 = 𝑡𝑜𝑥

- This 𝐶𝐺 is equally split between 𝐶𝐺𝑆 and 𝐶𝐺𝐷 such that:

1 1
𝐶𝐺𝑆 = 2 𝐶𝑜𝑥 𝑊 𝐿 and 𝐶𝐺𝐷 = 2 𝐶𝑜𝑥 𝑊 𝐿
 Also, the gate electrode overlaps the source and drain region at the edges and
results into overlap capacitances:
𝐶𝐺𝑆(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) = 𝐶𝑜𝑥 𝑊 𝐿𝐷 and 𝐶𝐺𝐷(𝑜𝑣𝑒𝑟𝑙𝑎𝑝) = 𝐶𝑜𝑥 𝑊𝐿𝐷
- here 𝐿𝐷 is the channel overlapping length at one end.
 Therefore, the resultant gate capacitance is given as:
𝟏 𝟏
𝑪𝑮𝑺 = 𝟐 𝑪𝒐𝒙 𝑾 𝑳 + 𝑪𝒐𝒙 𝑾 𝑳𝑫 and 𝑪𝑮𝑫 = 𝟐 𝑪𝒐𝒙 𝑾 𝑳 + 𝑪𝒐𝒙 𝑾 𝑳𝑫
Junction Capacitance
 It appears due to the diffusion of drain and source regions which create
depletion regions near the substrate and the channel stop implants.
 The capacitances for the surface 1 and 5, in the figure, are given as:
𝑪𝒋𝒖𝒏 = 𝑪𝒋 𝑨𝒋𝒖𝒏
where, 𝐶𝑗 is junction capacitance per unit area (F/cm2) and 𝐴𝑗𝑢𝑛 is junction area (cm2) .
 The junction capacitances for the diffusion surfaces (2, 3 and 4) which are in
contact with the highly doped channel stop implants are given as:
𝑪𝒔𝒘 = 𝑪𝒋𝒔𝒘 𝑷𝒔𝒘
here, 𝑪𝒋𝒔𝒘 = 𝑪𝒋 𝒙𝒋 (F/cm), 𝒙𝒋 is junction depth and 𝑷𝒔𝒘 is the surface perimeter
(cm).

 Therefore, the total junction capacitance is

given as:
𝑪𝒋𝒕𝒐𝒕𝒂𝒍 = 𝑪𝒋𝒖𝒏 + 𝑪𝒔𝒘
 It leads to total source and drain junction
capacitance as:
𝑪𝑺𝑩 (𝒔𝒐𝒖𝒓𝒄𝒆 − 𝒃𝒖𝒍𝒌) = 𝑪𝒋 𝑨𝑺𝒋𝒖𝒏 + 𝑪𝒋𝒔𝒘 𝑷𝑺𝒔𝒘
𝑪𝑫𝑩 (𝒅𝒓𝒂𝒊𝒏 − 𝒃𝒖𝒍𝒌) = 𝑪𝒋 𝑨𝑫𝒋𝒖𝒏 + 𝑪𝒋𝒔𝒘 𝑷𝑫𝒔𝒘
Capacitance dependence on sizing
 The gate capacitance increases with the increasing size of the device.
 Hence, for a MOSFET with k times of unit width will have gate capacitance
k𝑪𝑮 .
 Diffusion capacitance also increases proportional to the device width.
 However, Increasing channel length increases gate capacitance
proportionally but does not affect diffusion capacitance.

 The overall capacitance (gate capacitance and diffusion capacitance)

can be partitioned into 𝑪𝑮 , 𝑪𝑺 and 𝑪𝑫 as shown below:
Resultant RC delay Model for a MOSFET
 The equivalent RC delay models for nMOS and pMOS devices of width k are
shown in figure below.
𝑳
 where resistance 𝑹𝒏 ∝ (𝑾) and 𝑪 ∝ 𝐖

 Here, pMOS has twice the resistance than nMOS because holes mobility (µ𝒑 ) is
approx. half of the electron mobility (µ𝒏 ) and
𝑹 ∝ 𝟏/µ

 To make the equal resistance of nMOS and pMOS, we have to double the
width of pMOS.
Calculate the load capacitance at
the output node B of inverter X1?

 It can be determined by estimating the

individual terminal capacitances and
then calculating the equivalent effect
of them on node B, as shown in
figures below:

wire capacitance from

output of X1 to input of X2
RC Equivalent of an Inverter
 Below is the equivalent circuit for a fanout-of-1 inverter, when we have
neglected the wire capacitance.
- Fanout-of-1: means when the inverter is driving one similar inverter gate at the load.
 The given inverter is composed of nMOS of unit size and pMOS of twice width
of unit size to exhibit equal rise and fall current/resistance.

when input is logic 1.

Hence nMOS is ON and
pMOS is OFF

Fanout-of-1 (FO1) Inverter

Output capacitance = 𝟐𝑪 + 𝑪 + 𝟒 𝟐𝑪 + 𝑪 = 𝟏𝟓𝑪

Fanout-of-4 (FO4) Inverter

 Transient response from the RC delay model
 Once the RC model is determined from the CMOS
inverter, it can easily be analysed for the transient
response.
 The transfer function of this first order RC model
driven by a step input :
1
𝐻 𝑠 =
(1+𝑠𝑅𝐶)
 By taking the inverse Laplace transform of H(s), the
step response:
𝑉𝑌 𝑡 = 𝑉𝐷𝐷 𝑒 −𝑡 τ where 𝜏 = 𝑅𝐶
 Now, the propagation delay 𝑡𝑝𝑑 is the time at which
the output 𝑉𝑌 reaches to 𝑉𝐷𝐷 /2. Hence,
𝑉𝐷𝐷 /2 = 𝑉𝐷𝐷 𝑒 −𝑡𝑝𝑑 𝑅𝐶

 It gives: 𝑡𝑝𝑑 = 𝑅𝐶 𝑙𝑛2 𝑡𝑝𝑑 ∝ 𝑅𝐶

 Note: Delay increases with the increasing value of both R and C.

Design of a 3-input NAND gate for effective rise and fall
resistance equal to that of a unit inverter (R):
For worst case, only
single pMOS will be
ON, which is
equivalent to that of
a unit inverter

Width is 3 times due

to series connection:
(R/3 + R/3 + R/3
= R)

Capacitance gets increased

3 times due to increased
device width
Design of a 3-input NAND gate for effective rise and fall
resistance equal to that of a unit inverter (R)…

 Capacitances connected to the o/p terminal Y are combined

together (2C+2C+2C+3C=9C)
 In similar manner, gate capacitances are detemined.
 RC equivalent delay model for 3-input NAND
Gate
 In the worst case of output falling transition, output pulls
down through the three series nMOS transistors.
 During the worst case of rising transition, two pMOS
remains off and one is ON. Accordingly, upper two nMOS
are still ON and bottom one is OFF.
 Hence, the series capacitances of upper two nMOS must
also be discharged during the falling transition in worst
case.

RC equivalent when RC equivalent when output is rising

output is falling in worst case
Elmore Delay model to solve RC equivalent
delay models
 RC equivalent models of the CMOS circuits can be solved by using the Elmore’s
delay model:

𝒕𝒑𝒅 = 𝒏𝒐𝒅𝒆−𝒊 (𝑹𝒊−𝒕𝒐−𝒔𝒐𝒖𝒓𝒄𝒆 𝑪𝒊 )

= 𝑹𝟏 𝑪𝟏 + (𝑹𝟏 +𝑹𝟐 )𝑪𝟐 + ⋯ (𝑹𝟏 +𝑹𝟐 + 𝑹𝟑 … +𝑹𝑵 )𝑪𝑵
Delay Modelling for a 2-input NAND Gate with Fan-
out of h (FOh)

Worst case Falling delay:

Worst case Rising delay:
𝑅 𝑅 𝑅
𝑡𝑝𝑑𝑟 = (6 + 4ℎ)𝑅𝐶 𝑡𝑝𝑑𝑑 = 2𝐶 + + 6 + 4ℎ 𝐶
2 2 2
= (7 + 4ℎ)𝑅𝐶

Note: In both the cases, delay has two components (i) Independent of load
capacitance (here 6 or 7 RC) (ii) Due to external loading (4hRC)
Delay of a Gate as a Process-Independent Unit
(Normalized Delay 𝒅)
𝒅𝒂𝒃𝒔 where 𝜏 = 3𝑅𝐶 is the delay of an inverter driving an identical
𝒅= inverter (FO1 inverter) with no parasitic capacitance
𝝉
 Delay d has two components: 𝒅=𝒇+𝒑
 𝒇 is Effort Delay or Stage Effort which is due to the external loading
 𝒑 is Parasitic delay due to the internal capacitance when gate driving no load
(total capacitance appearing at the output terminal divided by that of unit
inverter)

 Stage effort 𝒇 = 𝒈. 𝒉

 Logic Effort (𝒈): Ratio of input capacitance of a gate to that of an inverter

capable of delivering the same output current:
𝑪𝒊𝒏,𝒈𝒂𝒕𝒆
𝒈=
𝑪𝒊𝒏,𝒖𝒏𝒊𝒕_𝒊𝒏𝒗
 Electrical Effort (𝒉): A gate driving h copies of itself is said to have a fan
out or electrical effort of h, which is the ratio of output capacitance and input
𝑪𝒐𝒖𝒕
capacitance of the gate: 𝒉=
𝑪𝒊𝒏,𝒈𝒂𝒕𝒆
Delay of a Gate as a Process-Independent Unit
(Normalized Delay 𝒅)…
𝑪𝒊𝒏,𝒈𝒂𝒕𝒆 𝑪𝒐𝒖𝒕
 Then, the Effort delay: 𝑓 = 𝑔. ℎ = 𝑪𝒊𝒏,𝒖𝒏𝒊𝒕_𝒊𝒏𝒗 𝑪𝒊𝒏,𝒈𝒂𝒕𝒆

𝑪𝒐𝒖𝒕
=𝑪
𝒊𝒏,𝒖𝒏𝒊𝒕_𝒊𝒏𝒗

 Hence, the delay due to the external loading only:

𝑪𝒐𝒖𝒕
𝑑(𝑎𝑏𝑠)_𝑒𝑥𝑡 = 𝑔. ℎ. τ = 3𝑅𝐶
𝑪𝒊𝒏,𝒖𝒏𝒊𝒕_𝒊𝒏𝒗
𝑪𝒐𝒖𝒕
= 𝑅 𝑪𝒊𝒏,𝒖𝒏𝒊𝒕𝒊𝒏𝒗 = 𝑪𝒐𝒖𝒕 𝑹
𝑪𝒊𝒏,𝒖𝒏𝒊𝒕𝒊𝒏𝒗

𝒅(𝒂𝒃𝒔)_𝒆𝒙𝒕 = 𝑪𝒐𝒖𝒕 𝑹

 Note: delay part due to the external loading is proportional to the load
capacitance (𝑪𝒐𝒖𝒕 ).
Estimation of Logical Effort (g)

(a) Inverter (b) 3-input NAND gate (c) 3-input NOR gate

𝑪𝒊𝒏 = 𝟐 + 𝟏 = 𝟑 𝑪𝒊𝒏 = 𝟐 + 𝟑 = 𝟓 𝑪𝒊𝒏 = 𝟔 + 𝟏 =7

𝑪𝒊𝒏,𝒈𝒂𝒕𝒆 𝟑 𝟓 𝟕
𝒈= = =𝟏 𝒈= 𝒈=
𝑪𝒊𝒏,𝒖𝒏𝒊𝒕_𝒊𝒏𝒗 𝟑 𝟑 𝟑
Logical Effort of Basic Gates
Gate Type Number of Inputs
1 2 3 4 N
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
MUX 2 2 2 2 2
XOR/XNOR 4 6 8

Parasitic Delay of Basic Gates

Gate Type Number of Inputs
1 2 3 4 N
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
MUX 2 4 6 8 2n
Frequency of a Ring Oscillator

Delay 𝑑 = 𝑔. ℎ + 𝑝
Logical effort 𝑔 = 1
Electrical Effort ℎ = 1
Parasitic Delay 𝑝 = 1
Delay of each stage 𝑑 = 𝑔. ℎ + 𝑝 = 1 ∗ 1 + 1 = 2
 Now, N-stage ring oscillator has a period of 2N stage delays because a value must
propagate twice around the ring to regain the original polarity. Therefore, the total
period of this oscillator is:
𝑇 = 2𝑁. 𝑑 = 4𝑁
1
 Hence, the frequency of operation is: f = 𝑇 = (1/4𝑁)
Individual estimation in multi stage path
Logical Effort of Paths and Path Delay
 Overall path effort is given as:
𝑭 = 𝑮𝑩𝑯
 Path logical effort G is the products of the logical efforts
of each stage along the path having i number of stages:
𝐺 = 𝑔𝑖
 Path electrical effort H is the ratio of the output
capacitance the path must drive divided by the input
capacitance presented by the path:
𝐶𝑜𝑢𝑡(𝑝𝑎𝑡ℎ}
𝐻=
𝐶𝑖𝑛(𝑝𝑎𝑡ℎ)
 Path branching effort B is the product of the branching
efforts between stages:
𝐵 = 𝑏𝑖
where, branching effort b is the ratio of the total capacitance
seen by a stage to the capacitance on the path:
𝐶𝑜𝑛(𝑝𝑎𝑡ℎ} + 𝐶𝑜𝑓𝑓(𝑝𝑎𝑡ℎ} 15 + 15
𝑏= = =2
𝐶𝑜𝑛(𝑝𝑎𝑡ℎ) 15
 Now, the Path delay D is the sum of the delays of each stage, or It can be written
as the sum of the path effort delay 𝐷𝐹 and path parasitic delay P:
𝑫= 𝒅𝒊 = 𝑮𝑩𝑯 + 𝑷 where, 𝑃= 𝑝𝑖
Logical Effort of Paths and Path Delay…

 The path delay is minimized when each stage bears the same effort.
 If a path has N stages and each bears the same effort, that the stage effort must
be:
𝒇 = 𝒈 𝒊 𝒉 𝒊 = 𝑭𝟏 𝑵
 Thus, the minimum possible delay of an N-stage path with path effort F and path
parasitic delay P is:
𝑫 = 𝑵𝑭𝟏 𝑵 + 𝑷
 This is a key result of Logical Effort. It shows that the minimum delay of the path
can be estimated knowing only the number of stages, path effort, and parasitic
delays without the need to assign transistor sizes.
Estimate the minimum delay of the
path from A to B, and determine the
required Gate sizes

 Path logical effort is: G = 4/3 x 5/3 x 5/3 = 100/27

 Path electrical effort is: H = 45/8
 Path branching effort is: B = (1+2)/1 x (1+1)/1 = 3 x 2 = 6
 The path effort is: F = GBH = 100/27 x 6 x 45/8 = 125
 Now, for the minimum path delay, the best stage effort is:
𝒇 = (125)1/3 = 5
 Path parasitic delay is: P = 2 + 3 + 2 = 7
 Hence, the minimum path delay is: D = N𝒇 + P = 3 x 5 + 7 = 22

 Now, to determine the size of various gates for min. delay:

𝑪 𝑪
𝒇 = 𝒈𝒊 𝒉𝒊 = 𝒈𝒊 𝑪𝒐𝒖𝒕,𝒊 => 𝑪𝒊𝒏,𝒊 = 𝒈𝒊 𝒐𝒖𝒕,𝒊
𝒊𝒏,𝒊 𝒇

 Hence, working backward along the path: size y = (5/3)x(45/5) = 15

x = (5/3)x(15+15)/5 = 10
Delay analysis through the simulation for a
FO3-Inverter
 Two methods for a Fan-out 3 Inverter is shown below:
1. The inverter working as the load has device sizes three times of the device size
for unit inverter
2. Three unit inverters are connected at the load of unit inverter

FO3 Inverter: Method 2

FO3 Inverter: Method 1
Delay analysis through the simulation for a
FO3-Inverter…

Transient simulation
result of FO3 Inverter

 From the simulation: τ𝑝𝐻𝐿 = 117.484𝑝𝑆, τ𝑝𝐿𝐻 = 176.403𝑝𝑆

 Hence, τ𝐹𝑂3 =(τ𝑝𝐻𝐿 + τ𝑝𝐿𝐻 )/2 = 146.94𝑝𝑆
 Since, it is the delay of FO3 inverter, then the unit inverter delay:
τ𝐹𝑂3
τ= = 36.735𝑝𝑆
4
Logical Effort and Parasitic Delay Estimation
using simulation
 The delay of a gate is given as: 𝑑𝑒𝑙𝑎𝑦 = 𝑔ℎ + 𝑝
 From the previous result of FO3 Inverter,
τ𝐹𝑂3 = 146.94𝑝𝑆 = 𝑔ℎ1 + 𝑝 (1)
 Now, by simulating the FO1 Inverter (as shown below, which has the same unit
inverter connected at the load), τ𝐹𝑂1= 94.06𝑝𝑆 = 𝑔ℎ2 + 𝑝 (2)

 By solving Eq. (1) and (2), we get:

Logical Effort (g) = 26.44 pS
Parasitic Delay (p) = 67.62 pS

https://www.engr.usask.ca/classes/CME/342/lab_files/CME
342_lab4_logic_effort.pdf
FO1 Inverter
 Driver/Buffer Design for I/O Pads and Bond wire
loading affect
 The delay (RC) for any circuit is increased with
the increasing load capacitance.
 The excessive load (as shown by CL) may
disturb the circuit functionality. It is due to the
time taken to charge/discharge the output load
capacitance.
 Now, think about the I/O pads and bond wire
loading effect with a huge size (see figures). It
is almost impossible for our design to drive
such a huge load.
A single
I/O pad

Unit Inverter

Small
Capacitor
(15fF)
Driver/Buffer Design for I/O Pads and Bond wire
loading affect…
 Each I/O Pad or Bond wire create a heavy
capacitive load (approx. in the range of 5-10
pF).
 A driver/buffer circuit is required providing a
large current to charge/discharge the load
capacitance.
 It can be done by using large pMOS and nMOS transistors in the buffer placed
at each output of our design driving the heavy load.
 However, such a large buffer with large input capacitance would itself create the
loading effect for the design.

 Thus the effect of large load can be propagated to many gates preceding the
last-stage driver, as shown below:

where, the no. of stages (N) and size multiplying factor (a) at each stage is determined
𝑪
as: 𝒂(𝒍𝒐𝒈 𝒆 𝒂 − 𝟏) = 𝑪𝒅 and 𝑪𝒍𝒐𝒂𝒅 = 𝒂𝑵+𝟏 𝑪𝒈 here 𝐶𝑑 and 𝐶𝑔 are the drain and input
𝒈
capacitance of first stage inverter
Loading effect on Inverter performance with
increasing CL
Transient simulation result of an Inverter

CL Inverter’s functionality is lost for 10pF load

capacitance
Buffer design to increase the driving capability of Inverter
- The scaling factor a is determined
𝑪
by: 𝒂(𝒍𝒐𝒈 𝒆 𝒂 − 𝟏) = 𝑪𝒅
𝒈
- For a simple case, a is 2.718 when
𝑪𝒅 is negligible as compared to 𝑪𝒈 .
- Here, we have chose the scaling
factor of 3.
- Then, the number of stages N to
drive a load (𝑪𝒍𝒐𝒂𝒅 ) of 10pF is
found to be 6 by the relation:
𝑪𝒍𝒐𝒂𝒅 = 𝒂𝑵+𝟏 𝑪𝒈
- The simulation results are shown in
figure.