ECE 725 Spring 2022

HW #1
Due 4/11/23 (Tuesday) in-class

30% penalty if less than 2 days late, no later submission.

Cleary show how you solved each problem. If there are only answers, no points will be given.

The textbook is “CMOS VLSI Design” 4th Edition, Neil Weste, David Haris.

1. Work the problem 4.14 of the textbook (10 points).

2. Using the Radix-4 modified Booth encoding (modified booth recoding) algorithm, compute
the following multiplication of two positive numbers. (10 points)
3. Consider the 16-bit carry bypass adder and 16-bit carry select adder. Both adder schemes
are divided into four groups, where the 1st group has M1 bits, 2nd group has M2 bits, 3rd
group has M3 bits, and 4th group has M4 bits, and (M1+M2+M3+M4) = 16. Assume that
the setup delay (including the 4-input AND for carry bypass adder), 1-bit carry delay,
multiplexer delay, sum delay are all 100 ps. (20 points)

a) When M1=4, M2=4, M3=4, M4=4, calculate the delay of 16-bit carry-bypass adder
and carry select adder. Clearly show your computation, and draw the critical path
through each adder diagram.
<Carry Bypass Adder>

Bit 0 – (i-1) Bit i – (j-1) Bit j – (k-1) Bit k – 15

Setup Setup Setup Setup

Carry Carry Carry Carry

propagation propagation propagation propagation

Sum Sum Sum Sum

M1 bits M2 bits M3 bits M4 bits

<Carry Select Adder>

Bit 0 – (i-1) Bit i – (j-1) Bit j – (k-1) Bit k – 15

Setup Setup Setup Setup

0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry

Ci,0 Multiplexer Multiplexer Multiplexer Multiplexer

Co,i-1 Co,j-1 Co,k-1 Co,15

Sum Sum Sum Sum

M1 bits M2 bits M3 bits M4 bits

b) When M1=1, M2=4, M3=5, M4=6, calculate the delay of 16-bit carry-bypass adder
and carry select adder. Clearly show your computation, and draw the critical path
through each adder diagram.
 <Carry Bypass Adder>

Bit 0 – (i-1) Bit i – (j-1) Bit j – (k-1) Bit k – 15

Setup Setup Setup Setup

Carry Carry Carry Carry

propagation propagation propagation propagation

Sum Sum Sum Sum

M1 bits M2 bits M3 bits M4 bits

M1=1, M2=4, M3=5, M4=6

<Carry select adder>

Bit 0 – (i-1) Bit i – (j-1) Bit j – (k-1) Bit k – 15

Setup Setup Setup Setup

0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry

Ci,0 Multiplexer Multiplexer Multiplexer Multiplexer

Co,i-1 Co,j-1 Co,k-1 Co,15

Sum Sum Sum Sum

M1 bits M2 bits M3 bits M4 bits

 4. Work the problem 11.18 in the textbook. (10 points)

5. Using the method of logical effort, compute the minimum delay of the path from A to B in
figure below, and choose the gate sizes (x and y) of each stage to achieve this delay under
equal rise and fall times assumption. The first 2-input NAND gate presents an equivalent
load of 8C on the input, while the output load is equivalent of 45C.

Unit
V
Inverter
DD

2
a a
1