Department of Electronics and Communication

Engineering

Course File

Digital System Design

(EC303PC)

II Tech I Semester
Academic Year: 2022-2023

Ms. G Ranjitha
Assistant Professor, Department of ECE

Bhoj Reddy Engineering College for Women

Vinaynagar, IS Sadan Crossroads, Saidabad, Hyderabad – 500 059, Telangana.
 Bhoj Reddy Engineering College for Women
(Sponsored by Sangam Laxmibai Vidyapeet, approved by AICTE and affiliated to JNTUH)
Vinayanagar, IS Sadan Crossroads, Saidabad, Hyderabad – 500 059, Telangana. www.brecw.ac.in

Vision of Institution - BRECW

BRECW develops confident and articulative young women into dynamic Engineers
equipped with skills, knowledge, values and an attitude to contribute to the society.

Mission of Institution- BRECW

 BRECW is committed to providing a challenging, enriching, safe and supportive

technical learning environment through its core values of responsibility, respect
and compassion.
 Fosters intellectual, spiritual and personal development of young women so that
they develop the tools necessary to lead meaningful lives.
 Offers academic curriculum along with an extensive co-curricular program with the
support of dedicated staff who ensure that students identify their strengths and
develop their skills such as teamwork, leadership, creativity and entrepreneurship.
 Develops independent, adaptable thinkers with a passion for learning, courage to
take risks and initiative to apply what is learned.

Department of Electronics and Communication Engineering

Vision

 ECE department envisions developing technically competent and meritorious

women engineers with a keen sense of social responsibility.
Mission
 To provide a challenging and value-based education, enriching knowledge of
young engineers in the field of Electronics and Communication Engineering
 To strive for the intellectual and personal development of young women to build a
healthy society by improving the quality of life through the application of
Electronics.
 To inculcate self-confidence, teamwork, leadership, and entrepreneurship in
students through curricular, co-curricular and extracurricular activities.
 To develop adaptable thinking and the ability to apply the techniques of
communication innovatively in a realistic environment for the current and future
technological requirements.
Programme Educational Objectives of ECE Department

At the end of the program, the women engineers will be able to:

PEO1: Solve complex problems by using their expertise in analyzing and developing
potential models using modern scientific tools.
PEO2: Prioritize their professional development through interpersonal, leadership, and
social skills, catering to the needs of society with ethics and integrity.
PEO3: Exhibit sustained learning adapting to changing professional needs.

Department of ECE Programme Outcomes (POs)

1. Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.
3. Design-development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified
needs with appropriate consideration for the public health and safety, and the
cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge
and research methods including design of experiments, analysis and interpretation
of data, and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modeling to
complex engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
 8. Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and teamwork: Function effectively as an individual, and as a member
or leader in diverse teams, and in multidisciplinary settings.
10.Communication: Communicate effectively on complex engineering activities with
the engineering community and with society at large, such as, being able to
comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding
of the engineering and management principles and apply these to one’s own work,
as a member and leader in a team, to manage projects and in multidisciplinary
environments.
12. Life-long learning: Recognize the need for and have the preparation and ability
to engage in independent and life-long learning in the broadest context of
technological change.

Programme Specific Outcomes (PSOs)

PSO1: Able to design, develop and analyse systems in the field of Electronics,
Communications & Networking, Signal & Image processing, VLSI technology and
Embedded systems.
PSO2: Demonstrate expertise in the use of software and hardware required in real-life
applications.
Mapping of PEOs and POs-PSOs

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

PEO 1 √ √ √ √ √ √ √
PEO-2 √ √ √ √ √ √
PEO-3 √ √ √
Syllabus:

UNIT - I
Number Systems: Number systems, Complements of Numbers, Codes- Weighted and
Non-weighted codes and its Properties, Parity check code and Hamming code.
Boolean Algebra: Basic Theorems and Properties, Switching Functions- Canonical and
Standard Form, Algebraic Simplification, Digital Logic Gates, EX-OR gates, Universal
Gates, Multilevel NAND/NOR realizations

UNIT - II
Minimization of Boolean Functions: Karnaugh Map Method - Up to five Variables,
Don’t Care Map Entries, Tabular Method,
Combinational Logic Circuits: Adders, Subtractors, Comparators, Multiplexers,
Demultiplexers, Encoders, Decoders and Code converters, Hazards and Hazard Free
Relations.

UNIT - III
Sequential Circuits Fundamentals: Basic Architectural Distinctions between
Combinational and Sequential circuits, SR Latch, Flip Flops: SR, JK, JK Master Slave, D
and T Type Flip Flops, Excitation Table of all Flip Flops, Timing and Triggering
Consideration, Conversion from one type of Flip-Flop to another.
Registers and Counters: Shift Registers – Left, Right and Bidirectional Shift Registers,
Applications of Shift Registers - Design and Operation of Ring and Twisted Ring Counter,
Operation of Asynchronous and Synchronous Counters

UNIT - IV
Sequential Machines: Finite State Machines, Synthesis of Synchronous Sequential
Circuits- Serial Binary Adder, Sequence Detector, Parity-bit Generator, Synchronous
Modulo N –Counters. Finite state machine-capabilities and limitations, Mealy and Moore
models.

UNIT – V
Realization of Logic Gates Using Diodes & Transistors: AND, OR and NOT Gates
using Diodes and Transistors, DCTL, RTL, DTL, TTL, CML and CMOS Logic Families
and its Comparison, Classification of Integrated circuits, comparison of various logic
families, standard TTL NAND Gate Analysis & characteristics, TTL open collector O/Ps,
Tristate TTL, MOS & CMOS open drain and tristate outputs, CMOS transmission gate, IC
interfacing- TTL driving CMOS & CMOS driving TTL..

TEXTBOOKS:

1. Switching and Finite Automata Theory - Zvi Kohavi & Niraj K. Jha, 3rd Edition,
Cambridge, 2010.

2. Modern Digital Electronics – R. P. Jain, 3rd Edition, 2007- Tata McGraw-Hill

REFERENCE BOOKS:
 1. Digital Design- Morris Mano, PHI, 4th Edition,2006
2. Introduction to Switching Theory and Logic Design – Fredriac J. Hill, Gerald R.
Peterson, 3rd Ed, John Wiley & Sons Inc.
3. Fundamentals of Logic Design- Charles H. Roth, Cengage Learning, 5th, Edition,
2004.
4. Switching Theory and Logic Design – A Anand Kumar, PHI, 2013
 Bhoj Reddy Engineering College for Women
(Sponsored by Sangam Laxmibai Vidyapeet, approved by AICTE and affiliated to JNTUH)
Vinayanagar, IS Sadan Crossroads, Saidabad, Hyderabad – 500 059, Telangana. www.brecw.ac.in

COURSE INFORMATION SHEET

PROGRAMME: B. Tech - Electronics and DEGREE: UG
Communication Engineering
COURSE: Digital System Design YEAR and SEMESTER: II-I CREDITS:4
COURSE CODE: EC303PC COURSE TYPE: Theory
REGULATION: R18
COURSE AREA/DOMAIN: Digital System CONTACT HOURS: 4 hours / Week
Design
CORRESPONDING LAB COURSE CODE (IF LAB COURSE NAME: - Digital System
ANY): - EC307PC Design Lab
UNIT DETAILS HOURS
Number Systems: Number systems, Complements of Numbers,
Codes- Weighted and Non-weighted codes and its Properties,
Parity check code and Hamming code.
I Boolean Algebra: Basic Theorems and Properties, Switching
09
Functions- Canonical and Standard Form, Algebraic
Simplification, Digital Logic Gates, EX-OR gates, Universal
Gates, Multilevel NAND/NOR realizations

Minimization of Boolean Functions: Karnaugh Map Method -

Up to five Variables, Don’t Care Map Entries, Tabular Method,
Combinational Logic Circuits: Adders, Subtractors,
II 10
Comparators, Multiplexers, Demultiplexers, Encoders, Decoders
and Code converters, Hazards, and Hazard Free Relations.

Sequential Circuits Fundamentals: Basic Architectural

Distinctions between Combinational and Sequential circuits, SR
Latch, Flip Flops: SR, JK, JK Master Slave, D and T Type Flip
Flops, Excitation Table of all Flip Flops, Timing and Triggering
Consideration, Conversion from one type of Flip-Flop to another.
III 11
Registers and Counters: Shift Registers – Left, Right and
Bidirectional Shift Registers, Applications of Shift Registers -
Design and Operation of Ring and Twisted Ring Counter,
Operation of Asynchronous and Synchronous Counters

Sequential Machines: Finite State Machines, Synthesis of

Synchronous Sequential Circuits- Serial Binary Adder, Sequence
Detector, Parity-bit Generator, Synchronous Modulo N –
IV Counters. Finite state machine-capabilities and limitations, Mealy 8
and Moore models.

V Realization of Logic Gates Using Diodes & Transistors: AND, 7

OR and NOT Gates using Diodes and Transistors, DCTL, RTL,
DTL, TTL, CML and CMOS Logic Families and its Comparison,
Classification of Integrated circuits, comparison of various logic
 families, standard TTL NAND Gate Analysis & characteristics,
TTL open collector O/Ps, Tristate TTL, MOS & CMOS open drain
and tristate outputs, CMOS transmission gate, IC interfacing-
TTL driving CMOS & CMOS driving TTL..

TOTAL HOURS 45
Descriptive Tests 02
Topics beyond the Syllabus 02
Remedial classes 02
Tutorial classes 17
Total Number of Classes 68

COURSE PRE-REQUISITES:

1. Basic Concepts of Decimal Number Systems.

COURSE OBJECTIVE:
 To understand common forms of number representation in logic circuits
 To learn basic techniques for the design of digital circuits and fundamental
concepts used in the design of digital systems.
 To understand the concepts of combinational logic circuits and sequential circuits.
 To understand the Realization of Logic Gates Using Diodes & Transistors.

COURSE OUTCOMES: At the end of this course, students will demonstrate the ability to

CO1: Understand the numerical information in different forms and Boolean Algebra
theorems.

CO2: Minimization of Boolean function and understand various combinational circuits.

CO3: Design and analysis of sequential circuits

CO4: Analyze Finite State Machines.

CO5: Realization of logic gates using various logic families.

Mapping of COs with POs and PSOs:

PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO
1 2 3 4 5 6 7 8 9 0 1 2 1 2
CO
3 2 2 1 0 0 1 1 0 0 1 1 3 2
1
CO
2 3 3 2 2 0 1 1 0 0 1 1 2 2
2
CO
3 3 3 2 2 1 0 1 0 0 0 1 2 2
3
CO
2 1 2 2 1 0 0 0 0 0 0 0 3 2
4
CO
2 2 1 2 2 1 0 0 0 0 0 1 2 2
5
Note: 0-No match, 1-Poor, 2-Light, 3-High

GAPS IN THE SYLLABUS - TO MEET INDUSTRY/PROFESSION REQUIREMENTS:

S.No. DESCRIPTION PROPOSED ACTIONS
1 Binary, Octal, Hexadecimal, Arithmetic Assignment
2 Latest Automatic applications (Hardware) Student Seminar

PROPOSED ACTIONS: Topics beyond syllabus/assignment/industry visit/guest

lecturer/NPTEL etc.
TOPICS BEYOND SYLLABUS/ADVANCED TOPICS/DESIGN:
1 Universal Shift Register
2 Sequence Generator
WEB SOURCE REFERENCES:
S. No. Name of Book/Web cite
1 https://www.coursera.org
2 https://www.engineering.com/
3 https://nptel.ac.in/courses/
4 https://www.tutorialspoint.com
5 http://ieee.org/
DELIVERY/INSTRUCTIONAL METHODOLOGIES:
√ Chalk and Talk √ STUD. √ WEB
ASSIGNMENT RESOURCES
√ LCD/SMART √ STUD. ☐ ADD-ON
BOARDS SEMINARS COURSES
ASSESSMENT METHODOLOGIES-DIRECT
√ ASSIGNMENTS ☐ STUD. √ TESTS/MODEL √ UNIV.
SEMINARS EXAMS EXAMINATION
☐ STUD. LAB √ STUD. VIVA ☐ MINI/MAJOR ☐
PRACTICES PROJECTS CERTIFICATIONS
☐ ADD-ON ☐ OTHERS
COURSES
ASSESSMENT METHODOLOGIES-INDIRECT
√ ASSESSMENT OF COURSE OUTCOMES √ STUDENT FEEDBACK ON FACULTY
(BY FEEDBACK, ONCE) (TWICE)

☐ ASSESSMENT OF MINI/MAJOR ☐ OTHERS

PROJECTS BY EXT. EXPERTS
Prepared by staff Approved by HoD
G Ranjitha S Manjula
 Bhoj Reddy Engineering College for Women
(Sponsored by Sangam Laxmibai Vidyapeet, approved by AICTE and affiliated to JNTUH)
Vinayanagar, IS Sadan Crossroads, Saidabad, Hyderabad – 500 059, Telangana. www.brecw.ac.in

LESSON PLAN

Sub: Digital System Design Faculty Name: G Ranjitha

Date No. of
S. Cumulativ
Classe Teachin
No Name of the Topic e number
s g AID
. of periods
require
UNIT-I: Number System and Boolean algebra And Switching Functions
Introduction to Digital System
29-11-2022 Chalk &
1 Design: Decimal number 01 01
Talk
systems Binary number systems
Octal number system, Chalk &
2 30-11-2022 01 02
hexadecimal number system Talk
Tutorial : Problems on
3 30-11-2022 01 03 Practice
conversion of number systems
Complements of Numbers Chalk &
4 02-12-2022 01 04
Codes- Binary Codes Talk
Binary Coded Decimal Code and Chalk &
5 06-12-2022 01 05 Talk
its Properties
Unit Distance Codes, Error Chalk &
6 07-12-2022 01 06 Talk
Detecting and Correcting Codes
Tutorial: Problems on Error
7 07-12-2022 01 07 Practice
Detecting and Correcting Codes
Boolean Algebra Basic Boolean Chalk &
8 09-12-2022 01 08 Talk
Algebra Properties
Switching Functions, Canonical Chalk &
9 13-12-2022 and Standard Form Algebraic 01 09 Talk
equation
Simplification of Digital Logic Chalk &
10 14-12-2022 Gates Properties of XOR Gates, 01 10 Talk
Universal Gates
Tutorial: Problems on logic Practice
11 14-12-2022 01 11
gates
Multilevel NAND/NOR Chalk &
12 16-12-2022 01 12 Talk
realizations
13 20-12-2022 Remedial Class 01 13 Practice
UNIT-II: Minimization and Design of Combinational Circuits
The Minimization of Switching PPT
14 21-12-2022 01 14
Function
15 21-12-2022 Tutorial: Simple Problems 01 15 Practice
The Karnaugh Map Method-Up Chalk &
16 23-12-2022 01 16 Talk
to Five Variable Maps
17 27-12-2022 Don’t Care Map Entries 01 17 Chalk &
 Talk
18 28-12-2022 Tabular Method 01 18
Chalk &
Talk
Tutorial: Problems on Tabular Practice
19 28-12-2022 01 19
method
Design of Combinational Logic Chalk &
20 30-12-2022 01 20 Talk
Adders, Subtractors
21 03-01-2023 Comparators 01 21
Chalk &
Talk
22 04-01-2023 Demultiplexer, Multiplexers 01 22
Chalk &
Talk
Tutorial: Design of Practice
23 04-01-2023 Combinational Logic using 01 23
adders, comparators
24 06-01-2023 Encoders, Decoders 01 24
Chalk &
Talk
25 10-01-2023 Code Converters 01 25
Chalk &
Talk
26 11-01-2023 Hazards, Hazard Free Relations 01 26
Chalk &
Talk
Tutorial: Design of Practice
27 11-01-2023 Combinational Logic using 01 27
decoders & multiplexers
28 13-01-2023 Descriptive Test -I 01 28 -
UNIT-III: Sequential Circuit Fundamentals and Applications
Introduction: Basic Architectural PPT
Distinctions between
29 17-01-2023 01 29
Combinational and Sequential
circuits
Fundamentals of Sequential Chalk &
30 18-01-2023 01 30 Talk
Machine Operation
31 18-01-2023 Tutorial: Design of SR Latch 01 31 Practice
Flip Flops SR, JK Chalk &
32 20 -01-2023 32 Talk
Race Around Condition in JK
D and T Type Flip Flops, Practice
33 24 -01-2023 01 33
Excitation Table of all Flip Flops
34 25 -01-2023 Design of a Clocked Flip-Flop 01 34 PPT
Tutorial: Timing and Triggering Practice
35 25 -01-2023 01 35
Consideration
Conversion from one type of PPT
36 31 -01-2023 01 36
Flip-Flop to another
Registers and Counters: Shift Chalk &
37 01 -02-2023 Registers Data Transmission in 01 37 Talk
Shift Registers
Tutorial: Conversion from one Practice
38 01 -02-2023 01 38
to other type of Flip-Flops
Operation of Shift Registers, PPT
39 03 -02-2023 01 39
Shift Register Configuration
Bidirectional Shift Registers, Chalk &
40 07 -02-2023 01 40 Talk
Applications of Shift Registers
41 08 -02-2023 Universal Shift Registers 01 41 PPT
42 08 -02-2023 Tutorial: Shift Registers 01 42 Practice
Design and Operation of Ring Chalk &
43 10-02-2023 01 43 Talk
Counter, Twisted Ring Counter
Operation of Synchronous Chalk &
44 13 -02-2023 Counters and Asynchronous 01 44 Talk
Counters
45 15 -02-2023 Remedial Class 01 45 Practice
Tutorial: Synchronous Counters Practice
46 15 -02-2023 01 46
and Asynchronous Counters
UNIT-IV : Sequential Machines
Introduction to FSM, Analysis of PPT
47 17 -02-2023 01 47
Synchronous Sequential Circuits
Approaches to the Design of PPT
48 20 -02-2023 Synchronous Sequential Finite 01 48
State Machines
Synthesis of Synchronous Chalk &
49 22 -02-2023 Sequential Circuits, Serial Binary 01 49 Talk
Adder
Tutorial: Sequential Circuits,
50 22 -02-2023 01 50 Practice
Serial Binary Adder
Chalk &
51 24 -02-2023 Sequence Detector 01 51
Talk
Parity-bit Generator Chalk &
52 27 -02-2023 52
Talk
Finite state machine-capabilities
Chalk &
53 01 -03-2023 and limitations, Mealy and 01 53
Talk
Moore models
Design of Asynchronous
Chalk &
54 01 -03-2023 Counters 01 54
Talk

Tutorial: Asynchronous
55 03 -03-2023 01 55 Practice
Counters
Design of Synchronous Modulo Chalk &
56 06 -03-2023 01 56
N – Counters Talk
Beyond Syllabus: Sequence
57 08 -03-2023 01 57 Practice
generator
UNIT-V : Realization of Logic Gates using Diode & Transistor
Tutorial : Introduction to AND, Practice
58 08 -03-2023 OR, NOT gates using diode, 01 58
transistor
59 10 -03-2023 IC Classification, standard TTL 01 59 PPT
01 Chalk &
60 13 -03-2023 RTL,DTL.TTL.DCTL,ECL Logic 60
Talk
61 CMOS Logic families and 61 Chalk &
15 -03-2023 01 Talk
comparison
Tutorial: NAND gate analysis & Practice
62 15 -03-2023 01 62
characteristics
TTL open collector’s O/PS Chalk &
63 17 -03-2023 01 63
Talk
64 20 -03-2023 MOS & CMOS open drain and 01 64 Chalk &
 tristate outputs Talk
CMOS transmission gates 01 Chalk &
65 24 -03-2023 65
Talk
IC Interfacing 01 Chalk &
66 27 -03-2023 66
Talk
67 Descriptive test- II 01 67 Chalk &
29 -03-2023
Talk
68 29 -03-2023 Tutorial: Revision 01 68 Practice
 Bhoj Reddy Engineering College for Women
(Sponsored by Sangam Laxmibai Vidyapeet, approved by AICTE and affiliated to JNTUH)
Vinayanagar, IS Sadan Crossroads, Saidabad, Hyderabad – 500 059, Telangana. www.brecw.ac.in

Lecture Plan with Blooms Taxonomy

Name of the Subject : Digital System Design

Subject Code : EC303PC
Name of the Faculty Member : G Ranjitha
Class & section : II ECE-B BTL- Blooms Taxonomy Level:
Level 1- Remembering
Level 2- Understanding
Level 3 - Applying
Level 4 - Analyzing
Level 5 - Evaluating
Level 6 - Creating
Cumulative Time Topics BT Teaching
Periods (Min) L –
Learning
Method
03 Attendance L-1 Talk
17 Overview of Syllabus L-2 Chalk &
1 Talk
20 Introduction to Digital System Design L-2 Chalk &
Talk
20 Decimal number systems Binary number L-2 Chalk &
systems Talk
10 Attendance Recalling previous topics L-1 Talk
2 50 Octal number system, hexadecimal number L-2 Chalk &
system Talk
10 Attendance Recalling previous topics L-1 Talk
50 Problems on conversion of number systems L-3 Chalk
3 Talk &
Practice
10 Attendance; Recalling previous concepts L-1 Chalk &
Talk
4 20 Complements of Numbers Codes L-2 Chalk &
Talk
20 Binary Codes- Classification with example L-2, Chalk &
L-4 Talk
10 Weighted and non-weighted codes L-2 Chalk &
Talk
10 Attendance; Recalling previous concepts L-1 Talk
10 Binary Coded Decimal Code and its L-3 Chalk &
 5 Properties Talk
20 Excess-3 code and its arithmetic’s L-2, Chalk &
L-4 Talk
20 Problems on codes L-2, Chalk &
L-4 Talk
10 Attendance; Recalling previous concepts L-1 Talk
6 20 Unit Distance Codes L-3 Practice

10 Clarification of doubts L-4 Practice

10 Attendance; Recalling previous concepts L-1 Talk
7 20 Error Detecting (Parity) L-2 Chalk &
Talk
20 Error Detecting and Correcting Codes L-4 Chalk &
Talk
10 Hamming code problems L-2 Chalk &
Talk
10 Attendance; Recalling previous concepts L-1 Talk
8 50 Boolean Algebra Basic Boolean Algebra L-2 Chalk &
Properties Talk

10 Attendance; Recalling previous concepts L-1 Talk

20 Switching Functions L-2 Chalk &
9 Talk
20 Canonical and Standard Form Algebraic L-2 Chalk &
equation Talk
10 Problems on std form for SOP&POS L-4 Chalk &
Talk
10 10 Attendance; Recalling previous concepts L-1 Talk
20 Simplification of Digital Logic Gates L-4 Practice
20 Properties of XOR L-4 Practice
10 Universal Gates L-4 Practice
11 10 Attendance; Recalling previous concepts L-1 Practice
20 Multilevel NAND/NOR realizations L-2 Practice
30 Problems on Multilevel NAND/NOR L-2 Practice
realizations
12 60 Remedial class L-2 Practice
UNIT-II
10 Attendance; Recalling previous concepts L-1 Talk
13 50 The Minimization of Switching Function L-2 PPT

10 Attendance; Recalling previous concepts L-1 Talk

14 50 The Karnaugh Map L-2 PPT
L-2 PPT
L-2 PPT
15 10 Attendance; Recalling previous concepts L-1 Talk
20 Method-Up to Five Variable Maps L-2, Chalk &
L-4 Talk
 30 Problems on 5 variable map L-2, Chalk &
L-4 Talk
L-2, Chalk &
L-4 Talk
10 Attendance; Recalling previous concepts L-1 Talk
16 20 Don’t Care Map Entries L-2 Chalk &
Talk

30 BCD Using don’t care L-3 Chalk &

Talk
10 Attendance; Recalling previous concepts L-1 Talk
17 20 Tabular Method procedure L-2, Chalk &
L-4 Talk
30 Problems on Tabular Method L-2, Chalk &
L-4 Talk
L-2, Chalk &
L-4 Talk
10 Attendance; Recalling previous concepts L-1 Talk
18 25 Design of Combinational Logic Adders L-2 Chalk &
Talk
L-2 Chalk &
Talk
25 Design of Combinational Logic Subtractors L-2 Chalk &
Talk
10 Attendance; Recalling previous concepts L-1 Talk
19 20 Full adder using 2 half adders L-2 Chalk &
Talk
30 1 ,2,4 - bit magnitude Comparators L-2, Chalk &
L-3 Talk
10 Attendance; Recalling previous concepts L-1 Talk
20 20 Concept of Demultiplexer L-2 Chalk &
Talk
30 Concept of Multiplexers L-2 Chalk &
Talk
Implementation of Mux L-2 Chalk &
Talk
21 10 Attendance; Recalling previous concepts L-1 Talk
10 Encoders L-2 Chalk &
Talk
40 Decoders L-4 Chalk &
Talk
L-4 Chalk &
Talk
22 10 Attendance; Recalling previous concepts L-1 Talk
10 Introduction to Code Converters L-2 Chalk &
Talk
20 Binary to gray L-2 Chalk &
Talk
20 BCD to binary,BCD to ex-3 L-2 Chalk &
 Talk
23 10 Attendance; Recalling previous concepts L-1 Talk
50 Design of Combinational Logic L-1 Practice
24 60 Design of Combinational Logic using Practice
decoders & multiplexers
25 60 Descriptive
UNIT-III
10 Attendance; Recalling previous concepts L-1 Talk
50 Introduction: Basic Architectural Distinctions L-2 PPT
26 between Combinational and Sequential
circuits
10 Attendance; Recalling previous concepts L-1 Talk
50 Fundamentals of Sequential Machine L-2 Chalk &
27 Operation Talk
10 Attendance; Recalling previous concepts L-1 Talk
50 Flip Flops SR, JK L-2 Chalk &
28 Race Around Condition in JK Talk
10 Attendance; Recalling previous concepts L-1 Talk
20 D and T Type Flip Flops, L-2 Practice
29 30 Excitation Table of all Flip Flops L-3 Practice
10 Attendance; Recalling previous concepts L-1 Talk
30 50 Design of a Clocked Flip-Flop L-4 PPT
10 Attendance; Recalling previous concepts L-1 Talk
31 50 Timing and Triggering Consideration L-2 PPT
10 Attendance; Recalling previous concepts L-1 Talk
32 50 Conversion from one type of Flip-Flop to L-4 Chalk &
another Talk
10 Attendance; Recalling previous concepts L-1 Talk
33 50 Registers and Counters: Shift Registers Data L-2 PPT
Transmission in Shift Registers
34 10 Attendance; Recalling previous concepts L-1 Talk
20 Introduction and Operation of Shift Registers L-2 Chalk &
Talk
20 Shift Register Configurations L-2 Chalk &
Talk
10 SISO ,PIPO ,PISO ,SIPO L-1 Chalk &
Talk
35 10 Attendance; Recalling previous concepts L-1 Talk
50 Bidirectional Shift Registers, Applications of L-4 PPT
Shift Registers
36 10 Attendance; Recalling previous concepts L-1 Talk
50 Design and Operation of Ring Counter, L-4 Chalk &
Twisted Ring Counter Talk
37 10 Attendance; Recalling previous concepts L-1 Talk
50 Synchronous Counters L-2 Practice
38 10 Attendance; Recalling previous concepts L-1 Talk
50 Operation of Synchronous Counters L-3 Chalk &
Talk
 39 60 Asynchronous Counters L-3 Practice
UNIT-IV
10 Attendance; Recalling previous concepts L-1 Talk
20 Introduction to FSM L-3 PPT
40 30 Analysis of Synchronous Sequential Circuits

10 Attendance; Recalling previous concepts L-2 Talk

41 50 Approaches to the Design of Synchronous L-3 PPT
Sequential Finite State Machines

10 Attendance; Recalling previous concepts L-1 Talk

20 Synthesis of Synchronous Sequential Circuit L-2 Chalk &
Talk
42 20 Serial Binary Adder L-2 Chalk &
Talk
10 Sequence Detector L-2 Chalk &
Talk
10 Attendance; Recalling previous concepts L-1 Talk
50 Parity-bit Generator L-2 Chalk &
43 Talk

10 Attendance; Recalling previous concepts L-1 Talk

50 Finite state machine-capabilities and L-2 Chalk &
44 limitations, Mealy and Moore models Talk
10 Attendance; Recalling previous concepts L-1 Talk
50 Design of Asynchronous Counters L-4 Chalk &
45 Talk

10 Attendance; Recalling previous concepts L-1 Talk

46 20 Decade Counter L-3 Chalk &
Talk
30 Design of Synchronous Modulo N – Counters L-4 Chalk &
Talk
10 Attendance; Recalling previous concepts L-1 Talk
47 50 L-4 Practice
Sequence generator

48 10 Attendance; Recalling previous concepts L-1 Talk

50 Problems on sequential circuit L-4 Practice
49 10 Attendance; Recalling previous concepts L-1 Talk
50 Problems on overlap and non-overlap L-3 Practice
sequence detector
50 10 Attendance; Recalling previous concepts L-1 Talk
50 Design of up-down counter L-3 Practice

10 Attendance; Recalling previous concepts L-1 Talk

51 10 Introduction to Logic families L-2 PPT
 20 Introduction to AND, OR, NOT gates using L-2 Chalk &
diode, Talk
20 AND, OR, NOT gates using transistor logic L-2 Chalk &
Talk
10 Attendance; Recalling previous concepts L-1 Talk
52 20 IC Classification L-2 Chalk &
Talk
20 standard TTL logic circuit L-2 Chalk &
Talk
10 DCTL Logic L-2 Chalk &
Talk
10 Attendance; Recalling previous concepts L-1 Talk
53 30 RTL,ECL,DTL,TTL L-2 Practice
20 IC parameter comparison

10 Attendance; Recalling previous concepts L-1 Talk

54 50 CMOS Logic families L-2 Practice

10 Attendance; Recalling previous concepts L-1 Talk

55 50 NAND gate analysis & characteristics L-4 Chalk &
Talk

56 10 Attendance; Recalling previous concepts L-1 Talk

50 TTL open collector’s O/PS L-3 Chalk &
Talk

57 10 Attendance; Recalling previous concepts L-1 Talk

50 MOS & CMOS open drain and tristate L-2 Practice
outputs
58 10 Attendance; Recalling previous concepts L-1 Talk
50 CMOS transmission gates L-3 Chalk &
Talk

59 10 Attendance; Recalling previous concepts L-1 Talk

50 IC Interfacing L-2 Chalk &
Talk

60 60 Descriptive Test -
61 60 Remedial class L-1 Practice

Number of classes =36

Tutorial Classes = 17
Classes for Beyond Syllabus -2, Remedial Classes -3, Descriptive Tests -2,
Gaps in the syllabus -1 = 08
Total Number of Classes = 61
 Bhoj Reddy Engineering College for Women
(Sponsored by Sangam Laxmibai Vidyapeet, approved by AICTE and affiliated to JNTUH)
Vinayanagar, IS Sadan Crossroads, Saidabad, Hyderabad – 500 059, Telangana. www.brecw.ac.in

Question Bank with Blooms Taxonomy Level (BTL)

Academic Year : 2022-23
Subject Name with code : Digital System Design EC303PC
Class : II ECE - C
Name of the Faculty Member : Nikhat Parvin

Blooms Taxonomy Levels (BTL)

1. Remembering
2. Understanding
3. Applying
4. Analyzing
5. Evaluating
6. Creating

Sl. Questions BTL Course

No. (Select Questions from University question Bank and level Outcom
mention year in bracket or you may give own standard (Please e
question with (new) in bracket) mention (Please
L1 or L2 mention
or etc...) CO1 or
CO2
etc…)
Unit - I
Part – A (2 Marks )
1 L-2 CO 1
Prove that the Gray code is reflecting code

2 Define logic gates? L-1 CO 1

3 Write truth table of special purpose gates? L-1 CO 1
4 Why NAND, NOR gates called as universal gates? L-2 CO 1
5 Give the formula to find the number of parity bits L-1 CO 1
required for hamming code?
6 Define cyclic codes? L-1 CO 1
7 Write the properties of XOR gates L-1 CO 1
8 What is demorgans theorem? L-1 CO 1

9 Explain duality function? L2 CO 1

10 Perform the addition of 35 and 97 using EX-3 code L-2 CO 1

11 Explain all the logic gates? L-1 CO 1
Part – B (5 Marks )

Implement the following boolean function with NAND

1 L-4 CO 1
gates only.
F(X,Y,Z) = Σm(1,2,3,4,5,7)
Convert the following expressions into sum of products
2 and product of sums. L-3 CO 1
i) (AB+C)(B+C'D) ii) x'+x(x+y')(y+z')
Given 2 binary numbers X=1010100(2) and Y=
3 1000011(2). Perform i) X- Y ii) Y-X L-2 CO 1
using 2's complement method.
Perform the following conversions.
4 i) AB(16) = ( )10 ii) 1234(8) = ( )10 L-2 CO 1
iii) 456(8) = ( )2 iv) 100011001(2) = ( )16
i) Find the 16’s complement of BABA.
ii) Convert BABA to binary
5 iii) Find 2’s complement of result in (b) L-2 CO 1
iv)Convert the answer in(c) to hexadecimal and
compare with the answer in (a)
Encode the following message bits into 7-bit even parity
6 hamming code. L-3 CO 1
i) (1001)2 ii) (1110)2
Obtain the dual of the following functions. i) F=A′B+A L-4 CO 1
′BC′+A′BCD+A′B(CDE) ′
ii) F=AB+(AC)′AB′C
7
Show that the dual of the exclusive – OR is equal to its
complement

Unit – II
Part – A (2 Marks )
1 Compare K Map and Tabular method of minimization L-1 CO 2
2 What is a Decoder L-4 CO 2
3 Write about prime implicants and essential prime L-1 CO 2
implicants
4 Draw the block diagram of 2:1 Multiplexers L-3 CO 2
5 Explain about static and dynamic hazards L-3 CO 2
6 What is the necessity of priority encoder L-4 CO 2
7 Define encoder L-3 CO 2
8 Compare encoder, decoder multiplexer and CO 2
L-1
demultiplexer
9 Differentiate combinational and sequential circuit L-1 CO 2
10 Elaborate the importance of Gray code L-4 CO 2
Part – B (5 Marks )
Implement the following functions on decoder logic. CO 2
Y1= Σ(0,1,3,6,7)
1 Y2=Π(0,2,4,7) L-3
Y3= Π(1,3,6,7
 Implement a Boolean function F(A,B,C)= Σ(3,4,5,7)
2 L-4 CO 2
using a 4X1 Mux
3 Design a BCD to Excess-3 code converter L-4 CO 2

4 Design 4-bit comparator using logic gates L-3 CO 2

5 Design a Full adder using multiplexer. L-3 CO 2
6 Design BCD to Decimal decoder L-3 CO 2
Simplify the following Boolean function using Tabular CO 2
7 method. L-3
F(A,B,C,D)=Σm(0,1,2,5,7,8,9,10,13,15)
Determine the Prime and essential prime implicants of CO 2
the following function.
8 L-4
F(A,B,C,D)=(0,2,3,5,7,8,10,11,14,15)

Unit – III
Part – A (2 Marks )
1 Define setup and hold times. L-1 CO 3
2 What is meant by Clock Skew L-1 CO 3
3 Explain the term race around condition L-2 CO 3
4 Write characteristic table of SR &JK Flipflop L-2 CO 3
5 What is the procedure to convert SR ff to T ff L-2 CO 3
6 Define Asynchronous Sequential Circuits L-4 CO 3
7 Compare synchronous Sequential & Asynchronous L-2 CO 3
Sequential Circuits
8 Draw the diagram of master slave flipflop L-1 CO 3
9 What is difference between SR &JK Flipflop L-1 CO 3
10 Define latch ,flipflop L-1 CO 3
Part – B (5 Marks )
Explain 3-bit bi-directional shift register with a neat CO 3
1 L-2
diagram
Draw a neat circuit diagram of a 3-bit Johnson counter. CO 3
2 L-2
Draw the relevant output waveforms
Design a counter with the following repeated binary CO 3
3 L-4
sequence:1,3,,5,7,1.. using D flip-flops
Design a 3-bit ripple up/down counter. Draw its timing CO 3
4 L-4
diagrams
What is race around condition? How does it get CO 3
5 L-3
eliminated in a Master – slave JK flip-flop?
Describe 4-bit Universal shift register with a neat CO 3
6 L-2
diagram
Obtain the characteristic equations of JK, SR, D and T CO 3
7 flip-flops. Also explain excitation tables of all these flip- L-3
flops.
8 Do the following conversions L-3 CO 3
a) RS to JK, T and D
b) JK to RS, T, and D
c) T to JK, RS and D
 d) D to JK, RS, and T
Unit – IV
Part – A (2 Marks )
1 Define FSM L-1 CO 4
2 List out the capabilities and limitation of FSM. L-1 CO 4
3 Differentiate between Mealy and Moore machines L-3 CO 4
4 Write about lock out conditions in counter L-1 CO 4
5 Define counter L-2 CO 4
6 Give the classification of counters
Part – B (5 Marks )
Design a sequence generator using JK Flipflop to CO 4
1 L-4
generate the sequence 1101011
2 Design a Synchronous binary UP / DOWN Counter. CO 4
L-3
Draw its timing diagrams
Design a sequence detector for finding the sequence of CO 4
3 L-4
1111 when non overlapping is allowed
Design a sequence detector for finding the sequence of CO 4
4 L-4
1111 when overlapping is allowed.
5 esign a counter with the following repeated binary L-4 CO 4
sequence: 0,2,4,6,0,2.... using D flip-flops.
Unit – V
Part – A (2 Marks )
1 Classify various logic families. L-2 CO 5
2 What is figure of merit L-1 CO 5
3 Why TTL logic is preferred over other logics L-2 CO 5
4 Define (i)noise immunity (ii)fanout(iii) transition time (iv) L-1 CO 5
propagation delay (v)fan in
5 Draw AND OR NOT gate using diode and transistor L-1 CO 5

Part – B (5 Marks )
Explain with the aid if circuit diagram, the operation of a CO 5
1 L-3
TTL3 input NAND gate?
Explain the parameters used to characterize logic CO 5
2 L-3
families?
3 Draw the circuit diagram to interface TTL to CMOS? L-2 CO 5
Draw a TTL circuit with open collector output.? CO 5
4 L-2
Draw a TTL circuit with totem pole output and explain its CO 5
5 working? L-2

Explain the working of (a)CMOS NAND (b) CMOS NOR CO 5

6 L-2
gate?

Signature of the Course Instructor

Name:
Verified by: Dr J Madhavan
 1. Course Coordinator :
2. Module Coordinator :
3. Department coordination committee Head :

Tutorial Classes

S. No. Date Topic delivered Teaching HOD Sign

AID
UNIT-I: Number System and Boolean algebra And Switching Functions
1 02-12-2022 Practice
Number Systems
2 09-12-2022 Practice
Binary weighted codes
3 16-12-2022 Practice
Boolean Laws
UNIT-II: Minimization and Design of Combinational Circuits
23-12-2022 Practice
Karnaugh map
4
5 30-12-2022 Multiplexer Practice
6 06-01-2023 Decoders Practice
7 13-01-2023 Encoders Practice
UNIT-III: Sequential Circuit Fundamentals and Applications
8 20-01-2023 All flipflops Practice
9 27-01-2023 Design of counter Practice

10 03-02-2023 Shift Registers Practice

11 10-02-2023 Johnson counter Practice

UNIT-IV: Sequential Machines
12 17-02-2023 Modulo N Counter Practice
13 24-02-2023 Sequence detector Practice
14 03-03-2023 Synchronous counters Practice
UNIT-V: Realization of Logic Gates using Diode & Transistor
15 10-03-2023 AND, OR, NOT gates using diode, Practice
transistor
16 17-03-2023 NAND ,NOR EXOR EXNOR gates Practice
using diode, transistor
17 24-03-2023 Totem pole output Practice
 BHOJ REDDY ENGINEERING COLLEGE FOR
WOMEN

Assignment Questions with Blooms Taxonomy Level (BTL)

Academic Year : 2022-23
Subject Name with code : Digital System Design EC303PC
Class & Section : II ECE-C
Name of the Faculty Member : Nikhat Parvin
Blooms Taxonomy Levels (BTL)
1. Remembering
2. Understanding
3. Applying
4. Analyzing
5. Evaluating
6. Creating
BTL Course
level Outcom
Sl.No. (Please e
Questions mention (Please
L1 or L2 mention
or etc...) CO1 or
CO2
etc…)
Unit - I
1 Simplify the following expressions using boolean L-2 CO 1
algebra.
i) ABCD'+A'BCD+CD' ii) (A+B')(A'+B'+D)(B'+C'+D')
2 Show that the dual of the exclusive – OR is equal L-3 CO 1
to its complement.
Add and subtract the following in binary. L-2 CO 1
3 i) 1111 and 1010 ii) 100100 and 10110
iii) 110110 and 11101010 iv) 1101001 and 11011
Convert the following to the required form.
4 i) A616= ( )8 ii) (1FFF)16=( )12 L-2 CO 1
iii) (101001.001)2= ( )10 iv) (1264)8 = ( )10
Unit – II
1 Simplify the following boolean function using
Tabular method. L-2 CO 2
F(A,B,C,D)=Σm(0,1,2,5,7,8,9,10,13,15)
2 Simplify the following boolean function using K-map L-2 CO 2
method. F(w,x,y,z) = Σm(0,1,2,4,5,6,8,9,12,13,14)
3 Implement the following functions using a decoder. L-2 CO 2
F1= Σ(1,2,3,5)
F2= Π(0,2,6,7)
F3= Σ(3,4,5,7)
4 Realize a Full adder using 3X8 decoder L-4 CO 2
 Unit – III
1 What is race around condition? How does it get L-1 CO 3
eliminated in a Master – slave JK flip-flop?
2 Explain the operation of negative edge triggered JK L-2 CO 3
flip-flop with active low preset and clear inputs
Realize JK Flipflop using SR flip flop, D flip-flop and
3 L-3 CO 3
T flip-flop
Draw a neat circuit diagram of a 3-bit Jhonson
4 L-2 CO 3
counter. Draw the relevant output waveforms
Unit – IV
1 Define FSM. List out the capabilities and limitation L-1 CO 4
of FSM.

2
Design a sequence detector for finding the
L-3 CO 4
sequence of 1010(overlapping)

3 Differentiate between Mealy and Moore machines. L-2 CO 4

Design a Synchronous binary UP / DOWN Counter.

4 L-3 CO 4
Draw its timing diagrams
5 Design a Synchronous counter with the following
repeated binary sequence 0,2,4,6,0 ….using T Flip L-3 CO 4
flops
Unit – V
1 Draw a TTL circuit with open collector output.? L-2 CO 5
2 Draw a TTL circuit with totem pole output and L-2 CO 5
explain its working?
3 Draw AND OR NOT gate using diode and transistor
L-1 CO 5
4 Write notes on (i)noise immunity (ii)fanout(iii)
transition time (iv) propagation delay (v)fan in(vi) L-1 CO 5
figure of merit
5 Draw the circuit diagram to interface CMOS to
TTL? L-1 CO 5