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Vlsippt 151008171253 Lva1 App6891
Vlsippt 151008171253 Lva1 App6891
ASET
POWER DISSIPATION
The AID refers to the power consumed by the execution units and memory. This
component is fundamental to a given algorithm and is the prime factor for comparison
between different algorithms as well as for the qualifying the effect of algorithm level
design decisions.
To estimate the capacitance switched at this level it is necessary to ignore the
statistics of the applies data and to employ a white noise model i.e. random data.
Switching statistics are strongly influenced by the hardware architecture. The mapping
of operators onto the hardware resources effects the temporal correlations between
signals.
ASET
Since this overhead is not essential to the basic functionality of a given algorithm,
several estimation tools ignore its effect for algorithm level comparisons. The
power consumed by these components is often comparable if not greater than the
AID.
So, its important to get reasonable estimates of the implementation overhead for
realistic comparisons algorithms and to guide high level decisions.
ASET
The implementation dependant power consumption is strongly correlated to a number of
properties of the algorithm. For example, structural property of an algorithm may affect
the amount of his overhead is the locality of reference.
SPATIAL LOCALITY TEMPORAL LOCALITY
1. It refers to the extent to which an 1. It refers to the average lifetimes of
alog. can be partitioned into natural
clusters based on connectivity.
variables.
2. A spatially local alog. renders itself more 2. It tends to require less temporary
easily to efficient partitioning on Storage and have small registers files
hardware, allowing highly capacitive leading to lower capacitances.
global buses to be used sparingly.
3. It refers to the probability of future
3. In terms of memory/registers access, access to items referenced in the
spatial locality refers to the distance
between the address of items referenced
past.
close together in time.
4. Its does not allow any portioning
4. A spatially local memory access pattern of memory into smaller blocks.
allows portioning of memory into smaller
blocks that require less power per access.
ASET
After examining methods for estimating power consumption at the algorithm level,
The next logical step is to examine power minimization techniques at this level.
2. Avoiding Wasteful Activity: At the algorithm level the size and complexity of a given
algorithm(operation counts word lengths) determine the activity. If there are several
algorithm for a given task the one with least number of operations is preferable.
ASET
Spatial Locality can be detected and used to guide portioning . Regular algorithm
typically require less control and interconnect overhead.
Other way to reduce the implementation overhead is to reduce the chip area as
this typically translates into reduced bus capacitances.
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