ESQUEMA ELECTRICO HP Pavilion 15-R Compal LA-B972P ASO56 Rev 1.0

A B C D E
1 1
Compal LA-B972P
2
Hasswell M/B Schematics Document 2
Intel ULV Processor with DDRIIIL

Date : 2014-02-08
Rev 1.0
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
T H I S S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N I C S , INC. A N D C O N T A I N S CONFIDENTI
Cover Page
SSAiLze Document Number Rev
A N D T R A D E S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O M P E T E N T DIVISION O F R & D
B
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , INC. N E I T H E R T H I S S H E E T N O R T H E I N F O R M A T I O N IT C O N T A I N S
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C T R O N I C S , INC.
LA-B972P 0.1
Date: Thursday, March 20, 2014 Sheet 1 of 54
A B C D E
A B C D E
Model Name : Haswell

File Name : LA-972P Rev 1.0 VRAM*4 Nvidia PCI-Ex4
Lane 7-Lane10
Single Rank N15V-GM
PCIe 2.0:5Gb/s
1
17W PCIe 3.0:8Gb/s 1
P37~P40 P32~P36 DDR3-SO-DIMM X 2
Dual Channel
P15,16
eDPx2 DDR3L 1600MHz 1.35V
LVDS panel RTD2132R
P20 P18 2.7Gb/s
Haswell SATA 3.0 Port 0
2.5" SATA HDD P22
CRT Conn
DDI Ultra Light & Thin GEN1 1.5Gb/s
IT6513 GEN2 3Gb/s Port 1
P29 P29 GEN3 6Gb/s ODD P22
1168P BGA
HDMI USB3.0
HDMI Conn 5Gb/s
DDPB port P19 222.75MHz (USW ULT) USB2.0 Port 0 Port 0
480Mb/s USB3.0 port P26
2 2
PCI-E Card reader Lane 4 PCI-E Port 1

USB2.0 port P26
RTS5239 P25 PCIe 1.0:2.5Gb/s
PCIe 2.0:5Gb/s
Port 2
10/100 1G LAN Lane 5 USB2.0 Port P27
8151/8166 Option P24
Port 3
Lane 11 PCIe 1.0:2.5Gb/s WLAN P20
PCIe 2.0:5Gb/s
WLAN(MiniPCIe slot) PCI-E
P23 Port 4
Camera P19
Port 5
Touch Screen P19
Port 3 Port 3 (Reserved) USB2.0
3 480Mb/s 3
SMBUS
1MHz
Int.KBD ENE KB9012 LPC

PS2 33MHz HDA Aduio codec
Touch Pad P30 HDA 24MHz
ALC3227 Internal SPK
FAN P25
TPM 1.2 @
Lid switch SLB 9656 P28 Combo Jack
SPI
4
50MHz 4
SPI ROM
8M P7
T HIS SHEET OF ENGINEERING DRAW ING IS T HE PROPRIET ARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTSSIAizLeDocument Number
Block Diagrams
Rev
AND T RADE SECRET INFORMAT ION. T HIS SHEET MAY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COMPET ENT DIVISION OF R&D
Custom 0.1
DEPART MENT EXCEPT AS AUT HORIZED BY COMPAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORMAT ION IT CONT AINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PART Y W IT HOUT PRIOR W RIT TEN CONSENT OF COMPAL ELECT RONICS, INC.
LA-B972P
Date: T hursday, March 20, 2014 Sheet 2 of 54
A B C D E
5 4 3 2 1
CMSRC ACDRV
B+
DC IN ACFET RBFET
D D
+3VALWP Jumper +3VALW

RT8243 SY8003 UMA only
+1.5VSP Jumper +1.5VS
Charger
BQ24738 SUSP#
Jumper +5VALW EN
+5VALWP
EC_ON
EN
BATDRV +1.35V_VDDQP Jumper +1.35V_VDDQ

RT8207M
Battery RBFET
BATT
+0.6V_0.675VSJPumper +0.6V_0.675VS
SYSON
EN
SUSP#
C C
SY8208D
+1.05VSP Jumper +1.05VS
SUSP#
EN
TPS51622
+VCC_CORE
VR12.5_VR_ON
EN
B B
RT8813 DIS only

+VGA_CORE
GPU_PWR_EN
EN
SY8208D DIS only

+1.5VDIS Jumper +1.5VS
SUSP#
EN
A A

Issued Date 2013/08/07 2016/08/06 Title
Deciphered Date
Power Block Diagram
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIASLize DocumentNumber
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS LA-B972P 0.4
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
A B C D E
DAX
Power rail Control (EC) Source (CPU) 45@
ZZZ1
+RTCVCC X X @ is NO SMT part (empty) <USB2.0 port>
VIN X X
PCB <BOM Structure>
BATT+ X X short@ : short pad , don't pop. Part Number = DAZ14Z00100
PCB 14Z LA-B972P REV0 M/B 3 ROYALTY HDMI W/LOGO+HDCP
Part Number = RO0000003HM
DESTINATION
B+ X X
ROYALTY HDMI W /LOGO+HDCP
+VL X X UMA Dis
+3VL X X
@EMI@,@ESD@,@RF@ : Reserve , don't pop. USB2.0 port
+5VALW EC_ON X 0 USB 2.0/3.0(left side) USB 2.0/3.0(left side)

1 1
+3VALW EC_ON X RF@ : RF team request, must add.
+3VALW_EC EC_ON X
ZSO40@,ZSO56@ : Board ID config. 1 USB 2.0(right side) USB 2.0(right side)
+3V_PCH PCH_PWR_EN X EMI@ : EMI team request, must add.
+1.35V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4# DIS@ : GPU BOM config. 2 USB 2.0(right side) USB 2.0(right side)
+5VS SUSP# PM_SLP_S3# ESD@ : ESD team request, must add.
+3VS SUSP# PM_SLP_S3# 3 WLAN/BT WLAN/BT
+1.5VS SUSP# PM_SLP_S3# LVDS@ : Support LVDS panel.
+1.05VS SUSP# PM_SLP_S3# 4 Camera Camera
+0.6V_0.675VS SUSP# GCLK@ : Support GCLK
+VCC_CORE X VR12.5_VR_ON 5 Touch screen(Options) Touch screen(Options)
CRT@,CRTEMI@ : Support CRT port
6 X X
eDP@,eDPEMI@ : Support eTP panel
7 X X
<PCI-E,SATA,USB3.0>
2 UCPU1 2
+3V_PCH +3VS DESTINATION
Lane# PCI-E SATA USB3.0
UMA Dis
R=2.2K R=10K
AP2 SMBCLK PCH_SMBCLK 1 1 USB3.0 USB3.0
AH1 SMBDATA 2N7002 PCH_SMBDATA 2 2 X X
SO‐DIMM A
CPU +3V_PCH
SO‐DIMM B
3
4
5
1
2
3
3
4
X
Card reader(PCI-E)
X
Card reader(PCI-E)
10/100/1000 LAN 10/100/1000 LAN
R=1K 6 4
SML0CLK
AN1
SML0DATA 7 GPU(DIS only)
AK1 8 GPU(DIS only)
5
9 GPU(DIS only)
+3V_PCH +3VS 10 GPU(DIS only)
11 L3 3 WLAN WLAN
R=2.2K R=2.2K
AU3 SML1CLK 12 L2 2 X X
AH3 SML1DATA 6
2N7002 13 L1 1 ODD ODD
EC_SMB_CK2
EC_SMB_DA2 14 L0 0 2.5"HDD 2.5"HDD
+3VS
3 3
Thermal Sensor @
UK1:+3VALW_EC
+3VS
79 EC_SMB_CK2
80 EC_SMB_DA2
eDP to LVDS bridge RTD2132R
EC +3VL
R=2.2K
77 EC_SMB_CK1
78 EC_SMB_DA1 R=100 BAT
Charger
G‐Sensor @
4 4

TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTI A L
Notes List
SS i ze Document Number Rev
A N D T R A D E S E C R E T IN F O R M A T I O N . TH IS S H E E T M A Y N O T B E T R A N S F E R E D F R O M TH E C U S TO D Y O F TH E C O M P E TE N T D IV IS IO N O F R & D
Custom 0.1
D E P A R TM E N T E X C E P T A S A U TH O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R TH E IN F O R M A T I O N IT C O N TA IN S
M A Y B E U S E D B Y O R D IS C L O S E D T O A N Y TH IR D P A R TY W ITH O U T P R IO R W R ITTE N C O N S E N T O F C O M P A L E L E C TR O N IC S , IN C . LA-B972P
A B C D E
5 4 3 2 1
UCPU1A HASW EL L _ MCP_ E L CC97~CC102 must closed to connector not CPU
<20> PCH_DPB_N2 C54 C45

DDI1_TXN0 EDP_TXN0 EDP_CPU_LANE_N0_C <18>
C55 B46
<20> PCH_DPB_P2
B58 DDI1_TXP0 EDP_TXP0 A47
EDP_CPU_LANE_P0_C <18> <eDP>
<20> PCH_DPB_N1 DDI1_TXN1 EDP_TXN1
<20> PCH_DPB_P1 C58 B47
B55 DDI1_TXP1 EDP_TXP1
D <20> PCH_DPB_N0 DDI1_TXN2 D
<20> PCH_DPB_P0 A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
<HDMI> <20> PCH_DPB_N3
B57 DDI1_TXN3 EDP_TXP2
<20> PCH_DPB_P3 A49
DDI1_TXP3 DDI EDP EDP_TXN3
B49
C51 EDP_TXP3
<29> PCH_DPC_N0
C50 DDI2_TXN0 A45
<29> PCH_DPC_P0
C53 DDI2_TXP0 EDP_AUXN B45
EDP_CPU_AUX#_C <18> <eDP>
<DP TO CRT> <29> PCH_DPC_N1
B54 DDI2_TXN1 EDP_AUXP EDP_CPU_AUX_C <18>
<29> PCH_DPC_P1
C49 DDI2_TXP1 D20 EDP_COMP
B50 DDI2_TXN2 EDP_RCOMP A43 RC1 1 @ 2 0_0201_5%
A53 DDI2_TXP2 EDP_DISP_UTIL
B53 DDI2_TXN3 RC2 1 @ 2 0_0201_5%
DDI2_TXP3 BKL_PW M_CPU <18,8>
RC11 2 1 10K_0402_5% H_CPUPWRGD_R

COMPENSATION PU FOR eDP
+3V_PCH
1 OF 19 +VCCIOA_OUT L DG V0.9 PEG_COMP
Trace width=20mil and spacing=25mil
1
RC234 EDP_COMP 2
Max length=100mil
1
+VCCIO_OUT 10K_0402_5% 24.9_0402_1% RC3
HASW EL L _ MCP_ E
UCPU1B
2
1
C RC4 PROC_DETECT# D61 C

62_0402_5% PAD T51@ K61 PROC_DETECT
MI SC
N62 CATERR J62 XDP_PRDY# T58 @ PAD
<30> H_PECI PECI PRDY K62 XDP_PREQ#
2
PREQ E60 XDP_TCK

PROC_TCK XDP_TCK <6>
E61 XDP_TMS_CPU
PROC_TMS XDP_TMS_CPU <6>
PROCHOT# RC6 1 2 56_0402_5% H_PROCHOT#_R K63 J TAG E59 XDP_TRST#_CPU
<30,44> PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI_CPU
PROC_TDI XDP_TDI_CPU <6> +1.05VS_VCCST
1 F62 XDP_TDO_CPU
PROC_TDO XDP_TDO_CPU <6>
@ESD@ @
C295 RC7 1 2 H_CPUPWRGD_R C61
<11,6> +1.05VS_PG PROCPW RGD
10P_0402_50V8J 1K_0402_1% PW R
2 J60 XDP_OBS0_R T80 @ PAD XDP_TDI_CPU @ RC12 2 1 51_0402_1%
BPM#0
L DG V0.5 Trace width=12~15 mil BPM#1
H60
H61
XDP_OBS1_R
XDP_OBS2_R
T79
T52
@ PAD
@ PAD XDP_PREQ# @ RC13 2 1 51_0402_1%
Max length=500mil BPM#2 H62 XDP_OBS3_R T53 @ PAD
SM_RCOMP0 AU60 BPM#3 K59 XDP_OBS4_R T54 @ PAD
DDR3 COMPENSATION SIGNALS SM_RCOMP1 AV60 SM_RCOMP0 DDR3
BPM#4 H63 XDP_OBS5_R T55 @ PAD XDP_TRST#_CPU
SM_RCOMP1 BPM#5 XDP_TRST#_CPU <6>
SM_RCOMP2 AU61 K60 XDP_OBS6_R T56 @ PAD
200_0402_1% 2 1 RC18 SM_RCOMP0 DDR3_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_OBS7_R T57 @ PAD 1
DDR_PG_CNTL AV61 SM_DRAMRST BPM#7 @ESD@
120_0402_1% 2 1 RC19 SM_RCOMP1 SM_PG_CNTL1 CC99
2 0.1U_0402_16V7K
100_0402_1% 2 1 RC20 SM_RCOMP2 2 OF 19
B B
+1.35V_VDDQ
+1.35V_VDDQ
1
RC308
470_0402_5%
UC10
5 1
2
DDR3_DRAMRST# VCC NC
DDR3_DRAMRST# <15,16>
1 2 DDR_PG_CNTL
4 A
<15> SM_PG_CTRL Y
@ESD@ CC88 3
GND
0.1U_0402_16V7K
2 74AUP1G07GW_TSSOP5
A A

TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTI A L
DDI,MSIC,XDP
D E P A R TM E N T E X C E P T A S A U TH O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R TH E IN F O R M A T I O N IT C O N TA IN S Custom 0.1
M A Y B E U S E D B Y O R D IS C L O S E D T O A N Y TH IR D P A R TY W ITH O U T P R IO R W R ITTE N C O N S E N T O F C O M P A L E L E C TR O N IC S , IN C .
LA-B972P
5 4 3 2 1
5 4 3 2 1
<15> DDR_A_D[0..63] <16> DDR_B_D[0..63]
HASWELL_MCP_E
UCPU1D
UCPU1C HASWELL_MCP_E <DDR3L>

<DDR3L>
DDR_B_D0 AY31 AM38
SB_DQ0 SB_CK#0 M_CLK_DDR#2 <16>
DDR_A_D0 AH63 AU37 DDR_B_D1 AW 31 AN38
D SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <15> SB_DQ1 SB_CK0 M_CLK_DDR2 <16> D
DDR_A_D1 AH62 AV37 DDR_B_D2 AY29 AK38
SA_DQ1 SA_CLK0 M_CLK_DDR0 <15> SB_DQ2 SB_CK#1 M_CLK_DDR#3 <16>
DDR_A_D2 AK63 AW 36 DDR_B_D3 AW 29 AL38
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <15> SB_DQ3 SB_CK1 M_CLK_DDR3 <16>
DDR_A_D3 AK62 AY36 DDR_B_D4 AV31
SA_DQ3 SA_CLK1 M_CLK_DDR1 <15> SB_DQ4
DDR_A_D4 AH61 DDR_B_D5 AU31 AY49
SA_DQ4 SB_DQ5 SB_CKE0 DDR_CKE0_DIMMB <16>
DDR_A_D5 AH60 AU43 DDR_B_D6 AV29 AU50
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <15> SB_DQ6 SB_CKE1 DDR_CKE1_DIMMB <16>
DDR_A_D6 AK61 AW 43 DDR_B_D7 AU29 AW 49
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <15> SB_DQ7 SB_CKE2
DDR_A_D7 AK60 AY42 DDR_B_D8 AY27 AV50
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_B_D9 AW 27 SB_DQ8 SB_CKE3
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D10 AY25 SB_DQ9 AM32
SA_DQ9 SB_DQ10 SB_CS#0 DDR_CS0_DIMMB# <16>
DDR_A_D10 AP63 AP33 DDR_B_D11 AW 25 AK32
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <15> SB_DQ11 SB_CS#1 DDR_CS1_DIMMB# <16>
DDR_A_D11 AP62 AR32 DDR_B_D12 AV27
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <15> SB_DQ12
DDR_A_D12 AM61 DDR_B_D13 AU27 SB_ODT0 AL32
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_B_D14 AV25 SB_DQ13
SA_DQ13 SA_ODT0 SB_DQ14
DDR_A_D14 AP61 DDR_B_D15 AU25 SB_RAS AM35
SA_DQ14 SB_DQ15 DDR_B_RAS# <16>
DDR_A_D15 AP60 SA_RAS AY34 DDR_B_D16 AM29 AK35
SA_DQ15 DDR_A_RAS# <15> SB_DQ16 SB_W E DDR_B_WE# <16>
DDR_A_D16 AP58 AW 34 DDR_B_D17 AK29 AM33
SA_DQ16 SA_W E DDR_A_WE# <15> SB_DQ17 SB_CAS DDR_B_CAS# <16>
DDR_A_D17 AR58 AU34 DDR_B_D18 AL28
SA_DQ17 SA_CAS DDR_A_CAS# <15> SB_DQ18
DDR_A_D18 AM57 DDR_B_D19 AK28 AL35
SA_DQ18 SB_DQ19 SB_BA0 DDR_B_BS0 <16>
DDR_A_D19 AK57 AU35 DDR_B_D20 AR29 AM36
SA_DQ19 SA_BA0 DDR_A_BS0 <15> SB_DQ20 SB_BA1 DDR_B_BS1 <16>
DDR_A_D20 AL58 AV35 DDR_B_D21 AN29 AU49
SA_DQ20 SA_BA1 DDR_A_BS1 <15> SB_DQ21 SB_BA2 DDR_B_BS2 <16>
DDR_A_D21 AK58 AY41 DDR_B_D22 AR28
SA_DQ21 SA_BA2 DDR_A_BS2 <15> SB_DQ22 DDR_B_MA[0..15] <16>
DDR_A_D22 AR57 DDR_B_D23 AP28 AP40 DDR_B_MA0
SA_DQ22 DDR_A_MA[0..15] <15> SB_DQ23 SB_MA0
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D24 AN26 AR40 DDR_B_MA1
SA_DQ23 SA_MA0 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D24 AP55 AY37 DDR_A_MA1
SA_DQ24 SA_MA1 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D25 AR55 AR38 DDR_A_MA2
SA_DQ25 SA_MA2 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D26 AM54 AP36 DDR_A_MA3
SA_DQ26 SA_MA3 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D27 AK54 AU39 DDR_A_MA4
SA_DQ27 SA_MA4 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW 46 DDR_B_MA6
C DDR_A_D28 AL55 AR36 DDR_A_MA5 C
DDR_A_D29 AK55 SA_DQ28 SA_MA5 DDR_A_MA6 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
AV40
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW 39 DDR_A_MA7 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D32 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D33 AW 23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D33 AW 58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D34 AY21 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW 41 DDR_A_MA11 DDR_B_D35 AW 21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D35 AW 56 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D36 AV58 SA_DQ35 DDR CHANNEL A SA_MA12 AR35 DDR_A_MA13 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D39 AU21 SB_DQ38 SB_MA15
SA_DQ38 SA_MA15 SB_DQ39 DDR_B_DQS#[0..7] <16>
DDR_A_D39 AU56 DDR_B_D40 AY19 AW 30DDR_B_DQS#0
SA_DQ39 DDR_A_DQS#[0..7] <15> SB_DQ40 SB_DQSN0
DDR_A_D40 AY54 AJ61 DDR_A_DQS#0 DDR_B_D41 AW 19 AV26 DDR_B_DQS#1
DDR_A_D41 AW 54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58DDR_A_DQS#2 DDR_B_D43 AW 17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D43 AW 52 SA_DQ42 SA_DQSN2 AM55DDR_A_DQS#3 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW 22DDR_B_DQS#4
DDR_A_D44 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D48 AR21 SB_DQ47 SB_DQSN7
SA_DQ47 SA_DQSN7 SB_DQ48 DDR_B_DQS[0..7] <16>
DDR_A_D48 AK40 DDR_B_D49 AR22 AV30 DDR_B_DQS0
SA_DQ48 DDR_A_DQS[0..7] <15> SB_DQ49 SB_DQSP0
DDR_A_D49 AK42 AJ62 DDR_A_DQS0 DDR_B_D50 AL21 AW 26DDR_B_DQS1
DDR_A_D50 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28DDR_B_DQS2
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW 57DDR_A_DQS4 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW 18DDR_B_DQS5
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW 53DDR_A_DQS5 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21DDR_B_DQS6
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18DDR_B_DQS7
B
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7 B
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D58 AK18 SB_DQ57

DDR_A_D58 AM49 SA_DQ57 AP49 +V_SM_VREF_CNT +V_SM_VREF_CNT DDR_B_D59 AL18 SB_DQ58
DDR_A_D59 AK49 SA_DQ58 SM_VREF_CA AR51 +V_DDR_REFA_R DDR_B_D60 AK20 SB_DQ59
SA_DQ59 SM_VREF_DQ0 +V_DDR_REFA_R SB_DQ60
DDR_A_D60 AM48 AP51 +V_DDR_REFB_R DDR_B_D61 AM20
SA_DQ60 SM_VREF_DQ1 +V_DDR_REFB_R SB_DQ61
DDR_A_D61 AK48 DDR_B_D62 AR18
DDR_A_D62 AM51 SA_DQ61 DDR_B_D63 AP18 SB_DQ62
DDR_A_D63 AK51 SA_DQ62 SB_DQ63
SA_DQ63
4 OF 19
3 OF 19
A A

2011/06/29 2011/06/29 Title
Issued Date Deciphered Date DDRIII
T HI S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N I C S , I NC . A N D C O NT AI NS CONFIDENSSTiIzAeL Document Number
Rev
A N D T R A D E S E C R E T I N F O R M A T I O N . T HI S S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O M P E T E N T D I VI S I O N O F R & D
C u stom 0.1
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I NC . NE I T HE R T HI S S H E E T N O R T H E I N F O R M A T I O N I T C O NT AI NS
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C T R O N I C S , I NC .
LA-B972P
5 4 3 2 1
5 4 3 2 1
+RTCBATT
+RTCVCC PCH_RTCX1
XTAL@
1 2 PCH_RTCX2 RTC BAT conn
330K_0402_5% 1 2 RC236 PCH_INTVRMEN RC31 10M_0402_5% 15mils
2 1
1 - +
1
+RTCVCC XTAL@ +RTCBATT_R +RTCBATT
CC2 JCMOS1 CMOS YC1 +RTCVCC
1U_0402_6.3V6K SHORT PADS 1 2 1K_0402_5%
2
2
RC33
INTVRMEN 1 2 PCH_RTCRST# XTAL@ 1 32.768KHZ Q13FC13501000500 DC1 15mils 15mils
*H：Integrated
L：Integrated
VRM enable
VRM disable
RC32 20K_0402_5%
1 2 PCH_SRTCRST#
CC3 CC4 XTAL@
18P_0402_50V8J
15mils 1
2 2 1 JRTC1
LOTES_AAA-BAT-054-K01 +3VS
RC34 20K_0402_5% 1 18P_0402_50V8J 3 CONN@
1 +3VL
1
2 2 CC6
CC5 JME1 ME CMOS 1U_0402_6.3V6K BAV70W 3P C/C_SOT-323
1U_0402_6.3V6K SHORT PADS
2
2 2
D MPHY_PW REN RC217 1 2 10K_0402_5% D

<9> MPHY_PW REN
PCH_RTCX1
PCH_RTCX1 <31>
ODD_PLUG# RC218 1 2 100K_0402_5%
HASWELL_MCP_E
UCPU1E
PCH_RTCX1 AW 5
RTCX1
PCH_RTCX2 AY5
2 SM_INTRUDER# AU6 RTCX2 J5
RC353 short@ 1M_0402_5%
+RTCVCC INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 <22>
HDA_SYNC_R 1 2 HDA_SYNC RC35 1 PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 <22>
PCH_SRTCRST# AV6 RTC B15 SATA_PTX_DRX_N0 <22> 2.5" HDD
SRTCRST SATA_TN0/PETN6_L3
0_0402_5% PCH_RTCRST# AU7 A15 SATA_PTX_DRX_P0 <22>
RTCRST SATA_TP0/PETP6_L3
J8
SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1 <22>
H8
SATA_RP1/PERP6_L2
A17
SATA_PRX_DTX_P1 <22> ODD
SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 <22>
B17
Intel ME update SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <22>
short@ HDA_BIT_CLK AW 8 J6
HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
RC356 1 20_0201_5% HDA_SDOUT AV11
<30> HDA_SDO HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1
HDA_RST# AU8 B14
HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
HDA_SDIN0 AY10
<25> HDA_SDIN0 HDA_SDI0/I2S0_RXD AUDIO SATA_TP2/PETP6_L1
AU12
AU11 HDA_SDI1/I2S1_RXD F5
HDA_SDOUT
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 PCIE_PRX_DTX_N6 <21>
EMI@ RC367 AW 10 E5
DOCKEN/I2S1_TXD SATA_RP3/PERP6_L0 PCIE_PRX_DTX_P6 <21>
HDA_BITCLK_AUDIO 2 1 HDA_BIT_CLK AV10 SATA C17 PCIE_PTX_DRX_N6 CC71 2 0.1U_0402_16V7K
<25> HDA_BITCLK_AUDIO HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 PCIE_PTX_C_DRX_N6 <21> WLAN
33_0402_5% SI# 2012.11.1 Add RC367 EMI@ toisolate AY8
I2S1_SCLK SATA_TP3/PETP6_L0
D17 PCIE_PTX_DRX_P6 CC81 2 0.1U_0402_16V7K PCIE_PTX_C_DRX_P6 <21>
RP1
1 8 Audio Clock by EMI request
HDA_RST_AUDIO# 2 7 HDA_RST# V1
<25> HDA_RST_AUDIO# SATA0GP/GPIO34
3 6 HDA_SYNC_R U1 ODD_PLUG#
<25> HDA_SYNC_AUDIO SATA1GP/GPIO35 ODD_PLUG# <22>
4 5 HDA_SDOUT V6 PCH_GPIO36 T159 PAD
<25> HDA_SDOUT_AUDIO SATA2GP/GPIO36
33_0804_8P4R_5% AC1 mSATA_DET#
SATA3GP/GPIO37 mSATA_DET# <7>
PCH_JTAG_RST# AU62
PCH_JTAG_TCK AE62 PCH_TRST
A12
PCH_JTAG_TDI AD61
PCH_TCK SATA_IREF L11 RC39
+1.05VS_VCCSATA3PLL <Page 12>
+3V_PCH PCH_TDI TP7
PCH_JTAG_TDO AE61 K10 3K_0402_1%
9/17 add RF solution
L
PCH_TDO TP8
C PCH_JTAG_TMS AD62
PCH_TMS
JTAG
SATA_RCOMP
C12 SATA_COMP 1 2 DG V0.9 SATA_COMP C
PAD T156 AL11 U3 SATA_LED#
TP5 SATA_LED# <27,9>
Width=12mil
1
AC4 SATALED
RC283 @ XDP_TCK_JTAGX AE63 TP6
CM28
PAD T157 AV2 JTAGX Max length=500mil
210_0402_5% @
RSVD
1 2 HDA_BITCLK_AUDIO
R3d
2
PCH_JTAG_TDO
22P_0402_50V8J
1
CM29 5 OF 19
RC304 @ @
100_0402_1% 1 2 HDA_RST_AUDIO#
2
22P_0402_50V8J
+3VS
RC240
@ @ CC86
+3V_PCH EC_+1.05VS_PG 2 1 1 2
+3V_PCH +3V_PCH
@ UC5 10K_0402_5% .1U_0402_16V7K
1
RC45 @ 2 16
1OE VCC
1
210_0402_5%
RC41 @ RC46 XDP_TDO_CPU 3 4 XDP_TDO
1A 1B
210_0402_5% 210_0402_5%
R5
2
PCH_JTAG_TMS 5
2OE
@ <CPU site>
R8
2
PCH_JTAG_TDI XDP_TCK_JTAGX XDP_TDI_CPU 6 7 XDP_TDI_SW ITCH

R4 RC303 @ 2A 2B
1
100_0402_1% 12
RC301 @ RC302 3OE
100_0402_1% 100_0402_1% 11 10 XDP_TMS
<4> XDP_TMS_CPU
2
3A 3B
@
15
4OE
2
XDP_TRST#_CPU 14 13 XDP_TRST#
S1 <4> XDP_TRST#_CPU 4A 4B
1
XDP_TRST# 1 XDP_TRST#_CPU NC
RC37 @ 2 0_0201_5% <CPU site>
Contact ok 8 9
B
<XDP> PCH_JTAG_RST# GND NC B
<PCH site>
74CBTLV3126DS_SSOP16
S2 R6
PCH_JTAG_TMS RC196 1 @ 2 0_0201_5% XDP_TMS_CPU
<PCH site> <CPU site>
Contact ok 51_0402_5%
PCH_JTAG_TCK 2 RC38
XDP_TMS 1 @ +1.05VS_VCCST
<XDP>
1
S3 +3V_PCH
XDP_TDI_SW ITCH RC199 1 @ 2 0_0201_5% XDP_TDI_CPU
XDP_TDI_CPU <4> <CPU> R9 R511
U16 10K_0402_5%
XDP_TRST#_CPU RC16 2 @ 1 51_0402_1% 1 5
J3S <EC output>
2
NC VCC
PCH_JTAG_TDO RC307 1 @ 2 0_0201_5% XDP_TDI_SW ITCH EC_+1.05VS_PG 2
<PCH site> <XDP> <30> EC_+1.05VS_PG A 4
Y +1.05VS_PG <11,4> <CPU,XDP,XDP Switch>
J4d 3
GND
<XDP> XDP_TDI RC200 1 2 0_0201_5% XDP_TDI_SW ITCH 74AUP1G07GW _TSSOP5

short@
Resistors Resistors
<PCH site> PCH_JTAG_TDI RC195
short@
1 2 0_0201_5% XDP_TDI +1.05VS_VCCST
Topolog Description Be st Use for Stuffed ufStuffed
R1d
S4 XDP_TDO_CPU RC10 2 1 51_0402_1% Default Setting: Dual In this topology, the - Run control oper. R1d,R2,R3d, J1s, J2s,
XDP_TDO RC198 1 @ 2 0_0201_5% XDP_TDO_CPU
<XDP>
XDP_TDO_CPU <4>
TCK S can Chains CPU JTAG chain will be - ME/Sx debug R4,R5,J1d J3s
+1.05VS_VCCST (also known as controlled by TCK0 and J2d,J3d* R6,R7,R8,R9
J3D <PCH site> "Shared JTAG" in TCK1 will control J4d and Rs5*
RC194
short@
1 2 0_0201_5% PCH_JTAG_TDO R7 other docum ent) the PCH JTAG chain.
@
XDP_TDO RC14 2 1 51_0402_1%
XDP_TCK:XDP contact with CPU No 0ohm(RS5) In th is topolog y, PCH -B oundary Scan/ J1s,J2s,J3s** R1d,r3d,J1d,J2d
A
Single TCK scan chain TDI- TDO and CPU TDI-TDO Manufacturing est R2,R4,R5,R5s** J3d**,J4d, A
R2 (also known as "Com m on will be chained to form R6,R7,R8,R9

<PCH site> PCH_JTAG_TCK XDP_TCK RC15 2 1 51_0402_1%
JTAG" in other docum one JTAG scan chain
ent) controlled by TCK0
J1S
RC197 1 @ 2 0_0201_5% XDP_TCK
XDP_TCK <4> <CPU and XDP>
<PCH site> J2D

XDP_TCK_JTAGX RC193
short@
1 2 0_0201_5%
J2S <XDP> T HI S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N I C S , I NC . A N D C O NT AI NS C O NF I D E NT I AL
RTC,SATA,HDA,JTAG
XDP_TCK_JTAGX RC306 1 @ 2 0_0201_5% XDP_TDO Rev
<PCH site> A N D T R A D E S E C R E T I N F O R M A T I O N . T HI S S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O M P E T E N T D I VI S I O N O F R & D
Size Document Number
0.1
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I NC . NE I T HE R T HI S S H E E T N O R T H E I N F O R M A T I O N I T C O NT AI NS
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C T R O N I C S , I NC .
Custom
LA-B972P
5 4 3 2 1
5 4 3 2 1
CPU_XTAL24_IN CPU_XTAL24_IN <31> CPU_XTAL24_IN
CPU_XTAL24_OUT
XTAL@
HASWELL_MCP_E 1
UCPU1F 2
1M_0402_5% RC48
3 1
CLK_PCIE_LAN# C43 3 1
A25 CPU_XTAL24_IN
<23> CLK_PCIE_LAN# XTAL24_IN B25 GND GND
PCIE LAN CLK_PCIE_LAN C42 CLKOUT_PCIE_N0 CPU_XTAL24_OUT XTAL@ 1 1 XTAL@
<23> CLK_PCIE_LAN PCIECLKREQ0# U2 CLKOUT_PCIE_P0 XTAL24_OUT
CC9 CC10
PCIECLKRQ0/GPIO18 K21 4 XTAL@ 2
RC52 18P_0402_50V8J
CLK_PCIE_CR# B41 TP15 M21 18P_0402_50V8J YC2
<23> CLK_PCIE_CR# 3K_0402_1%
D CLK_PCIE_CR A41 CLKOUT_PCIE_N1 TP16 C26 PCH_CLK_BIASREF 1 2 2 24MHZ 12PF 5YEA24000122IF240Q3 D
PCIE Card reader <23> CLK_PCIE_CR
Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF +1.05VS_AXCK_LCPLL <Page12>
<23,9> CR_CLKREQ# CR_CLKREQ#
PCIECLKRQ1/GPIO19 C35 TESTLOW1 4 5 RPH22
CLK_PCIE_MINI1# C41 CLOCK TP19 C34 TESTLOW2 3
<21> CLK_PCIE_MINI1#
CLK_PCIE_MINI1 B42
CLKOUT_PCIE_N2 SIGNALS TP20 AK8 TESTLOW3 2
6
7
<PV>PRH13 change to RPH22.
WLAN <21> CLK_PCIE_MINI1
LAN_CLKREQ#
CLKOUT_PCIE_P2 TP21 AL8 TESTLOW4
<23> LAN_CLKREQ# AD1 1 8
PCIECLKRQ2/GPIO20 TP22 10K_0804_8P4R_5%
CLK_PCIE_GPU# B38 AN15 CLK_PCI0 EMI@ RC61 1 2 22_0402_5% CLK_PCI_LPC
<32> CLK_PCIE_GPU# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_LPC <30> <EC>
GPU <32> CLK_PCIE_GPU CLK_PCIE_GPU C37 AP15 CLK_PCI1 EMI@ RC62 1 2 22_0402_5% CLK_PCI_TPM
CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM <28>
<32,8> GPU_CLKREQ# GPU_CLKREQ# N1
PCIECLKRQ3/GPIO21 B35 CLK_CPU_ITP# T82 @ PAD
A39 CLKOUT_ITPXDP A35
B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
CLK_CPU_ITP T81 @ PAD <XDP CLK reserve TP>
PCIECLKREQ4# U5 CLKOUT_PCIE_P4
+3VS <9> PCIECLKREQ4# PCIECLKRQ4/GPIO22
RPH11 9/17 add RF solution
B37
4 5 LAN_CLKREQ# A37 CLKOUT_PCIE_N5
3 6 SYS_RESET#
SYS_RESET# <8> <21> MINI1_CLKREQ# MINI1_CLKREQ# T2 CLKOUT_PCIE_P5 +3V_PCH
2 7 EC_KBRST# PCIECLKRQ5/GPIO23 @RF@
EC_KBRST# <30,9> CM30
1 8 MSATA_DET# MSATA_DET# <6>
6 OF 19 1 2 CLK_PCI_LPC
10K_0804_8P4R_5%
+3VS 22P_0402_50V8J
RPH12 SML0CLK 1K_0402_5% 1 2 RC72
HASWELL_MCP_E @RF@
UCPU1G CM31
4 5 PCIECLKREQ0# SML0DATA 1K_0402_5% 1 2 RC73
3 6 MINI1_CLKREQ# LPC_AD0 AU14 AN2 SMBALERT# 1 2 CLK_PCI_TPM
2 7 PCI_PIRQB# <28,30> LPC_AD0 LAD0 SMBALERT/GPIO11 AP2 SMBCLK SMBALERT# <9>
PCI_PIRQB# <8> LPC_AD1 AW 12
1 8 PCH_GPIO33 <28,30> LPC_AD1 LAD1 SMBCLK
LPC_AD2 AY12 LPC AH1 SMBDATA 22P_0402_50V8J SMBCLK RP2 1 8 2.2K_0804_8P4R_5%
PCH_GPIO33 <9> <28,30> LPC_AD2 LAD2 SMBDATA
C LPC_AD3 AW 11 SMBUS AL2 USB_CR_PWREN SMBDATA 2 7 C
<28,30> LPC_AD3 LAD3 SML0ALERT/GPIO60 AN1 SML0CLK USB_CR_PWREN <8> @RF@
10K_0804_8P4R_5% LPC_FRAME# AV12 CM33 SML1CLK 3 6
<28,30> LPC_FRAME# LFRAME SML0CLK
RPH19 AK1 SML0DATA SML1DATA 4 5
1 PCH_SPI_CS0#_R SML0DATA
PCH_SPI_CS0# 8 AU4 SML1ALERT# 1 2 PCH_SPI_CLK_R
PCH_SPI_SO 7 2 PCH_SPI_SO_R SML1ALERT/PCHHOT/GPIO73 SML1ALERT# <9>
AU3 SML1CLK
PCH_SPI_SI 6 3 PCH_SPI_SI_R SML1CLK/GPIO75
AH3 SML1DATA
PCH_SPI_HOLD# 5 4 PCH_SPI_SIO3 PCH_SPI_CLK AA3 SML1DATA/GPIO74 22P_0402_50V8J
SPI_CLK
DB# 2013.08.27 RC368 place near CPU PCH_SPI_CS0# Y7 AF2
SPI_CS0 CL_CLK
15_0804_8P4R_5% Y4 AD2
SPI_CS1 SPI C-LINK CL_DATA
AC2 AF4
PCH_SPI_CLK RC368 1 2 PCH_SPI_CLK_R SPI_CS2 CL_RST
PCH_SPI_SI AA2
EMI@ 15_0402_5% SPI_MOSI +3VS +3VS
PCH_SPI_SO AA4
RPH20 PCH_SPI_SIO2 SPI_MISO
Y6
8 1 PCH_SPI_SI_R PCH_SPI_SIO3 AF1 SPI_IO2
<30> EC_SPI_SI SPI_IO3
7 2 PCH_SPI_SO_R
<30> EC_SPI_SO
6 3 PCH_SPI_CS0#_R SI# 2012.11.1 Add RC368 ,RC369 to
<30> EC_SPI_CS0#
2
PCH_SPI_SIO2 5 4 PCH_SPI_WP#
Isolate SPI Clock by EMI request RC78 RC79
15_0804_8P4R_5% 7 OF 19 10K_0402_5% 10K_0402_5%
2
EMI@ RC369 1 2 short@ RC56 1 2 0_0402_5% PCH_SPI_CLK_R QC2A 2N7002DWH_SOT363-6
<30> EC_SPI_CLK
1
15_0402_5%
SMBCLK 6 1
DB# 2013.08.27 RC369 place near SPI ROM PCH_SMBCLK <15,16>
+3V_PCH
5
EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P MXIC 2N7002DWH_SOT363-6
SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P QC2B
WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
2
SMBDATA 3 4
B
@ RC80
3.3K_0402_5%
SPI ROM 8M Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8+P3V_PCH PCH_SMBDATA <15,16>
B
+3VS
1
UC2
PCH_SPI_CS0#_R 1 8
CS# VCC
PCH_SPI_SO_R 2 7 PCH_SPI_HOLD# 2 1 RC84 3.3K_0402_5% 1
1 2 PCH_SPI_WP# 3 SO/SIO1 HOLD# 6
+3V_PCH PCH_SPI_CLK_R
RC85 3.3K_0402_5% 4 W P# SCLK 5 PCH_SPI_SI_R CC11
GND SI/SIO0 0.1U_0402_16V7K
2
2
EN25Q64-104HIP @ 2N7002DWH_SOT363-6
SML1CLK 6 1
EC_SMB_CK2 <18,30,32>
5
QC6A
SML1DATA 3 4
EC_SMB_DA2 <18,30,32>
2N7002DWH_SOT363-6
QC6B
remove thernal sensor 10/14

A A

T HIS SH EET O F EN G IN EER IN G D R AW IN G IS T H E PR O PR IET AR Y PR O PER T Y O F C O MPAL ELEC T R O N IC S, INC. AN D CONT AINS CONFIDENTIA L
CLK,SPI,SMB,LPC
SS ize Document Number Rev
AN D T R AD E SEC R ET IN F O R MAT IO N . T HIS SH EET MAY N O T BE T R AN SF ER ED F R O M T H E C U ST O D Y O F T H E C O MPET EN T DIVISION O F R &D
Custom 0.1
D EPAR T MEN T EXC EPT AS AU T H O R IZ ED BY C O MPAL ELEC T R O N IC S, INC. NEIT HER T HIS SH EET N O R T H E IN F O R MAT IO N IT CONT AINS
MAY BE U SED BY O R DISCLO SED T O AN Y T H IR D PAR T Y W IT H OU T PR IO R W RIT T EN C O N SEN T O F C O MPAL ELEC T R O N IC S, INC.
LA-B972P
5 4 3 2 1
5 4 3 2 1
+RTCVCC
T83 short@ RC268 1 20_0201_5% PM_SLP_S0#_R

DSWODVREN - On Die DSW VR Enable
PAD
RC269 1 2 0_0201_5% PM_SLP_S3# * H：Enable DSW ODVREN RC254 2 1 330K_0402_5%
@ L：Disable DSW ODVREN RC255 2 1 330K_0402_5%

Non Deep S3 RC91-->SMT @
Deep S3 RC93-->SMT
UCPU1H HASWELL_MCP_E
@
SUSW ARN#_R RC91 1 2 0_0201_5% SYSTEM POWERMANAGEMENT
<9> SUSW ARN#_R
short@ RC93 1 20_0201_5% SUSACK#_R AK2 AW 7 DSW ODVREN RC371 1 2 0_0402_5% AOAC_PME#
<30> SUSACK# SUSACK DSW VRMEN
SYS_RESET# AC3 AV5 PCH_DPW ROK_R short@
D <7> SYS_RESET# SYS_RESET DPW ROK D
<30> SYS_PW ROK SYS_PW ROK AG2 AJ5 W AKE#
SYS_PW ROK W AKE W AKE# <41> +3V_DSW _P
short@ RC99 1 2 0_0402_5% PM_PW ROK_R AY7
PCH_PW ROK
PCH_PW ROK short@ RC1001 2 0_0402_5% APW ROK_R AB5
<30> PCH_PW ROK APW RO K T147
PLT_RST#_PCH AG7 V5 PM_CLKRUN#
PLTRST CLKRUN/GPIO32 PM_CLKRUN# <30>
AG4 SUS_STAT# W AKE# RC98 1 2 1K_0402_5%
SUS_STAT/GPIO61
AE6
SUSCLK/GPIO62
AP5
SLP_S5/GPIO63 PAD PM_SLP_S5# <30>
PCH_RSMRST# AW 6
<30> PCH_RSMRST# RSMRST @
Deep S3 <30> PCH_SUSWARN# short@ RC1041 2 0_0402_5% SUSW ARN#_R AV4
short@ RC1031 2 0_0402_5% PBTN_OUT#_R AL7 AJ6
<30> PBTN_OUT# SUSW AR N/SUSPW RDNACK/GPIO30 PM_SLP_S4# <30>
1 2 DC2 ACIN_R AJ8 AT4 PM_SLP_S3#
<30,44,45,46> ACIN PW RBTN SLP_S4 PM_SLP_S3# <30>
CH751H-40PT_SOD323-2 PM_BATLOW # AN4 AL5 T145PAD @
ACPRESENT/GP IO 31 SLP_S3 AP4
PM_SLP_S0#_R AF3 1 2 0_0201_5%
BATLOW /GPIO72 SLP_A PM_SLP_SUS# <30>
PCH_SLP_W LAN# AM5 AJ7
SLP_S0 SLP_SUS
short@ RC286 PCH_RSMRST# RC106 2 1 10K_0402_5%
SLP_W LAN/GPIO29 SLP_LAN
C70 ESD@
1 2 PCH_PW ROK Non Deep S3 RC286-->@
8 OF 19 T142 T143Deep S3 RC286-->SMT T144
PAD PAD PAD
0.047U_0402_16V7K
@ @ @
CH751H-40PT_SOD323-2
Deep S3:DSW power choose on page12
PCH_RSMRST# 1 2 DC3 PCH_PW ROK
CH751H-40PT_SOD323-2 +3V_DSW _P
RC112 2 1 100K_0402_5% SYS_PW ROK DC4 2 1
SPOK <47>
C C
PCH_DPW ROK_R RC316 1 20_0201_5% PCH_DPW ROK <30>
short@
RPH15
HASWELL_MCP_E 1 8
UCPU1I PM_BATLOW #
USB_CR_PW REN 2 7
<7> USB_CR_PW REN
3 6
PANEL_BKEN_CPU PD 100K on Page20 PCH_SLP_W LAN# 4 5
short@ RC114 1 2 0_0402_5% BKL_PW M_CPU_R B8 B9 PCH_DDPB_CLK 10K_0804_8P4R_5%

<18,4> BKL_PW M_CPU EDP_BKLCT L DDPB_CTRLCLK PCH_DDPB_CLK <20>
short@ RC115 1 2 0_0402_5% ENBKL_CPU A9 C9 PCH_DDPB_DAT ACIN_R RC101 1 2 10K_0402_5%
<30> ENBKL
ENVDD_CPU RC116 1 2 0_0402_5% ENVDD_CPU_R EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA
2 2.2K_0402_5%
PCH_DDPB_DAT <20> <HDMI>
<19> ENVDD_CPU C6 D9 @ 1RC107
short@ EDP_VDDEN DDPC_CTRLCLK 2
D11 1 +3VS
DDPC_CTRLDATA RC102 2.2K_0402_5%
EC_SMI# U6 <SI>Displayport Port C Enable pin RC102 pull high +3VS

<9> EC_SMI# PIRQA/GPIO77
PCI_PIRQB# P4 C5
<7> PCI_PIRQB# PIRQB/GPIO78 DISPLAY DDPB_AUXN +3VS
PCI_PIRQC# N4 B6 DDI1_AUX_DN
<9> PCI_PIRQC# PIRQC/GPIO79 DDPC_AUXN DDI1_AUX_DN <29>
@ PCH_GPIO80 N2 B5
PIRQD/GPIO80 DDPB_AUXP <DP TO CRT HPD>
<30> AOAC_PME# AOAC_PME# 1 2 AOAC_PME#_R AD4 A6 DDI1_AUX_DP
PME DDPC_AUXP DDI1_AUX_DP <29>
RC305 0_0402_5% G PIO
U7
TS_RST# GPIO55
L1
PAD T146@ GPIO52
PCH_MC_W AKE# PM_CLKRUN# RC110 2 1 8.2K_0402_5%
L3
GPIO54 DDPB_HPD
C8 PCH_DDPB_HPD <20> <HDMI>
PCH_MIC_DET R5 A8 DDI1_HPD <29>
PAD T154@ GPIO51 DDPC_HPD <DP TO CRT HPD>
PCH_HP_DET L4 D6
GPIO53 EDP_HPD EDP_HPD <18>
RC120 1 2 100K_0402_5% ENVDD_CPU
<eDP HPD>
B B
9 OF 19
+3VS
@
1 2
RC300 0_0402_5%
RC125 2 1 10K_0402_5% PCH_MC_W AKE#
+3VS
RPH27 4 5 GPU_CLKREQ#
GPU_CLKREQ# <32,7>
3 6 PCH_GPIO80
5
2 7 PCH_HP_DET UC9
1 8 DEVSLP1 1 PLT_RST#_PCH
10K_0804_8P4R_5%
DEVSLP1 <22,9>
PLT_RST# 4 IN1 <CPU>
<21,23,28,30,32> PLT_RST# O
G P
2
IN2
SN74AHC1G08DCKR_SC70-5
3
PD on KBC page
A A
Security Classification Compal Secret Data

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N IC S , IN C . A N D C O N T A IN S CONFIDENTIA L
PM,GPIO,DDI
S ize Document Number Rev
A N D T R A D E S E C R E T I N F O R MA T I O N . T H I S S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O MP E T E N T D IVIS IO N O F R & D
Custom 0.1
D E P A R T ME N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , IN C . N E I T H E R T H I S S H E E T N O R T H E IN F O R MA T IO N IT C O N T A IN S
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T O F C O M P A L E L E C T R O N IC S , IN C .
LA-B972P
5 4 3 2 1
5 4 3 2 1
+1.05VS_VCCST
1
HASWELL_MCP_E
UCPU1J RC242
1K_0402_5%
short@ RC129
2
0_0402_5%
PCH_AUDIO_PWREN P1 D60 H_THERMTRIP#_C 1 2 H_THEMTRIP#
BMBUSY/GPIO76 THRMTRIP
AU2 V4 EC_KBRST# EC_KBRST# <30,7>
LAN_PWR_EN GPIO8 RCIN/GPIO82 SERIRQ
<23> LAN_PWR_EN AM7
LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ
T4 SERIRQ <28,30> DG V0.9 PCH_OPIRCOMP
<30> EC_LID_OUT# EC_LID_OUT# AD6 AW15PCH_OPIRCOMP 2 1
GPIO15 OPI_COMP2
Width=12mil,spacing=12mil
D
<30> EC_FB_CLAMP_TGL_REQ#
<34> DGPU_GC6_EN
RC1221@
RC1231@
2 0_0201_5% PCH_GPIO16
2 0_0201_5% PCH_GPIO17
Y1
T3
GPIO16
GPIO17
MISC
RSVD
RSVD
AF20
AB21
RC131
49.9_0402_1% L Max length=500mil D
UART_WAKE# AD5
EC_PME# GPIO24
<23,30> EC_PME# AN5
PAD T148 GPIO27
AD7
PAD T149 GPIO28
AN3
GPIO26
R6 Boot B I O S Strap
BT_ON AG6 NGFF_WIFI_3.3_PWREN
WWAN_PWREN
GSPI0_CS/GPIO83 L6
GSPI0_CLK/GPIO84 PCH_GPIO86 Boot BIOS Location
AP1 GPIO56 N6 PCH_GPIO85RC1081@ 2
AL4 GPIO57 GSPI0_MISO/GPIO85 L8 MSATA_SSD_PWREN DGPU_PWR_EN <30,35,53>
<30,32> DGPU_HOLD_RST#
<10,21> WL_OFF#
2 PCH_GPIO58
RC1191@ 0_0201_5% WL_OFF# AT5 GPIO58
GPIO59
GSPI0_MOSI/GPIO86 R7
GSPI1_CS/GPIO87
0_0201_5%
* 0 SPI
NMI_DBG#_CPU AK4 GPIO L5
<30> NMI_DBG#_CPU GPIO44 GSPI1_CLK/GPIO88 N7 TOUCH_PANEL_PWREN
LPDDR3_ID1 AB6 GSPI1_MISO/GPIO89
LPDDR3_ID2 GPIO47
U4 K2 SATA1_PWREN
LPDDR3_ID3 GPIO48 GSPI_MOSI/GPIO90
Y3 J1 PCH_LAN_RST# 9/12 reserve DGPU_PWR_EN on GPIO85
PAD T150 GPIO49 UART0_RXD/GPIO91
P3 K3 PCH_LAN_WAKE#
MPHY_PWREN GPIO50 UART0_TXD/GPIO92
<6> MPHY_PWREN Y2 J2 PCH_CR_RST#
USB32_P0_PWREN_R# AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93
G1 PCH_CR_WAKE#
GPIO13 UART0_CTS/GPIO94
AH4 K4
USB_CAM_PWREN GPIO14 UART1_RXD/GPIO0
AM4 G2
TS_GPIO_CPU GPIO25 UART1_TXD/GPIO1
<19> TS_GPIO_CPU AG5 J3
ACCEL_INT# GPIO45 UART1_RST/GPIO2
<28> ACCEL_INT# AG3 J4 ODD_DA# ODD_DA# <22>
GPIO46 UART1_CTS/GPIO3 I2C_0_SDA
F2
PCH_GPIO9 AM3 I2C0_SDA/GPIO4 I2C_0_SCL
F3
EC_SCI# AM2 GPIO9 I2C0_SCL/GPIO5 I2C_1_SDA
<30> EC_SCI# G4
PCH_GPIO33 P2 GPIO10 I2C1_SDA/GPIO6 I2C_1_SCL
<7> PCH_GPIO33 F1
PAD T158 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7
Dummy SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64
E3
DEVSLP1 L2 F4
<22,8> DEVSLP1 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65
D3
HDA_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66
<25> HDA_SPKR E4
SPKR/GPIO81 SDIO_D1/GPIO67 ODD_PWR NGFF_WIFI_3.3_PWREN 4 5 RPH21
C C3 ODD_PWR <22>
C
SDIO_D2/GPIO68 WWAN_PWREN 3 6
E2
+3VS SDIO_D3/GPIO69 MSATA_SSD_PWREN 2 7
+3V_PCH 10 OF 19 TOUCH_PANEL_PWREN 1 8
10K_0804_8P4R_5%
<SI> PRH14.4 change from +3V_PCH to +3VS for S3 leakage
RPH23 4 5 ODD_DA# <PV>PRH12 change to RPH21.
3 6 EC_LID_OUT# +3V_PCH +3VS +3VS
2 7 UART_WAKE# +3VS
1 8 BT_ON
1
1
10K_0804_8P4R_5%
RC135 RC261 RC262
RPH24 4 5 USB_OC2#
3 6 USB_OC2# <10> 10K_0402_5% 10K_0402_5%
10K_0402_5%
2 7 ACCEL_INT# @ @ @
2
2
1 8 PCH_GPIO58 LPDDR3_ID1
10K_0804_8P4R_5% LPDDR3_ID2 PCH_CR_WAKE# 4 5 RPH28
LPDDR3_ID3 PCH_CR_RST# 3 6
RPH25 4 5 USB_OC0# PCH_LAN_WAKE# 2 7
USB_OC0# <10,24> 1 8
3 6 USB32_P0_PWREN_R# PCH_LAN_RST#
1
2 7 PCH_GPIO9 10K_0804_8P4R_5%
1 8 NMI_DBG#_CPU @RC263 @RC264 @RC265 @
10K_0804_8P4R_5%
<PV>PRH14 change to RPH23. 10K_0402_5% 10K_0402_5% 10K_0402_5%
I2C_1_SDA 8 1 RPH18
PRH15 change to RPH24.
2
I2C_0_SCL 7 2
I2C_0_SDA 6 3
+3VS PRH16 change to RPH25. I2C_1_SCL 5 4
B RPH13 B
4 5 1K_0804_8P4R_5%
3 6 CR_CLKREQ#
2 7 SERIRQ CR_CLKREQ# <23,7> @
1 8 SATA_LED# +3V_PCH
SATA_LED# <27,6>
10K_0804_8P4R_5%
RPH26 4 5 PCH_GPIO17
3 6 EC_SMI# RPH14 4 5 SUSWARN#_R
EC_SMI# <8> SUSWARN#_R <8>
2 7 PCIECLKREQ4# 3 6 SML1ALERT#
PCIECLKREQ4# <7> SML1ALERT# <7>
1 8 PCI_PIRQC# 2 7 SMBALERT#
PCI_PIRQC# <8> SMBALERT# <7>
10K_0804_8P4R_5% 1 8 EC_SCI#
10K_0804_8P4R_5%
RPH10 4 5 SATA1_PWREN
3 6 PCH_AUDIO_PWREN
2 7 USB_CAM_PWREN
1 8 LAN_PWR_EN
10K_0804_8P4R_5% <PV>PRH10 change to RPH10.
PRH17 change to RPH26.
+3V_DSW_P
DSW power choose on page12
* GPIO27 RC277 1 2 10K_0402_5% EC_PME#
A A
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable

GPIO,UART,I2C
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIASLize Document Number
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS
LA-B972P
5 4 3 2 1
5 4 3 2 1
HASW ELL_MCP_E
UCPU1K
<DB>change AC cap to 0.22uF review by Nvidia
PEG_GTX_C_HRX_N7 F10 AN8
D <32> PEG_GTX_C_HRX_N7 PERN5_L0 USB2N0 USB20_N0 <24> D
PEG_GTX_C_HRX_P7 E10 AM8 USB2.0/USB3.0
<32> PEG_GTX_C_HRX_P7 PERP5_L0 USB2P0 USB20_P0 <24>
0.22U_0402_6.3V6K DIS@ 1 2 CC90 PEG_HTX_GRX_NC723 AR7
<32> PEG_HTX_C_GRX_N7 PETN5_L0 USB2N1 USB20_N1 <24>
0.22U_0402_6.3V6K DIS@ 1 2 CC91 PEG_HTX_GRX_PC722 AT7 USB2.0
<32> PEG_HTX_C_GRX_P7 PETP5_L0 USB2P1 USB20_P1 <24>
<32> PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N8 F8 AR8 USB20_N2 <24>

PERN5_L1 USB2N2
PEG_GTX_C_HRX_P8 E8 AP8 USB2.0
<32> PEG_GTX_C_HRX_P8 PERP5_L1 USB2P2 USB20_P2 <24>
0.22U_0402_6.3V6K DIS@ 1 2 CC89 PEG_HTX_GRX_NB823 AR10
0.22U_0402_6.3V6K DIS@ 1 2 CC92 PEG_HTX_GRX_PA823 AT10 WLAN/BT
<32> PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N9 H10 AM15 USB20_N4 <19>

PERN5_L2 USB2N4
<32> PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P9 G10
PERP5_L2 USB2P4
AL15 USB20_P4 <19> Camera
0.22U_0402_6.3V6K DIS@ 1 2 CC93 PEG_HTX_GRX_N9 B21 AM13
0.22U_0402_6.3V6K DIS@ 1 2 CC94 PEG_HTX_GRX_P9 C21 AN13 Touch screen
<32> PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N10 E6 AP11

PERN5_L3 USB2N6
<32> PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P10 F6 AN11
PERP5_L3 USB2P6
0.22U_0402_6.3V6K DIS@ 1 2 CC95 PEG_HTX_GRX_N10 B22 AR13
<32> PEG_HTX_C_GRX_N10 PETN5_L3 USB2N7
0.22U_0402_6.3V6K DIS@ 1 2 CC96 PEG_HTX_GRX_P10 A21 AP13
<32> PEG_HTX_C_GRX_P10 PETP5_L3 USB2P7
C <23> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11 C
<23> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_P3 F11 PERN3 G20 USB3_RX0_N <24>
10/100/1G LAN CC12 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N3 C29
PERP3 USB3RN0 H20 USB3_RX0_P <24>
<23> PCIE_PTX_C_DRX_N3 CC13 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30 USB3RP0 USB2.0/USB3.0
PETN3 PCIe USB C33 USB3_TX0_N <24>
<23> PCIE_PTX_C_DRX_P3
PETP3 USB3TN0 B34 USB3_TX0_P <24>
F13 USB3TP0
G13 PERN4 E18
PERP4 USB3RN1 F18
B29
A29 USB3RP1
PETN4 B33
PETP4 USB3TN1 A33
G17
F17
PERN1/USB3RN
USB3TP1 L DG V0.9 USBRBIAS
Trace width=50ohm and spacing=15mil
C30 2
C31 PERP1/USB3RP2 USBRBIAS RC148 1 2 22.6_0402_1%
Max length=500mil
AJ10
AJ11
<23> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 F15 PETN1/USB3TN USBRBIAS AN10
<23> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 G15 2 USBRBIAS AM10
PCI-E Card reader PETP1/USB3TP2 TP13
<23> PCIE_PTX_C_DRX_N2 CC16 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N2 B31 TP14
<23> PCIE_PTX_C_DRX_P2 CC17 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P2 A31 PERN2/USB3RN
3 AL3 USB_OC0# USB_OC0# <24,9>
B PERP2/USB3RP3 AT1 USB_OC1# USB_OC1# <24> B
OC0/GPIO40 AH2 USB_OC2#
RC151 E15 USB_OC2# <9>
PETN2/USB3TN OC1/GPIO41 AV3 USB1_PWR_EN
3K_0402_1% E13 OC2/GPIO42
1 2 PCH_PCIE_RCOMP A27 3 +3V_PCH
<Page12> +1.05VS_VCCUSB3PLL B27 PETP2/USB3TP3 OC3/GPIO43
RPH17
4 5
L DG V0.9 PCIE_RCOMP
Width=12mil,spacing=12mil
TP3 11 OF 19 <21,9> WL_OFF#
USB_OC1#
WL_OFF#
3
2
USB1_PWR_EN 1
6
7
8
TP4
Max length=500mil PCIE_RCOMP
PCIE_IREF 10K_0804_8P4R_5%
A A

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N I C S , INC. A N D C O N T A I N S CONFIDENTI A L
PCIE,USB
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , INC. N E I T H E R T H I S S H E E T N O R T H E I N F O R M A T I O N IT C O N T A I N S B LA-B972P 0.1
5 4 3 2 1
5 4 3 2 1
+VCC_CORE@10000mA
+VCC_CORE
HASWELL_MCP_E
UCPU1L
+1.35V_VDDQ L59 C36

VCC
J58 RSVD C40
RSVD VCC
2500mA AH26 C44
+VCC_CORE VCC
C48
VDDQ VCC
AJ31 C52
VDDQ VCC
AJ33 C56
VDDQ VCC
D AJ37 E23 D
VDDQ VCC
AN33 E25
VDDQ VCC
AP43 E27
VDDQ VCC
AR48 E29
VDDQ VCC
AY35 E31
VDDQ VCC
AY40 E33
VDDQ VCC
AY44 E35
VDDQ VCC
AY50 E37
+1.05VS_VCCST VDDQ VCC
DG V0.5 H_CPU_SVIDALRT# E39
SVID ALERT L RC154 close to CPU<300mil VCC_SENSE
F59
N58
VCCIN
VCC
VCC
VCC
E41
E43
Max length=1000~2000mil PH on power page AC58 RSVD E45
RSVD VCC
1
E47
VCC
RC154 <PWR VR12.6> <50> VCCSENSE VCCSENSE E63 E49
AB23 VCC_SENSE VCC
E51
RSVD VCC
75_0402_5% +VCCIO_OUT A59 E53
VCCIO_OUT VCC
<VR IV and CPU> E20 E55
+VCCIOA_OUT VCCIOA_OUT VCC
2
<EDP_COMP power rail> AD23 E57
RSVD VCC
2 H_CPU_SVIDALRT# AA23 F24
<50> VR_SVID_ALRT# RSVD VCC
<PWR VR12.6> RC155143_0402_1% AE59 F28
RSVD VCC
F32
VCC
H_CPU_SVIDALRT# L62 F36
VIDALERT VCC
<50> VR_SVID_CLK VR_SVID_CLK N63 F40
+1.05VS_VCCST VIDSCLK VCC
VR_SVID_DAT L63 F44
VIDSOUT VCC
B59 F48
SVID DATA <4,6> +1.05VS_PG
<50> VR12.5_VR_ON F60 VCCST_PWRGD
VR_EN
VCC
VCC
F52
1
VR12.6PG_MCP C59 F56

RC156 VR_READY HSW ULT POW ER VCC
G23
VCC
110_0402_1% D63 G25
VSS VCC
CPU_PWR_DEBUG H59 G27
PWR_DEBUG VCC
<PWR VR12.6> P62 G29
VSS VCC
2
P60 G31
VCC
P61 RSVD_TP G33
C
VR_SVID_DAT N59 RSVD_TP VCC G35 C
<50> VR_SVID_DAT N61 RSVD_TP VCC G37
T59 RSVD_TP VCC G39
AD60 VSS VCC G41
AD59 VSS VCC G43
AA59 VSS VCC G45
AE60 VSS VCC G47
AC59 VSS VCC G49
AG58 VSS VCC G51
+VCCIO_OUT +1.05VS_VCCST U59 VSS VCC G53
@ V59 VSS VCC G55
<CPU> RC294 1 2 0_0402_5% +VCC_CORE VSS VCC G57
+1.05VS 600mA AC22 VCC H23
AE22 VCCST VCC J23
AE23 VCCST VCC K23
VCCST VCC K57
AB57 VCC L22
AD57 VCC VCC M23
AG57 VCC VCC M57
C24 VCC VCC P57
C28 VCC VCC U57
VCC VCC
L DG V0.5 VIDSOUT C32
VCC VCC
W57
RC156 close to CPU<500mil 12 OF 19

Max length=1000~2000mil
+1.05VS_VCCST
+1.05VS_VCCST
1
B +3V_PCH B
RC288
%
150_0402_5
1
+1.05VS +1.05VS_VCCST UC8 10K_0402_5%

1 5
RC166
NC VCC
2
short@ 2
<50> VGATE A
RC223 1 2 4 VR12.6PG_MCP
2
3 Y
GND
1U_0402_6.3V6
CPU_PWR_DEBUG 0_0805_5%
1 1 74AUP1G07GW_TSSOP5
CC7
22U_0805_6.3V6
%
10K_0402_5
7
CC72
1
@
@
2 2
RC16
K
2
M
1
+1.35V_VDDQ +1.35V_VDDQ
M
2.2U_0402_6.3V6
CC20
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
2.2U_0402_6.3V6
CC21
M
2.2U_0402_6.3V6
CC22
M
2.2U_0402_6.3V6
CC23
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
1 1
1 1 1 1 1 1 @ 1 1 @ 1 1 @
CC24 + CC25 +
@
CC27
CC29
CC26
CC28
CC30
CC31
330U_2.5V_M 330U_2.5V_M
2 2 2 2 2 2 2 2 2 2 2 2
@
A A

T HIS SHEET OF ENGINEERING DRAW ING IS T HE PROPRIET ARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIALSize Document Number
Power
AND T RADE SECRET INFORMAT ION. T HIS SHEET MAY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COMPET ENT DIVISION OF R&D Rev
Custom
LA-B972P 0.1

5 4 3 2 1
5 4 3 2 1
+1.05VS_VCCUSB3PLL short@ 1.838A +1.05VS_VCCHSIO short@

RC1681 2 65mA
1U_0402_6.3V6K
+1.05VS_MODPHY
RC170 +3V_DSW_PRTCSUS 1 RC1692 1 0_0402_5% +3V_PCH
1 2 +1.05VS_VCCUSB3PLL 0_0805_5% 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.05VS_MODPHY
CC32
41mA
47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
CC33
CC34
1U_0402_6.3V6K
2
1 1 2 2
CC35
+RTCVCC
CC36
HASWELL_MCP_E +RTCVCC
UCPU1M
D 2 2 D
0.1U_0402_16V7K
K9
CC37
1 1
1U_0402_6.3V6K
VCCHSIO
L10
VCCHSIO
M9
CC39
VCCHSIO mPHY RTC @
+1.05VS N8 AH11
+1.05VS_VCCSATA3PLL VCCIO VCCSUS3 2 2
1 P9 AG10
1U_0402_6.3V6K
+1.05VS_VCCUSB3PLL VCCIO VCCRTC AE7 CC40 1 2 0.1U_0402_16V7K
B18
VCCUSB3PLL DCPRTC
RC171 +1.05VS_VCCSATA3PLL B11
CC41
VCCSATA3PLL
+1.05VS_MODPHY 1 2 +1.05VS_VCCSATA3PLL
2
42mA 18mA
47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% RC173 Y20 SPI Y8 SPI ROM power rail
1U_0402_6.3V6K
VCCAPLL VCCSPI +3V_PCH
1 1 Use +1.05V +1.05V 0_0402_5% 1 @ 2 +1.05VS_APPLOPI AA21 OPI
1
VCCAPLL
W 21
CC42
VCCAPLL AG14 CC44 @
CC43
VCCASW AG13 +1.05VS
2 1 0.1U_0402_16V7K
2 2 10U_0603_6.3V6M
USB3 VCCASW 2
CC45
2 1 +1.05V_DCPSUS J13 1.6A
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K DCPSUS3 J11
CC46 +1.05VS
VCC1P05 H11
AXALIA/HDA CORE VCC1P05 H15 1 1 1
+VCCSUSHDA AH14
CC48
CC49
CC50
VCCSUSHDA VCC1P05 AE8 RC174 CC52
1
1U_0402_6.3V6K
short@ VCC1P05 AF22 5.11_0402_1% 1U_0402_6.3V6K
RC172 1 2 0_0402_5% VRM/USB2/AZALIA VCC1P05 AG19 2 1 1 2 2 2 2
AH13
CC51
<DB>Aduio code power rail +1.5VS DCPSUS2 DCPSUSBYP AG20 short@
C 2 DCPSUSBYP AE9 +1.05VS_VCCASW
0.658A RC1751 2
C
1U_0402_6.3V6K
VCCASW AF9 +1.05VS
RC176
2 +1.05VS_APPLOPI VCCASW AG8 0_0805_5%
1 AC9
22U_0805_6.3V6M
+1.05VS +3V_PCH 1 1
CC5
VCCSUS3_3 VCCASW AD10 +1.05V_DCPSUS
AA9
CC53
57mA
22U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% +3V_DSW_P VCCSUS3_3 DCPSUS1 AD8

AH10
22U_0805_6.3V6M
1
1U_0402_6.3V6K
CC5
VCCDSW3_3 GPIO/LCC DCPSUS1
1 1 V8
VCC3_3 2 2
W9
CC57
+3VS VCC3_3
J15
CC58
22U_0805_6.3V6M
1 +1.5VS
CC5
2 THERMAL SENSOR VCCTS1_5
K14 +3VS
2 2 VCC3_3
K16
4
VCC3_3
2 1 2
5
ICC
+1.05VS_AXCKDCB J18 SDIO/PLSS CC76 0.1U_0402_16V7K
VCC1P05 +3V_1V8_SDIO
K19 U8
+1.05VS_AXCK_LCPLL VCC1P05 VCCSDIO RC178 short@
A20 T9
1U_0402_6.3V6K
1 RC280 2 +V1.05S_SSCF100 VCCACLKPLL VCCSDIO
+1.05VS +V1.05S_SSCF100 J17 1 1 2 0_0603_5% +3VS
+V1.05S_SSCFF VCCCLK
R21
0_0603_5%
62mA T21
VCCCLK LPT LP POW ER
CC60
1U_0402_6.3V6K
VCCCLK SUS OSCILLATOR +1.05V_AOSCSUS

1 K18 AB8
VCCCLK DCPSUS4 2
M20
VCCCLK
V21
CC61
RC281 VCCCLK
+3V_PCH AE20 AC20
2 +V1.05S_SSCFF VCCSUS3_3 VCCAPLL
+1.05VS 1 2 AE21 AG16
VCCSUS3_3 USB2 VCCIO @
124mA AG17
1U_0402_6.3V6K
B +1.05VS B
VCCIO RC180
short@ 1
1U_0402_6.3V6K
0_0603_5% 1 +1.05V_AOSCSUS 1 2 +1.05V
CC62
13 OF 19 2.2UH_LQM2MPN2R2NG0L_30%
CC65
1U_0402_6.3V6K
2
1 1
100U_1206_6.3V6K
2
CC67
+3V_DSW_P @
CC66
RC179
1 2 +1.05VS_AXCKDCB Deep S3 and Non Deep S3 2 2 @
47U_0805_6.3V6M
+1.05VS
short@
2.2UH_LQM2MPN2R2NG0L_30% 1 1 RC285 1 2 0_0402_5% Deep S3 RC285-->SMT Total 1.05VS=1838+2274=4111mA
1U_0402_6.3V6K
+3VALW
CC63
+3V_PCH RC182 1 2 0_0402_5% +3V_DSW_P Non Deep S3 RC182-->SMT Total 1.5VS=3mA

CC64
2 2 1
@ Total 1.8VS=7mA
1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
CC70
2
Total 3VS=0mA
RC181
2 +1.05VS_AXCK_LCPLL
+1.05VS 1 Total 3VALW=200+62=262mA
31mA
47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% Total 3V_PCH=99mA

1U_0402_6.3V6K
1 1
Total 1.05V=540+109=649mA
CC68
CC69
A A
2 2

Power
D EPAR T MEN T EXC EPT AS AU T H O R IZ ED BY C O MPAL ELEC T R O N IC S, INC. NEIT HER T HIS SH EET N O R T H E IN F O R MAT IO N IT CONT AINS Custom LA-B972P 0.1
5 4 3 2 1
5 4 3 2 1
UCPU1NHASWELL_MCP_E
A11 AJ35 UCPU1O HASW ELL_MCP_E

A14 VSS VSS AJ39
A18 VSS VSS AJ41 AP22 AV59
A24 VSS VSS AJ43 AP23 VSS VSS AV8
A28 VSS VSS AJ45 AP26 VSS VSS AW16
A32 VSS VSS AJ47 AP29 VSS VSS AW24
A36 VSS VSS AJ50 AP3 VSS VSS AW33 UCPU1P HASW ELL_MCP_E
D A40 VSS VSS AJ52 AP31 VSS VSS AW35 H17 D
A44 VSS VSS AJ54 AP38 VSS VSS AW37 D33 VSS H57
A48 VSS VSS AJ56 AP39 VSS VSS AW4 D34 VSS VSS J10
AA1 VSS VSS AJ63 AP54 VSS VSS AW44 D38 VSS VSS J63
AA58 VSS VSS AK23 AP57 VSS VSS AW47 D39 VSS VSS K1
AB10 VSS VSS AK3 AR11 VSS VSS AW50 D41 VSS VSS K12
AB20 VSS VSS AK52 AR15 VSS VSS AW51 D42 VSS VSS L13
AB22 VSS VSS AL10 AR17 VSS VSS AW59 D43 VSS VSS L15
AB7 VSS VSS AL13 AR23 VSS VSS AW60 D45 VSS VSS L17
AC61 VSS VSS AL17 AR31 VSS VSS AY11 D46 VSS VSS L18
AD21 VSS VSS AL20 AR33 VSS VSS AY16 D47 VSS VSS L20
AE10 VSS VSS AL26 AR49 VSS VSS AY24 D50 VSS VSS L7
AE5 VSS VSS AL29 AR5 VSS VSS AY26 D51 VSS VSS M22
AE58 VSS VSS AL31 AR52 VSS VSS AY30 D53 VSS VSS N10
AF11 VSS VSS AL33 AT13 VSS VSS AY33 D54 VSS VSS N3
AF12 VSS VSS AL36 AT35 VSS VSS AY4 D55 VSS VSS P59
AF14 VSS VSS AL39 AT37 VSS VSS AY51 D57 VSS VSS P63
AF15 VSS VSS AL40 AT40 VSS VSS AY53 D59 VSS VSS R10
C VSS VSS VSS VSS VSS VSS C
AG1 AL51 AT46 AY6 E11 T1
AG11 VSS VSS AL52 AT49 VSS VSS B20 E17 VSS VSS T58
AG21 VSS VSS AL54 AT61 VSS VSS B24 F20 VSS VSS U20
AG61 VSS VSS AL61 AU1 VSS VSS B32 F34 VSS VSS U9
AG62 VSS VSS AM1 AU16 VSS VSS B36 F38 VSS VSS V10
AG63 VSS VSS AM17 AU18 VSS VSS B4 F42 VSS VSS V3
AH17 VSS VSS AM23 AU20 VSS VSS B40 F46 VSS VSS V7
AH19 VSS VSS AM31 AU22 VSS VSS B44 F50 VSS VSS W20
AH20 VSS VSS AM52 AU24 VSS VSS B48 F54 VSS VSS W22
AH22 VSS VSS AN17 AU26 VSS VSS B52 F58 VSS VSS Y10
AH24 VSS VSS AN23 AU28 VSS VSS B56 F61 VSS VSS Y59
AH28 VSS VSS AN31 AU30 VSS VSS B60 G18 VSS VSS Y63
AH30 VSS VSS AN32 AU33 VSS VSS C11 G22 VSS VSS
AH32 VSS VSS AN35 AU51 VSS VSS C14 G3 VSS
AH34 VSS VSS AN36 AU53 VSS VSS C18 G5 VSS V58
AH36 VSS VSS AN39 AU55 VSS VSS C20 G6 VSS VSS AH46
AH38 VSS VSS AN40 AU57 VSS VSS C25 G8 VSS VSS V23
AH40 VSS VSS AN42 AU59 VSS VSS C27 H13 VSS VSS E62
AH42 VSS VSS AN43 AV14 VSS VSS C38 VSS VSS_SENSE AH16 VSSSENSE <50> <PWR VR12.6>
AH44 VSS VSS AN45 AV16 VSS VSS C39 16 OF 19 VSS
AH49 VSS VSS AN46 AV20 VSS VSS C57
AH51 VSS VSS AN48 AV24 VSS VSS D12
B B
AJ13 VSS VSS AN60 AV36 VSS VSS D21
AJ25 VSS VSS AP10 AV43 VSS VSS D26
VSS VSS AV51 VSS VSS D30
AV55 VSS VSS D31
VSS 15 OF 19 VSS
14 OF 19
A A

GND/VSSSEN
LA-B972P 0.1
5 4 3 2 1
5 4 3 2 1
HASW ELL_MCP_E
UCPU1Q CFG4
1
DC_TEST_AY2_AW2 AY2 A3 TP_DC_TEST_A3_B3
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4
DC_TEST_AY3_AW3 AY3 RC185
AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_AY60 1K_0402_1%
DC_TEST_AY61_AW61 AY61 A60
2
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
DC_TEST_AY61_AW62 AY62 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61
B2 A62
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62
TP_DC_TEST_A3_B3 B3 AV1
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW1
D DC_TEST_B62_B63 B62 D
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW2 DC_TEST_AY2_AW2
B63
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW3 DC_TEST_AY3_AW3
AW61DC_TEST_AY61_AW61
Display Port Presence Strap
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW62DC_TEST_AY61_AW62
17 OF 19 DAISY_CHAIN_NCTF_AW63
AW63
1 : Disabled; No Physical Display Port
CFG4 attached to Embedded Display Port
UCPU1R HASW ELL_MCP_E
* 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
N23
RSVD R23
RSVD
T23
RSVD
AT2 U10
AU44 RSVD RSVD
RSVD
AV44
RSVD
D15 AL1
RSVD RSVD AM11
RSVD
AP7
F22 RSVD AU10
H22 RSVD RSVD
AU15
J21 RSVD RSVD
AW14
C RSVD TP2 C
AY14
TP1
18 OF 19
UCPU1S HASW ELL_MCP_E
PAD @ T59 CFG0 AC60 AV63

CFG0 RSVD_TP
PAD @ T60 CFG1 AC62 CFG1 AU63
CFG2 AC63 RSVD_TP
PAD @ T61 CFG2
PAD @ T63 CFG3 AA63 CFG3
CFG4 AA60 C63
PAD @ T64 CFG4 RSVD_TP
CFG5 Y62 CFG5 C62
PAD @ T65 CFG6 Y61 RSVD_TP
CFG6 B43
PAD @ T66 CFG7 Y60 EDP_SPARE
PAD @ T67 CFG7
CFG8 V62 A51
PAD @ T68 CFG8 RSVD_TP
CFG9 V61 CFG9 B51
PAD @ T69 CFG10 V60 RSVD_TP
PAD @ T70 CFG10 L60
B CFG11 U60 CFG11 B
PAD @ T71 CFG12 T63 RSVD_TP
PAD @ T72 CFG12 N60
CFG13 T62 CFG13 RSVD
PAD @ T73 CFG14 T61 RESERVED
PAD @ T74 CFG14 W23
CFG15 T60 CFG15 RSVD Y22 MCP_RSVD_29 RC296 2 @ 1 49.9_0402_1%
PAD @ T75
PAD @ T76
CFG16
CFG18
AA62
U63
CFG16
CFG18
RSVD
OPI_COMP1
AY15 PROC_OPI_COMP RC186 2 1 49.9_0402_1%
L DG V0.9 PROC_OPI_COMP
PAD @ T77 CFG17 AA61 AV62 Width=12mil,spacing=12mil
PAD @ T78 CFG17 RSVD
CFG19 U62 D58 Max length=500mil
CFG19
RSVD
2 1 CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
RC188 49.9_0402_1%
A5 VSS
RSVD
HVM_CLK P20
E1 TP9 HVM_CLK_P R20
D1 TP10
J20 TP11
H18 TP12
1 2 TD_IREF B12 TD_IREF
RC191 8.2K_0402_5% 19 OF 19
A A

RSVD/CFG
LA-B972P 0.1
5 4 3 2 1
5 4 3 2 1
+V_VDDR_REFA_DQ +1.35V_VDDQ +1.35V_VDDQ
JDIMM1
+V_VDDR_REFA_DQ 1 2
D 3 VREF_DQ VSS1 4 DDR_A_D9
D
DDR_A_D13 5 VSS2 DQ4 6 DDR_A_D12
K
0.1U_0402_16V7
<5> DDR_A_D[0..63] 7 DQ0 DQ5 8
DDR_A_D8
CD1
1
9 DQ1 VSS3 10 DDR_A_DQS#1
<5> DDR_A_DQS[0..7] 11 VSS4 DQS#0 12 DDR_A_DQS1
13 DM0 DQS0 14
<5> DDR_A_DQS#[0..7] 2 15 VSS5 VSS6 16
DDR_A_D14 DDR_A_D15
17 DQ2 DQ6 18
<5> DDR_A_MA[0..15] DDR_A_D10 DDR_A_D11
19 DQ3 DQ7 20
DDR_A_D29 21 VSS7 VSS8 22 DDR_A_D25
DDR_A_D28 23 DQ8 DQ12 24 DDR_A_D24
25 DQ9 DQ13 26
27 VSS9 VSS10 28
DDR_A_DQS#3
29 DQS#1 DM1 30 DDR3_DRAMRST#
DDR_A_DQS3 DDR3_DRAMRST# <16,4>
31 DQS1 RESET# 32 1
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27 @ESD@
DDR_A_D31 35 DQ10 DQ14 36 DDR_A_D26 CD99 +1.35V_VDDQ
37 DQ11 DQ15 38 0.1U_0402_16V7K
DDR_A_D44 39 VSS13 VSS14 40 DDR_A_D45 2
DDR_A_D41 41 DQ16 DQ20 42 DDR_A_D40
43 DQ17 DQ21 44 +5VALW QD1
45 VSS15 VSS16 46
DDR_A_DQS#5 BSS138_NL_SOT23-3
47 DQS#2 DM2 48
DDR_A_DQS5
49 DQS2 VSS17 50 DDR_A_D42 1 3 RD20 1 2 66.5_0402_1% M_ODT0
S
1
DDR_A_D47 53 DQ18 DQ23 54 RD21 RD22 1 2 66.5_0402_1% M_ODT1
55 DQ19 VSS19 56 DDR_A_D52
G
2
DDR_A_D51 57 VSS20 DQ28 58 DDR_A_D53 220K_0402_5% RD23 1 2 66.5_0402_1% M_ODT2
59 DQ24 DQ29 60 M_ODT2 <16>
DDR_A_D50
2
61 DQ25 VSS21 62 DDR_A_DQS#6 RD24 1 2 66.5_0402_1% M_ODT3
63 VSS22 DQS#3 64 M_ODT3 <16>
DDR_A_DQS6
65 DM3 DQS3 66
67 VSS23 VSS24
1
DDR_A_D49 68 DDR_A_D54 @
69 DQ26 DQ30 70 SM_PG_CTRL
DDR_A_D48 DDR_A_D55 RD25 SM_PG_CTRL <4>
71 DQ27 DQ31 72
VSS25 VSS26 2M_0402_5%
2
C C
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA <5>
<5> DDR_CKE0_DIMMA
75 CKE0 CKE1 76
VDD1 VDD2
77 78 DDR_A_MA15
<5> DDR_A_BS2 DDR_A_BS2 79 NC1 A15 80
DDR_A_MA14
BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86
DDR_A_MA7
A9 A7
87 88
DDR_A_MA8 89 VDD5 VDD6 90
DDR_A_MA6
A8 A6
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 94
DDR_A_MA2
A3 A2
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 100
M_CLK_DDR0 101 VDD9 VDD10 102
M_CLK_DDR1 M_CLK_DDR1 <5>
<5> M_CLK_DDR0 CK0 CK1
M_CLK_DDR#0 103 104 M_CLK_DDR#1 M_CLK_DDR#1 <5>
<5> M_CLK_DDR#0 CK0# CK1#
105 106
DDR_A_BS1 DDR_A_BS1 <5>
BA1
<5> DDR_A_BS0 DDR_A_BS0 109 A10/AP 110 DDR_A_RAS#
BA0 RAS# 112 DDR_A_RAS# <5>
111
<5> DDR_A_WE# DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# DDR_CS0_DIMMA# <5>
WE# S0#
<5> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
117 CAS# ODT0 118
DDR_A_MA13 119 VDD15 VDD16
120 M_ODT1 +V_VDDR_REFA_CA
A13 ODT1 122
DDR_CS1_DIMMA# 121
<5> DDR_CS1_DIMMA# S1# NC2
123 124
VDD17 VDD18 +V_VDDR_REFA_CA
125 126
127 NCTEST VREF_CA 128
VSS27 VSS28
DDR_A_D0 129 130 DDR_A_D5
K
0.1U_0402_16V7
DQ32 DQ36
133 DQ33 DQ37 134
CD3
1
DDR_A_DQS#0 135 VSS29 VSS30 136
DQS#4 DM4
DDR_A_DQS0 137 138
139 DQS4 VSS31 140
DDR_A_D3
VSS32 DQ38 2
DDR_A_D6 143 DQ34 DQ39 144
145 DQ35 VSS33 146
DDR_A_D18
B
DDR_A_D21 147 VSS34 DQ44 148
DDR_A_D19
B
DDR_A_D20 149 DQ40 DQ45 150

151 DQ41 VSS35 152
DDR_A_DQS#2
153 VSS36 DQS#5 154
DDR_A_DQS2
155 DM5 DQS5 156
157 VSS37 VSS38 158
DDR_A_D17 DDR_A_D22
159 DQ42 DQ46 160
DDR_A_D16 DDR_A_D23
161 DQ43 DQ47 162
+1.35V_VDDQ DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37
DDR_A_D33 165 DQ48 DQ52 166
DDR_A_D32
167 DQ49 DQ53 168
169 VSS41 VSS42 170
DDR_A_DQS#4
171 DQS#6 DM6 172
DDR_A_DQS4
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
173 DQS6 VSS43 174 DDR_A_D35

CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
1 1 1 1 1 1 1 1
@ @ DDR_A_D38 177 DQ50 DQ55 178
@ @ 179 DQ51 VSS45 180
DDR_A_D63
2 2 2 2 2 2 2 2 DDR_A_D62 181 VSS46 DQ60 182
DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS47 186
DDR_A_DQS#7
187 VSS48 DQS#7 188
DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D60 191 VSS49 VSS50 192
DDR_A_D56 +0.6V_0.675VS
+1.35V_VDDQ 193 DQ58 DQ62 194
DDR_A_D61 DDR_A_D57
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 PCH_SMBDATA
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
+3VS 201 VDDSPD SDA 202 PCH_SMBDATA <16,7>
CD24
10U_0603_6.3V6M
PCH_SMBCLK
K
0.1U_0402_16V7
K
0.1U_0402_16V7
K
0.1U_0402_16V7
1 1 1 1 1 1 1 1 PCH_SMBCLK <16,7>
203 SA1 SCL 204
CD17
CD19
CD21
1 VTT1 VTT2 +0.6V_0.675VS 1 1 1
CD55
CD56
CD57
CD58
CD63
CD64
CD65
CD66
205 206
2 2 2 2 2 2 2 2 G1 G2
@ @ @
2 FOX_AS0A626-U4R6-7H 2 2 2
CONN@
A A

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L DIMM0
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B972P
5 4 3 2 1
5 4 3 2 1
+V_VDDR_REFB_DQ +1.35V_VDDQ +1.35V_VDDQ
JDIMM2
+V_VDDR_REFB_DQ 1 2
3 VREF_DQ VSS1 4
DDR_B_D12
VSS2 DQ4
DDR_B_D8 5 6 DDR_B_D9
K
0.1U_0402_16V7
<5> DDR_B_D[0..63] DQ0 DQ5 8
DDR_B_D14 7
CD27
1
9 DQ1 VSS3 10 DDR_B_DQS#1
<5> DDR_B_DQS[0..7]
11 VSS4 DQS#0 12
DDR_B_DQS1
D 13 DM0 DQS0 14 D
<5> DDR_B_DQS#[0..7] 2 15 VSS5 VSS6 16
DDR_B_D10 DDR_B_D13
DDR_B_D11 17 DQ2 DQ6 18
DDR_B_D15
<5> DDR_B_MA[0..15] 19 DQ3 DQ7 20
DDR_B_D28 21 VSS7 VSS8 22
DDR_B_D25
DDR_B_D29 23 DQ8 DQ12 24
DDR_B_D24
25 DQ9 DQ13 26
DDR_B_DQS#3 27 VSS9 VSS10 28
DDR_B_DQS3 29 DQS#1 DM1 30 DDR3_DRAMRST# DDR3_DRAMRST# <15,4>
31 DQS1 RESET# 32
DDR_B_D30
DDR_B_D27 35 DQ10 DQ14 36
DDR_B_D31
37 DQ11 DQ15 38
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45
DDR_B_D41 41 DQ16 DQ20 42
DDR_B_D44
43 DQ17 DQ21 44
DDR_B_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D47
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
DDR_B_D42 53 DQ18 DQ23 54
55 DQ19 VSS19 56
DDR_B_D61
DDR_B_D56 57 VSS20 DQ28 58
DDR_B_D60
DDR_B_D57 59 DQ24 DQ29 60
61 DQ25 VSS21 62
DDR_B_DQS#7
63 VSS22 DQS#3 64
DDR_B_DQS7
65 DM3 DQS3 66
DDR_B_D63
69 DQ26 DQ30 70
DDR_B_D58 DDR_B_D62
71 DQ27 DQ31 72
VSS25 VSS26
DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB DDR_CKE1_DIMMB <5>

<5> DDR_CKE0_DIMMB
75 CKE0 CKE1 76
VDD1 VDD2
77 78 DDR_B_MA15
<5> DDR_B_BS2 DDR_B_BS2 79 NC1 A15 80
DDR_B_MA14
BA2 A14
C 81 82 C
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86
DDR_B_MA7
A9 A7
87 88
DDR_B_MA8 89 VDD5 VDD6 90
DDR_B_MA6
A8 A6
DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
93 94
DDR_B_MA2
A3 A2
DDR_B_MA1 97 98 DDR_B_MA0
A1 A0
99 100
M_CLK_DDR2 101 VDD9 VDD10 102
M_CLK_DDR3 M_CLK_DDR3 <5>
<5> M_CLK_DDR2 CK0 CK1
<5> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3 M_CLK_DDR#3 <5>
CK0# CK1#
105 106
DDR_B_BS1 DDR_B_BS1 <5>
BA1
<5> DDR_B_BS0 DDR_B_BS0 109 A10/AP 110 DDR_B_RAS# DDR_B_RAS# <5>
BA0 RAS# 112
111
<5> DDR_B_WE# DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMB# DDR_CS0_DIMMB# <5>
WE# S0#
<5> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 M_ODT2 <15>
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16
120 M_ODT3 M_ODT3 <15>
+V_VDDR_REFA_CA
A13 ODT1 122
DDR_CS1_DIMMB# 121
<5> DDR_CS1_DIMMB# S1# NC2
123 124
VDD17 VDD18 +V_VDDR_REFA_CA
125 126
127 NCTEST VREF_CA 128
VSS27 VSS28
K
0.1U_0402_16V7
DDR_B_D1 131 DQ32 DQ36 132
DDR_B_D0
133 DQ33 DQ37 134
CD29
VSS29 VSS30 136 1
DDR_B_DQS#0 135 DM4
DDR_B_DQS0 137 DQS#4 138
DQS4 VSS31
139 140 DDR_B_D2
VSS32 DQ38 2
DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS33 146
DDR_B_D16
VSS34 DQ44
DDR_B_D21 147 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
DQ41 VSS35
151 152 DDR_B_DQS#2
153 VSS36 DQS#5 154
DDR_B_DQS2
DM5 DQS5 156
155
B
DDR_B_D22 157 VSS37 VSS38 158
DDR_B_D19
B
DDR_B_D23 159 DQ42 DQ46 160

DDR_B_D18
161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166
DDR_B_D32
167 DQ49 DQ53 168
DDR_B_DQS4 171 DQS#6 DM6 172
+1.35V_VDDQ 173 DQS6 VSS43 174 DDR_B_D34
DDR_B_D35 175 VSS44 DQ54 176 DDR_B_D38
DDR_B_D39 177 DQ50 DQ55 178
179 DQ51 VSS45 180
DDR_B_D51
DDR_B_D52 181 VSS46 DQ60 182
DDR_B_D55
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
M
10U_0603_6.3V6
DDR_B_D49 183 DQ56 DQ61 184

CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
1 1 1 1 1 1 1 1
185 DQ57 VSS47 186
DDR_B_DQS#6
187 VSS48 DQS#7 188
DDR_B_DQS6
@ @ @ @ 189 DM7 DQS7 190
2 2 2 2 2 2 2 2 DDR_B_D48 191 VSS49 VSS50 192
DDR_B_D54
193 DQ58 DQ62 194 +0.6V_0.675VS
DDR_B_D53 DDR_B_D50
195 DQ59 DQ63 196
197 VSS51 VSS52 198
199 SA0 EVENT# 200 PCH_SMBDATA
+3VS PCH_SMBDATA <15,7>
201 VDDSPD SDA 202 PCH_SMBCLK
K
0.1U_0402_16V7
203 SA1 SCL 204 PCH_SMBCLK <15,7>
CD50
10U_0603_6.3V6M
K
0.1U_0402_16V7
CD44
K
0.1U_0402_16V7
1 VTT1 VTT2 +0.6V_0.675VS
1
CD46
%
10K_0402_5
RD4
CD45
1 1 1
205 206
G1 G2
+1.35V_VDDQ 2 +3VS FOX_AS0A626-U4R6-7H
2 2 2
2
CONN@
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
K
1U_0402_6.3V6
1 1 1 1 1 1 1 1
CD59
CD60
CD61
CD62
CD67
CD68
CD69
CD70
2 2 2 2 2 @ 2 @ 2 2
@
A A

DDR3L DIMM1
0.1
LA-B972P
5 4 3 2 1
5 4 3 2 1
+1.35V_VDDQ
DDR3L VREF +1.35V_VDDQ
D D
1
RD5 RD6
1.8K_0402_1% 1.8K_0402_1%
RD7 RD8
2
1 2 1 2
<CPU> +V_DDR_REFA_R +V_VDDR_REFA_DQ <DDR3L_A> +V_SM_VREF_CNT +V_VDDR_REFA_CA <DDR3L_A_CA>
1 <CPU> 1
2_0402_1% 2_0402_1% <DDR3L_B_CA>
CD52 CD53
1
0.022U_0402_25V7K 0.022U_0402_25V7K
2 RD9 2 RD10
1
RD11 1.8K_0402_1% RD12 1.8K_0402_1%
@ @
24.9_0402_1% 24.9_0402_1%
2
2
2
@ @
+1.35V_VDDQ
C C
1
RD13
1.8K_0402_1%
RD15
<CPU> 1 2 2 +V_VDDR_REFB_DQ <DDR3L_B>

+V_DDR_REFB_R
1
2_0402_1%
CD54
1
0.022U_0402_25V7K
2 RD17
1
RD19 1.8K_0402_1%
@
24.9_0402_1%
2
2
B B
A A

DDR3L VREF
LA-B972P 0.1
5 4 3 2 1
5 4 3 2 1
JPHW7 need to short Layout note

+3VS +3VS_RT
Layout note Close to
@ JPHW 7 Close to Pin11 Pin27 ※ROM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.
80mil 1 2
80mil Close to LT5 Close to Pin18 Close toPin13 Close to Pin7
1 2 EP mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.
JUMP_43X79 +SW R_VDD +SW R_V12
EEPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.
〈 ※Default mode 〉
10U_0603_6.3V6M
0.1U_0402_16V4Z
22U_0603_6.3V6M
0.1U_0402_16V4Z
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout note 1 1 1 1 1 1 1 1 1
Close to Pin3
CT9
CT7
CT8
CT10
CT11
CT12
CT13
CT14
CT15
+3VS_RT +3VS_RT
D +DP_V33 2 2 2 2 2 2 2 2 2 D
2132S@
2
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
1 1 1 LVDS@ RT2 RT3
LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ LVDS@ 4.7K_0402_5% LVDS@ 4.7K_0402_5%
CT16
CT17
CT18
1
2 2 2 MIIC_SDA MIIC_SCL
+3VS_RT 2132S@
2
LVDS@ LVDS@ LVDS@ UT1 @
LVDS@ 19 LVDS_CLKP RT4 RT5
TXEC+ LVDS_CLKP <19>
LT6 2 1 +DP_V33 40mil 3 20 LVDS_CLKN LVDS@ 4.7K_0402_5% 4.7K_0402_5%
DP_V33 TXEC- LVDS_CLKN <19>
FBMA-L11-201209-221LMA30T_0805
LVDS@ 100mil 13 21 LVDS_TXP2 PIN30 PIN31
1
LT5 2 1 +SW R_VDD SW R_VDD TXE2+ 22
40mil 18
Power
80mil LVDS_TXN2
LVDS
FBMA-L11-201209-221LMA30T_0805 PVCC TXE2-
+SW R_V12 2 1 +SW R_LX 40mil 12 23 LVDS_TXP1 <CONN>
SWR / LDO Mode select @ LT7 0_1206_5% 40mil 11
40mil 27
SW R_LX
SW R_VCCK
TXE1+
TXE1-
24 LVDS_TXN1
LVDS_TXP1 <19>
LVDS_TXN1 <19>
VCCK 25 LVDS_TXP0
40mil 7 DP_V12 TXE0+ LVDS_TXP0 <19>
LDO SWR 26 LVDS_TXN0
TXE0- LVDS_TXN0 <19> +3VS_RT
<SI> LT7 change to 0 ohm short pad LVDS@
2132S Do not support mount LT7

use LDO mode translator only RTD2132S LCD_EDID_CLK RT6 1
LVDS@
2 4.7K_0402_5%
EDP_CPU_AUX 2 LCD_EDID_DATA RT7 1 2 4.7K_0402_5%

1 AUX_P
DP-IN
14 DP_INT_PWM
EDP_CPU_AUX# DP_INT_PWM <19> <CONN>
GPIO
AUX_N GPIO(PW M OUT) 15 +DP_ENVDD +DP_ENVDD <19>
5 GPIO(Panel_VCC) 16 BKL_PW M_CPU
2132R Use 0 ohm mount LT7 EDP_CPU_LANE_P0
LANE0P GPIO(PW M IN) BKL_PW M_CPU <4,8> <CPU>
EDP_CPU_LANE_N0 6 17 TS_BKOFF# PIN15 PIN16 Accept voltage input (high level)
LANE0N GPIO(BL_EN)
C C
※ If use 2132R, please select LDO mode asdefault. <30,32,7> EC_SMB_CK2
9
CIICSCL1
LVDS MIICSCL1 29 LCD_EDID_CLK 2132S TL_ENVDD 2132S 3.3V
10 28 LCD_EDID_DATA
<CPU CTRL> <30,32,7> EC_SMB_DA2 CIICSDA1 EDID MIICDA1
Other
LVDS@ 2132R +LCD_VDD * 2132R 1.5~3.3V
<8> EDP_HPD
EDP_HPD 1 2 RT192 32
HPD
ROM MIICSCL0
31 MIIC_SCL
1K_0402_1% 30 MIIC_SDA
MIICSDA0
1
8 * Version R internal Power Switch, can * Version R has internal level shifter, remove
RT11 4 DP_REXT 33
GND output 1A, Rds(on)=0.2 ohm level shifter circuit on AMD platform
2
100K_0402_5% DP_GND
RT8 LVDS@ RTD2132R-CG QFN32

2
12K_0402_1% SA000069200
LVDS@
Different between 2132S and 2132R
1
2132S 2132R
Layout note 1. Support SWR mode 1. Support LDO mode and SWR mode
+LCDVDD
Close to Pin8 2. Internal ROM
+DP_ENVDD 1 2
80ml trace width RT9 0_0805_5% 3. Support LCD_VDD(internal Power switch)
LVDS@
4. Integrates Level shifter
1
2
Close to Pin15 RT10
CT23 100K_0402_5%
CC102 1 2 .1U_0402_16V7K EDP_CPU_AUX 4.7U_0603_6.3V6K
<CPU> <4> EDP_CPU_AUX_C
LVDS@ 1
LVDS@
2
CC101 1 2 .1U_0402_16V7K EDP_CPU_AUX#
<4> EDP_CPU_AUX#_C
B CC98 1 2 .1U_0402_16V7K EDP_CPU_LANE_P0 B
<4> EDP_CPU_LANE_P0_C
2 .1U_0402_16V7K EDP_CPU_LANE_N0
Close to Panel conn. <CPU by PASS eDP>
CC97 1
<4> EDP_CPU_LANE_N0_C <eDP to connector>
0_0804_8P4R_5% RP9 eDP@ SD309000080

EDP_CPU_LANE_N0 1 8 EDP_LANE_N0 EDP_AUX 4 5 LCD_CLK
EDP_CPU_LANE_P0 2 7 EDP_LANE_P0 EDP_AUX# 3 6 LCD_DATA LCD_CLK <19>
EDP_CPU_AUX 3 6 EDP_AUX EDP_LANE_N0 2 7 LVDS_TXN2_LN0 LCD_DATA <19>
EDP_CPU_AUX# 4 5 EDP_AUX# EDP_LANE_P0 1 8 LVDS_TXP2_LP0 LVDS_TXN2_LN0 <19>
10/9 colay eDP use close Connector LVDS_TXP2_LP0 <19>
eDP@ SD309000080
RP6 0_0804_8P4R_5%
2 4
EDP_HPD RT34 1 eDP@ 2 0_0201_5% EDP_HPD_PANEL

EDP_HPD_PANEL <19>
@ BKL_PW M_CPU RT35 1 eDP@ 2 0_0201_5% DP_INT_PWM
RT14 1 2 0_0402_5%
CT24
@ <LVDS to connector>
<PV>Change PR37 pin define , Add PR38.
1 2
+3VS <PV>PR36 Change to RP6.
<SI> Update UT3 footprint (As UV11) 0_0804_8P4R_5%
0.1U_0402_16V7K LCD_EDID_CLK 1 8 LCD_CLK PR37 change to RP9.
5
LCD_EDID_DATA 2 7 LCD_DATA
TS_BKOFF# 1
UT3
LVDS_TXN2 3 6 LVDS_TXN2_LN0 PR38 change to RP10.
<RTS2132>
P
B 4 LVDS_TXP2 4 5 LVDS_TXP2_LP0
EC_BKOFF# 2 Y EC_TS_BKOFF# <19> <LVDS Panel>
<EC CTRL> <30> EC_BKOFF# A
G
A LVDS@ SD309000080 A
RP10
TC7SH08FUF_SSOP5
3
1
LVDS@
RT12 PD 100K on LVDS page
100K_0402_5%
LVDS@
<PV> Add RT12
2

eDP@ 2013/3/1 2015/3/1 Title
RT15 1 2 0_0402_5%
Issued Date Deciphered Date
LVDS Translator-RTD2132R
TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTIAL
D E P A R TM E N T E X C E P T A S A U TH O R I Z E D B Y C O M P A L E L E C TR O N IC S , IN C . N E ITH E R TH IS S H E E T N O R TH E IN F O R M A T I O N IT C O N TA IN S LA-B972P 0.1
5 4 3 2 1
5 4 3 2 1
LVDS Power 2132S@ +3VALW

+3VS
W=60mils W=60mils
eDP@
INVPWR_B+ B+
UG1 Touch Screen Power
1
5 1 eDP@ @EMI@
IN OUT +LCDVDD
RTS2 0_0805_5% 2 1 L1
0_0201_5% 2 2132S@ 2132S@
GND 100K_0402_5%
@EMI@ 0_0805_5%
0.1U_0402_16V7K
2
RG1 1 eDP@2 4 3 @
CG3
SS EN 1 eDP@ 1 2 1 L2
1 CG2
1
eDP@ 1 1
eDP@ D
1
D 2132S@ CG1 APL3512_SOT23-5 4.7U_0603_6.3V6K RTS1 @EMI@ C117 C118 SM010014520 3000ma D
eDP@ 2 2 QTS1 2 680P_0402_50V7K 68P_0402_50V8J
1500P_0402_50V7K 2 1K_0402_5%
G
TOUCH_ON# <30> 220ohm@100mhz
2N7002K_SOT23 2 2 DCR 0.04
CTS2 S
3
+VCC_TOUCH 1 2
eDP@
2 2
0.047U_0402_16V7K
G
RG3 1 @ 2 0_0402_5%
<18> +DP_ENVDD
1 3 +3VS
S
R172 1 2 0_0402_5%
<PV>Change Touch power to 3V
<8> ENVDD_CPU 1 eDP@
CTS1 eDP@
eDP@ 0.1U_0402_16V4Z QTS2
S TR LP2301ALT1G 1P SOT-23-3
2
<PV>Change BOM structure
Camera @
R170 1 2 0_0402_5%
L12 EMI@
D5
1 2 USB20_N4_R
<10> USB20_N4 1 2 1 220P_0402_50V7K INVTPWM
USB20_P4_R 2 C121 2
Part Number = SM070003Y00 1
4 3 USB20_P4_R USB20_N4_R 3 C122 2 1 220P_0402_50V7K DISPOFF#
<10> USB20_P4 4 3
C C
WCM-2012-900T_4P PESD5V0U2BT_SOT23-3
1 R171 2 0_0402_5% @ESD@ SCA00000U10
R2591 @ 2 INVTPWM
<30> EC_INVT_PWM
0_0402_5%
@
LCD/LED PANEL Conn.
<PV>L12 change PN. +LCDVDD
1
<18> DP_INT_PWM R258 1 @ 2 0_0402_5% @

R163 CONN@
10K_0402_5% JLVDS1
1
1
2 41
D3 2 G1
2
LCD_CLK 3 42
<18> LCD_CLK 3 G2
D_MIC_L_CLK 2 LCD_DATA 4 43
<18> LCD_DATA 4 G3
1 5 44
5 G4
D_MIC_L_DATA 3 6 45
<18> LVDS_TXP0 6 G5
7 46
<18> LVDS_TXN0 7 G6
8
PESD5V0U2BT_SOT23-3 8
9
@ESD@ SCA00000U10 <18> LVDS_TXP1 9
10
<18> LVDS_TXN1 10
R166 33_0402_5% <DB>LA1/LA2 closed to Aduio codec 11
11
<18> EC_TS_BKOFF# 1 2 DISPOFF# 12
<18> LVDS_TXP2_LP0 12
EC_TS_BKOFF# EMI@ 13
<18> LVDS_TXN2_LN0 13
LA1 FBMA-L10-160808-301LMT_2P 14
14
1
D_MIC_CLK 1 2 D_MIC_L_CLK 15
B <25> D_MIC_CLK <18> LVDS_CLKP 15 B
R167 D_MIC_DATA 1 @ 2 D_MIC_L_DATA 16
<25> D_MIC_DATA <18> LVDS_CLKN 16
10K_0402_5% LA2 0_0603_5% 17
<PV>LA1,LA2 change PN, LA2 change to 0ohm. 17
USB20_N4_R 18
<MV>LA2 change to short pad. 18
USB20_P4_R 19
19
2
20
20
USB20_P5_R 21
21
USB20_N5_R 22
22
R260
TS_GPIO_CPU TS_GPIO DISPOFF# 23
<9> TS_GPIO_CPU 23
1 @ 2 0_0402_5% INVTPWM 24
24
TS_GPIO_EC R2611 @ 2 TS_GPIO 25
<30> TS_GPIO_EC 25
0_0402_5% 26
26
INVPWR_B+ 27
27
28
28
29
29
+VCC_TOUCH 30
30
<PV>L13 change PN,BS. 31
31
32
<PV>Remove R168,R169. TouchScreen @
+3VS
33
32
33
R173 1 2 0_0402_5% 34
34
D_MIC_L_CLK 35
35
L13 eDPEMI@ D_MIC_L_DATA 36
D6 36
1 2 USB20_P5_R 37
<10> USB20_P5 1 2 37
USB20_P5_R 2 38
<18> EDP_HPD_PANEL 38
1 Part Number = SM070003Y00 39
39
USB20_N5_R 3 4 3 USB20_N5_R 40
<10> USB20_N5 4 3 40
A WCM-2012-900T_4P STARC_107K40-000001-G2
PESD5V0U2BT_SOT23-3 A
@ESD@ SCA00000U10 1 R174 2 0_0402_5% <PV>JLVDS1 pin40 change to NC.

@
LVDS Connector
LA-B972P
T HIS SH EET O F EN G IN EER IN G D R AW IN G IS T H E PR O PR IET AR Y PR O PER T Y O F C O MPAL ELEC T R O N IC S, INC. AN D CONT AINS CONFIDENT IAL
SSize Document Number Rev
D EPAR T MEN T EXC EPT AS AU T H O R IZ ED BY C O MPAL ELEC T R O N IC S, INC. NEIT HER T HIS SH EET N O R T H E IN F O R MAT IO N IT CONT AINS 0.1
5 4 3 2 1
5 4 3 2 1
+3VS
PCH_DPB_P0 0.1U_0402_16V7K 1 2 CG27 PCH_DPB_P0_C
<4> PCH_DPB_P0 PCH_DPB_N0 0.1U_0402_16V7K 1
<4> PCH_DPB_N0 2 CG28 PCH_DPB_N0_C

<CPU> <4> PCH_DPB_N1 2 CG30 PCH_DPB_N1_C
1
RG47
<4> PCH_DPB_N2 2 CG32 PCH_DPB_N2_C 1M_0402_5%
2
<4> PCH_DPB_P3
2
D
PCH_DPB_N3 0.1U_0402_16V7K 1 2 CG34 PCH_DPB_N3_C D
<4> PCH_DPB_N3
1 6 HP_DETECT
<8> PCH_DDPB_HPD
20K_0402_5%
QG1A 1
5
6
7
8
5
6
7
8
1
2N7002KDW_SOT363-6 CM17@
5V Level RG56 220P_0402_50V7K
2N7002KDW_SOT363-6 2
QG1B
4
3
2
1
4
3
2
1
3 4
2
RP3 RP4
470_0804_8P4R_5% 470_0804_8P4R_5%
5
+3VS
+3VS
@
PCH_DPB_P3_C RG59 1 2 0_0402_5% HDMI_R_CK+
4 3
4 3
C C
5
EMI@ CMMI21T-900Y-N
SM070003K00 LM13 1 2 QG2B
1 2
PCH_DDPB_CLK 4 3 HDMI_SCLK
<8> PCH_DDPB_CLK
PCH_DPB_N3_C RG60 1 2 0_0402_5% HDMI_R_CK-
@ 2N7002DWH_SOT363-6
SB00000DH00
@ +3VS
PCH_DPB_N0_C RG61 1 2 0_0402_5% HDMI_R_D0-
1 2
1 2
EMI@ LM14
2
SM070003K00CMMI21T-900Y-N
4 3
4 3
PCH_DDPB_DAT 1 6 HDMI_SDATA
<8> PCH_DDPB_DAT
PCH_DPB_P0_C RG63 1 2 0_0402_5% HDMI_R_D0+
@ 2N7002DWH_SOT363-6
+HDMI_5V_OUT SB00000DH00 QG2A
PCH_DPB_P1_C RG64 1 @ 2 0_0402_5% HDMI_R_D1+
4 3 +3VS
4 3 RG105
EMI@ CMMI21T-900Y-N 1 8 HDMI_SDATA
SM070003K00 LM15 1 2 2 7 HDMI_SCLK
1 2
3 6 PCH_DDPB_DAT
PCH_DPB_N1_C RG65 1 2 0_0402_5% HDMI_R_D1- 4 5 PCH_DDPB_CLK
@
2.2K_0804_8P4R_5%
PCH_DPB_P2_C RG66 1 @ 2 0_0402_5% HDMI_R_D2+
B B
4 3
4 3
EMI@ CMMI21T-900Y-N HDMI Conn.
SM070003K00 LM16 1 2
1 2
PCH_DPB_N2_C RG70 1 2 0_0402_5% HDMI_R_D2-
@ JHDMI1
HP_DETECT 19
SC300002800 HP_DET
+HDMI_5V_OUT 18
@ESD@ DG1 +5V
17
HP_DETECT 11 1 0 9 HP_DETECT HDMI_SDATA DDC/CEC_GND
16
HDMI_SCLK SDA
15
HDMI_SDATA 2 2 9 8 HDMI_SDATA SCL
W=40mils 14
Reserved
FG1 13
+HDMI_5V_OUT HDMI_SCLK 4 4 7 7 HDMI_SCLK HDMI_R_CK- CEC 20
12
@ @ CK- GND
11 21
3 CK_shield GND
10P_0402_50V8J
10P_0402_50V8J
5 5 6 6 1 1 HDMI_R_CK+ 10 22
OUT CM26 CM27 HDMI_R_D0- CK+ GND
9 23
1 33 D0- GND
+5VS 8
IN HDMI_R_D0+ D0_shield
1 7
2 8 2 2 HDMI_R_D1- D0+
6
GND D1-
5
CG46 IP4292CZ10-TB HDMI_R_D1+ D1_shield
4
0.1U_0402_16V7K 2 HDMI_R_D2- D1+
3
AP2330W-7_SC59-3 D2-
2
HDMI_R_D2+ D2_shield
1
D2+
CONCR_099AKAC19NBLCNF
A A
CONN@

HDMI Conn/Level shift
Rev
0.1
LA-B972P
5 4 3 2 1
5 4 3 2 1
+3VS_WLAN
1
D +3VS_WLAN RN3 +1.5VS_WLAN +3VS_WLAN D
<41> MC_WAKE#
10K_0402_5%
short@ 0_0201_5% JMINI1
2
<30> EC_PCIE_WAKE# RN13 1 2 1 2
1 2
3 4
3 4
BT_ON_EC 5 6
5 6
<7> MINI1_CLKREQ# 7 8
7 8
9 10
9 10
11 12
<7> CLK_PCIE_MINI1# 11 12
13 14
<7> CLK_PCIE_MINI1 13 14
15 16
15 16
17 18
17 18
19 20 WL_OFF# WL_OFF# <10,9>
19 20
21 22
21 22 PLT_RST# <23,28,30,32,8>
23 24
<6> PCIE_PRX_DTX_N6 23 24 +3VS_WLAN
25 26
<6> PCIE_PRX_DTX_P6 25 26
27 28
27 28
29 30
29 30
<6> PCIE_PTX_C_DRX_N6 31 32
31 32
33 34
<6> PCIE_PTX_C_DRX_P6 33 34
35 36
35 36 USB20_N3 <10>
37 38
37 38 USB20_P3 <10>
39 40
C 39 40 C
41 42
41 42
43 44
43 44 MINI1_LED# <30>
45 46
45 46
47 48
47 48
E51TXD_P80DATA 49 50
<30> E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52
<30> E51RXD_P80CLK 51 52
53 54
GND1 GND2
1
2
RN7
R216 BELLW_80053-1021 4.7K_0402_5%
100K_0402_5% CONN@
<30> BT_ON_EC BT_ON_EC 1 RC160 2 E51RXD_P80CLK
2
1K_0402_1%
1
+3VS_WLAN
+1.5VS +1.5VS_WLAN
B RN1 @ B
1 2 <PV>Change WLAN power to single load switch.
1
0_0603_5% CN1 +5VALW +3VALW
Q23
4.7U_0603_6.3V6K
2 1 7
VIN VOUT +3VS_WLAN_R
@ 2 8
VIN VOUT
1
WL_PWREN_EC 3 6
10U_0603_6.3V6M
C571
+3VS_WLAN_R +3VS_WLAN <30> WL_PWREN_EC ON CT
1
4 2
J
100P_0402_50V8
C558
R271 @ VBIAS 5
1 2 GND 9 2
GND
0.1U_0402_16V7K
0_0805_5% 1@
CN3
1
CN2 TPS22967DSGR_SON8_2X2
<PV>R271 change to 0805 4.7U_0603_6.3V6K
2 2
<PV>C558 change to 100pf for SVTP spec.
A A

WLAN
LA-B972P 0.1
5 4 3 2 1
5 4 3 2 1
JHDD1
2.5" SATA HDD connector +5VS_HDD1 1
GND GND
23
C155 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 24
<6> SATA_PTX_DRX_P0 A+ GND
C156 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
<6> SATA_PTX_DRX_N0
4 A-
C153 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND
+5VS <6> SATA_PRX_DTX_N0 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 B-
10U_0603_6.3V6M
0.1U_0402_16V7K
C154 1
<6> SATA_PRX_DTX_P0 7 B+
C150
1 1
@ 0_0603_5%
C149
GND
D
R201 1 2 +5VS_HDD1
<SI>RS11 change to un pop D
@ 0_0603_5% +3VS RS11 1 @ 2 0_0402_5% 8

R212 1 2 2 2 VCC3.3
9
RS12 1 JHDD_P10 10 VCC3.3
<8,9> DEVSLP1 11 VCC3.3
@ 2 0_0402_5%
12 GND
GND
13
14 GND
15 VCC5
+5VS_HDD1 VCC5
16
17 VCC5
18 GND
19 RESERVED
20 GND
21 VCC12
22 VCC12
VCC12
SANTA_193202-1
CONN@
Change to dual load switch for ODD and WLAN

<PV>Q22 change to single load switch.
C C
+5VALW +5VS
Q22
+5VS_ODD
1 7 +5VS_ODD
Pleace near ODD Connector
VIN VOUT 8
2
VIN VOUT
0.1U_0402_25V6K
0.1U
ODD_PWR 3 6 C555 1 2
10U_0603_6.3V6M
1000P_0402_50V7K
K
10U_0805_10V6
<9> ODD_PWR ON CT
22U_0805_6.3V6M
1 1 1 1 1
100P_0402_50V8J
C576
CC73
CS13
4
CS16
CS12
VBIAS 5
<MV>Add 22UF for RF suggestion ,4/10.
GND 9 2 2 @ 2 2 2
GND
TPS22967DSGR_SON8_2X2
JODD1
1
CS11 2 1 0.01U_0402_16V7K GND
<6> SATA_PTX_DRX_P1 SATA_PTX_C_DRX_P1 2
RX+
<6> SATA_PTX_DRX_N1 CS14 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3
RX-
B 4 B
CS15 1 0.01U_0402_16V7K GND
SATA_PRX_C_DTX_N1 5
<6> SATA_PRX_DTX_N1 TX-
2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6
<6> SATA_PRX_DTX_P1 TX+
CS18 2 7
GND
8
<6> ODD_PLUG# DP
9
+5V
10
ODD_DA# 11 +5V
<9> ODD_DA# MD
12 14
GND GND1
13 15
GND GND2
<SI> Delete Q84, R954 OCTEK_SLS-13HCAB
1
CS17 CONN@
0.1U_0402_25V6K
2 ESD@
Place CS17 close to JODD
A A

ODD/SATA Conn
B
LA-B972P 0.1
5 4 3 2 1
5 4 3 2 1
JHW1 need to short LDO mode Switcing mode

@ JHW1 LL1 SMT @
1
1 2
2
+LAN_VDD_3V3 Rising time RTL8151G (LDO mode)
CL21 SMT @
+3VALW JUMP_43X79
@ UG5
need>0.5mS and <100mS LL2 @ SMT
+LAN_VDD_1V0
5 1
CL8 @ SMT
IN OUT +LAN_VDD_3V3
LL1 1 20_0603_5% CL14 & CL15 close UL1 Pin22
2
GND
CL26 & CL27 close UL1 Pin30
1@RL35 20_0201_5% 1 4 3 @LL2
SS EN +LAN_REGOUT 1 2
@CL28 2.2UH +-5% NLC252018T-2R2J-N
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
APL3512_SOT23-5 1 1 1 1 1 1 1 1 1
0.1U_0402_16V7K
D 2 D
CL8
1500P_0402_50V7K CL12 CL13
CL23
1 @
CL11 CL14 CL15 CL26 CL27
CL21 @ @ 8161@ @8161@ 8166@ @8166@
@ 2 2 2 2 2 2 2 2 2
RL29 2 1 10K_0402_5%LAN_PWR_EN_R 2
<9> LAN_PWR_EN
Place CL11~CL13 close UL1 Pin 3, 8 , 22 EC_LAN_ISOLATEB# 2 1 +3VS

LL2, CL8, CL23 for 8161 1K_0402_5% RL5
1
2
+LAN_VDD_3V3 +VDDREG @CL29
CL8 & CL18 close LL2 RL8
2 0.1U_0402_16V7K
8151/8166 Co‐Lay 15K_0402_5%
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+LAN_VDD_3V3=40mil
0.1U_0402_16V7K
0.1U_0402_16V7K
1
0.1U_0402_16V7
1 1 1 1 1 1 8161@
L
CL10
UL1 +LAN_VDD_1V0
CL16
@8161@ @ +VDDREG=40mil
CL20 CL19 CL9 CL5
@ @
2 2 2 @2 2 2 LAN_MDIP0 1 3
+LAN_REGOUT=60mil XTLO
MDIP0 AVDD10 8 XTLO <31>
LAN_MDIN0 2
K 4 MDIN0 AVDD10 30 +LAN_VDD_3V3 XTLI
LAN_MDIP1
5 MDIP1 AVDD10 22 +LAN_VDD_3V3
LAN_MDIN1
LAN_MDIP2 6 MDIN1 DVDD10 2 1 XTLO
7 MDIP2 11 +LAN_VDD_3V3
LAN_MDIN2 1M_0402_5% RL7
MDIN2 AVDD33 32
1
LAN_MDIP3 9 @
MDIP3 AVDD33 XTAL@
LAN_MDIN3 10 RL15
MDIN3
CL9 & CL5 close to UL1: Pin 11,32 CL10& CL16 close to UL1: Pin 23 23
VDDREG(VDD33) 24
+VDDREG RL10 1 2 10K_0402_5%
+LAN_REGOUT 0_0603_5%
REGOUT
CL19 close to UL1: Pin 32 <7> LAN_CLKREQ# LAN_CLKREQ#2 @ RL6 1 0_0201_5% LAN_CLKREQ#_R 12 RTL8111G
2
PLT_RST# 19 CLKREQB 21 LANWAKEB XTAL@
<21,28,30,32,8> PLT_RST# PERSTB LANWAKEB 20 EC_PME# <30,9>
3
CL20 close to UL1: Pin 11 EC_LAN_ISOLATEB# YL1
15 ISOLATEB XTAL@ 1 XTAL@ 1
10P_0402_50V8J
10P_0402_50V8J
<7> CLK_PCIE_LAN CLK_PCIE_LAN
16 REFCLK_P
GND OSC
GND OSC
CLK_PCIE_LAN# 27 LED0 TH2 CL25 CL24
<7> CLK_PCIE_LAN# REFCLK_N LED0 26
LED1/GPO TH1
13 LED1/GPO 25 LED2 TH3
<10> PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_P3
PCIE_PTX_C_DRX_N3 14 HSIP LED2(LED1) 2 2
<10> PCIE_PTX_C_DRX_N3
C PCIE_PRX_DTX_P3 CR11 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P3 17 HSIN 28 XTLI C
<10> PCIE_PRX_DTX_P3 CKXTAL1 29
PCIE_PRX_DTX_N3 CR13 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N3 18 HSOP XTLO
<10> PCIE_PRX_DTX_N3 HSON CKXTAL2
4
RSET 31 33
RSET GND 25MHZ 10PF 5YEA25000102IF50Q3
2
SP050005L00 Footprint
RL11
TSL1 8161@ 2.49K_0402_1% SA00005YT00 <PV>CL24,CL25 change to 10pf.
UL1 8166@
+V_DAC 1 24
1
LAN_MDIN3 2 TCT1 MCT1 23 RP5 SA000063500
RJ45_TX3-
LAN_MDIP3 3 TD1+ MX1+ 22 1 8 RTL8166EH-CG QFN 32P E-LAN CTRL
RJ45_TX3+
TD1- MX1- 2 7 SANTA_130456-291 JLAN1 CONN@
4 21 3 6 RJ45_TX3- 8
LAN_MDIN2 5 TCT2 MCT2 20 RJ45_TX2- 4 5 (SA000063500) 10/100 8166@ PR4- 10
LAN_MDIP2 6 TD2+ MX2+ 19 RJ45_TX2+ RJ45_TX3+ 7 GND 9
TD2- MX2- 75_0804_8P4R_1% (SA00005YT00) Giga 8151@ PR4+ GND
7 18 SD300002E80 2 RJ45_RX1- 6
TCT3 MCT3 17 PR2-
LAN_MDIN1 8 RJ45_RX1- CL2
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_RX1+ SE167100J80 RJ45_TX2- 5 PR3-
TD3- MX3- 10P_1808_3KV
10 15 1 RJ45_TX2+ 4 PR3+
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_TX0- LANGND
LAN_MDIP0 12 TD4+ MX4+ 13 RJ45_TX0+ 1 EMI@ RJ45_RX1+ 3 PR2+
3
TD4- MX4- CL3

LANGND RJ45_TX0- 2
YSLC05CH_SOT23-3
ESD@ 120P_0402_50V8 PR1-

2
DL1
2 1 LANKO_LG-2446S-1 RJ45_TX0+ 1 PR1+
@ @EMI@ SP050006800
CL1 CL4 S X’FORM_ LG-2446S-1 100/1000BASE-TX LAN
1 0.01U_0402_16V7K 2 0.1U_0402_16V7K
TSL1 8166@
1
SCA00000U10
SP050003P00
S X'FORM_ NS892404 ETHERNET 10/100
B
(SP050003P00) 10/100 8166@ B
(SP050006800) Giga 8161@
RR1
+3VS 1 2 +3VS_CR +3VS_CR
0_0603_5%
short@
1 1 Card Reader Connector
CR9 CR10
RTS5239 RR4-RR9 close to chip
4.7U_0402_6.3V6M 2 2 0.1U_0402_16V7K CONN@
CR12-CR13 close to chip or socket JREAD1
UR1 SD_D3_R 1
Close to Chip 1 12 SD_D1 @EMI@ 1 RR2 2 0_0402_5% SD_D1_R 208MHz DAT3
<10> PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_P2
HSIP SP1
PCIE_PTX_C_DRX_N2 2 13 SD_D0 @EMI@ 1 RR4 2 0_0402_5% SD_D0_R @CR12 SD_CMD_R 2
<10> PCIE_PTX_C_DRX_N2 HSIN SP2 +CR_VDD_3V3 CMD
CLK_PCIE_CR 3 14 SD_CLK EMI@ 1 RR5 2 33_0402_5% SD_CLK_R 1 2
<7> CLK_PCIE_CR REFCLKP SP3
<7> CLK_PCIE_CR# CLK_PCIE_CR# 4 16 SD_CMD @EMI@ 1 RR3 2 0_0402_5% SD_CMD_R Close to Conn
2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P2 REFCLKN SP4 @EMI@ 1 RR6 2 0_0402_5% 3 VSS1
CL17 1 5 17 SD_D3 SD_D3_R 6.8P_0402_50V8C
<10> PCIE_PRX_DTX_P2 HSOP SP5
CL18 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N2 6 18 SD_D2 @EMI@ 1 RR7 2 0_0402_5% SD_D2_R +CR_VDD_3V3
<10> PCIE_PRX_DTX_N2 HSON SP6 4 VDD
20 SD_WP
0.1U_0402_16V7K
SP7
SD_CLK_R
4.7U_0603_6.3V6M
1 5
15 12 CR7 CR8 CLK
24 DV33_18 11 +DVDD12 CR14 1U_0402_6.3V4Z Close to Chip 6
CR_CLKREQ#
<7,9> CR_CLKREQ# 23 CLKREQ# DV12_S VSS2
2 1
PLT_RST#
22 PERST# 2 SD_D0_R 7
SD_CD# 21 MS_INS# 9 +3VS_CR DAT0
+3VS_CR 1 2 19 SD_CD# 3V3_IN 7 +AVDD12 SD_D1_R 8
10K_0402_5% RR8 GPIO AV12 10 DAT1
CARD_3V3 +CR_VDD_3V3
SD_D2_R 9
DAT2
6.2K_0402_1% 1 2 RR9 RREF 8 25 SD_CD# 10 12
RREF GND CD G1
RTS5239-GR_QFN24_4X4 SD_WP 11 13
RR9 close to chip WP G2
TAITW_PSDAT0-09GLBS1ZZ4H1
A A
+DVDD12 +DVDD12 +AVDD12 +AVDD12 Close to Chip

+3VS_CR
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1 1
1
CR1 CR2 CR3 CR4

0.1U_0402_16V7K
1 1
CR5 CR6
2
2 2 4.7U_0402_6.3V6M @
2 2
LAN 8111G
0.1
LA-B972P
5 4 3 2 1
A B C D E
RS1 @ 0_0402_5% 1 USB3.0 need support 2.5A

<10> USB3_TX0_P USB3_TX0_P 2 1 CS1 USB3_TX0_C_P 2 USB3TXDP0_C_R change USB PWR SW SA00005VN00
0.1U_0402_16V7K
CMMI21T-900Y-N low active
+5VALW +USB_VCCA
4 3
4 3
EMI@ US1 W=100mils
1 2 W=100mils 1 8
1
1000P_0402_50V7K
2 GND VOUT
2 7
0.1U_0402_16V7K
47U_0805_6.3V6M
LM1 SM070003K00 VIN VOUT
3 6
1 USB3_TX0_N 2 1 CS2 USB3_TX0_C_N 1 USB3TXDN0_C_R VIN VOUT 1
<10> USB3_TX0_N 2 4 5
0.1U_0402_16V7K RS2 @ 0_0402_5% EN FLG @ 1 1 1
CS6
1 G547I2P81U_MSOP8 CS5
CS4
CS3
2 2 2
0.1U_0402_16V7K
RS3 @ 0_0402_5% 1 2
2 USB3RXDP0_C
<10> USB3_RX0_P
CMMI21T-900Y-N @
4 3 <30> USB_ON# USB_ON# 1 2 RS4
4 3
<EC> 0_0402_5% RS5 1 @ 2 USB_OC0# 0_0402_5% USB_OC0# <10,9>
EMI@
1 2
1 2
LM2 SM070003K00
1 2 USB3RXDN0_C @ESD@
<10> USB3_RX0_N
RS6 @0_0402_5% DM1 SCA00000U10
2 USB20_N0_C
RS7 @ 0_0402_5% 1 1
2 USB20_P0_C 3 USB20_P0_C
<10> USB20_P0
LM3 YSLC05CH_SOT23-3
1 2
1 2
2 EMI@ Part Number = SM070003Y00 USB2.0/USB3.0 port 1 2
4 3
4 3 SC300002800 +USB_VCCA
WCM-2012-900T_4P ESD@ DM2 JUSB1
1 2 USB20_N0_C USB3RXDN0_C 11 109 USB3RXDN0_C USB3TXDP0_C_R 9
<10> USB20_N0 1 SSTX+
RS8 @0_0402_5%
USB3RXDP0_C 2 2 9 8 USB3RXDP0_C 8 VBUS
USB3TXDN0_C_R
SSTX-
<PV>LM3 change PN. USB20_P0_C 3
USB3TXDN0_C_R 4 4 7 7 USB3TXDN0_C_R 7 D+
2 GND 10
USB20_N0_C D- GND
USB3TXDP0_C_R 5 5 6 6 USB3TXDP0_C_R USB3RXDP0_C 6 11
4 SSRX+ GND
12
3 3 USB3RXDN0_C 5 GND GND
13
SSRX- GND
8 ACON_TARA4-9K1311
CONN@
IP4292CZ10-TB
@RS13
<PV>LM4,LM5 change PN.
0_0402_5%
3 USB2.0 port x 2 <10> USB20_N2
1 2 USB20_N2_C 3
LM4
1 2 +USB_VCCB E-T_6916K-Q12N-00L
1 2
+5VALW +USB_VCCB
EMI@ Part Number = SM070003Y00
US2 W=100mils 4 3 12 14
W=100mils 4 3 11 12 G2 13
1 8
2 GND VOUT 7 WCM-2012-900T_4P 10 11 G1
3 VIN VOUT 6 1 2 USB20_P2_C 9 10
VIN VOUT 5 <10> USB20_P2 9
4 @RS14 0_0402_5% 8
EN FLG 7 8
1 6 7
G547I2P81U_MSOP8 @RS15 0_0402_5% USB20_P2_C
USB20_N1_C 5 6
CS10 <10> USB20_N1 1 2 USB20_N2_C
4 5
0.1U_0402_16V7K LM5 3 4
2 USB20_P1_C 3
1 2 USB20_N1_C 2
1 2 2
1
EMI@ Part Number = SM070003Y00 1
USB_ON# @RS101 2 4 3
4 3
0_0402_5% RS9 1 @ 2 USB_OC1# USB_OC1# <10> JUSB2
0_0402_5% WCM-2012-900T_4P
1 2 USB20_P1_C
<10> USB20_P1
@RS16 0_0402_5%
4 4

USB 3.0/2.0 conn
B
LA-B972P 0.1
A B C D E
5 4 3 2 1
UA1
+3VS +DVDD +DVDD_IO +1.5VS
20 1 +DVDD
MIC1_R DVDD 1@2 1 2
19 9 +DVDD_IO
MIC1_L DVDD_IO LA3
CA1 1 2 4.7U_0402_6.3V6M INT_MICR_C SUPPRE_ KC FBMA-10-100505-101T 0402
.1U_0402_16V7K
CA5
.1U_0402_16V7K
CA7
18 26 RA2
M
10U_0603_6.3V6
CA6
M
10U_0603_6.3V6
CA8
2 1K_0402_5% CA4 1 MIC2_R AVDD1 +5VS_AVDD
INT_MIC RA3 1 2 4.7U_0402_6.3V6M INT_MICL_C 17 40 +1.5VS_AVDD 0_0603_5% 1 1 1 1 PCB Footprint = R_0402
MIC2_L AVDD2
31 41 +5VS_PVDD
MUTE_LED_CTR 30 MIC1_VREFO_L PVDD1 46
+MIC2_VREFO 29 MIC1_VREFO_R PVDD2 2 2 2 2

MIC2_VREFO
23 45 SPK_R+
LINE2_R SPK_OUT_R+
24 44 SPK_R-
LINE2_L SPK_OUT_R-
Internal Speaker Place near Pin1 Place near Pin9

16 42 SPK_L+
D MONO_OUT SPK_OUT_L+ 43 SPK_L- D
PC_BEEP 12 SPK_OUT_L- +5VS_AVDD +5VS

PCBEEP LA4 +1.5VS_AVDD +1.5VS
+3VS 10 33 HPOUT_R RA4 1 2 75_0402_1% HP_OUTR 1 2
<6> HDA_SYNC_AUDIO SYNC HPOUT_R
32 HPOUT_L RA5 1 2 75_0402_1% HP_OUTL
Headphone FBMA-L11160808601LMA10T_2P 1 2
HPOUT_L
4.7U_0603_6.3V6K
CA10
HDA_RST_AUDIO# LA5
.1U_0402_16V7K
CA9
11
<6> HDA_RST_AUDIO# RESET#
600ohms @100MHz 1A
4.7U_0603_6.3V6K
CA13
SUPPRE_ KC FBMA-10-100505-101T 0402
.1U_0402_16V7K
CA12
1 2
2 CPVDD +3VS 1 @ 2 5 1 2 PCB Footprint = R_0402
RA6 SDATA_OUT 8 SDATA_IN RA7 1 2 22_0402_5%
HDA_SDOUT_AUDIO <6> Main:SM010007Z00
SDATA_IN HDA_SDIN0 <6>
CA17 4.7K_0402_5% CA11 1 2 10U_0603_6.3V6M ALDO_CAP 7
LDO3-CAP 2 1 2nd:SM01000BU00
6
1 4.7U_0603_6.3V6K CA14 1 2 2.2U_0402_6.3V6M ACPVEE 34 BCLK HDA_BITCLK_AUDIO <6> 2 1
CPVEE
CPVDD 36 22
CBN 35 CPVDD LINE1_L 21
CA15 1 2 2.2U_0402_6.3V6M CBP 37 CBN LINE1_R 48 MIC_JD Place near Pin26
CBP SPDIFO/GPIO2
Place near Pin40
15 JDREF RA9 2 1 20K_0402_1% GNDA
JDREF
2 28 AVREF CA16 2 1 .1U_0402_16V7K GNDA
<19> D_MIC_DATA VREF
3 GPIO0/DMIC_DATA 27 CA18 1 2 10U_0603_6.3V6M
<19> D_MIC_CLK GPIO1/DMIC_CLK LDO1_CAP +5VS_PVDD +5VS
39 CA19 1 2 10U_0603_6.3V6M MUTE_LED <26>
LDO2_CAP LA6 600ohms @100MHz 2A
PLUG_IN# RA10 1 2 39.2K_0402_1% SENSEA 13 25 2 RA29 1 100K_0402_5% 1 2
14 SENSE_A AVSS1 38 @ FBMA-L11-201209601LMA20T_2P Main:SM01000NS00
SENSE_B AVSS2
2nd:SM01000EE00
M
10U_0603_6.3V6
CA22
M
10U_0603_6.3V6
CA23
.1U_0402_16V7K
CA20
.1U_0402_16V7K
CA21
3
4 GNDA 1 1 2 2
DVSS DA8
47 49
3
+1.5VS +DVDD PDB Thermal Pad YSLC05CH_SOT23-3
SCA00002900 Q4B
1
ALC3227-CG_MQFN48P_6X6 AVREFCA24 1 2 2.2U_0402_6.3V6M 2 2 1 1 2N7002KDW_SOT363-6
1
MUTE_LED_CTR 5
RA25 1K_0402_5%
<SI> QA2 change from NMOS to BJT 2.2K_0402_5%
4
1
RA26 GNDA
<PV> QA2 change to QA1.
1
2 2
GNDA
2
10K_0402_5%
B
RA12
E
HDA_RST_AUDIO# 3 1 PD#
2
C
C C
Part Number = SB000008E10 QA1
Internal SPK
1
MMBT3904WH_SOT323-3
10K_0402_5% Power down (PD#) power stage for save power <DB>Relace RA13/RA14/RA15/RA16 close to UA1
<30> EC_MUTE#
1 2
RA11
<PV>RA13~RA16 change to SM010008A00, 30-ohm.
DA3 0V: Power down power stage
CH751H-40PT_SOD323-2 JSPK1
3.3V: Power up power stage
2
SPK_R- EMI@ RA13 1 2 PBY160808T-300Y-N_2P SPK_R-_CONN 1

SPK_R+ EMI@ RA14 1 2 2 1
PBY160808T-300Y-N_2P SPK_R+_CONN
SPK_L- EMI@ RA15 1 2 3 2 5
PBY160808T-300Y-N_2P SPK_L-_CONN
SPK_L+ EMI@ RA16 1 2 4 3 GND 6
PBY160808T-300Y-N_2P SPK_L+_CONN
4 GND
E-T_3703-Q04N-11R
wide 40 MIL Delete ESD Diode
220P_0402_50V7K
CONN@
220P_0402_50V7
220P_0402_50V7
220P_0402_50V7
1 1 1 1
@EMII@ C126
@EMII@ C123
@EMII@ C124
@EMII@ C125
SPK_R-_CONN SPK_L-_CONN
2 2 2 2
SPK_R+_CONN SPK_L+_CONN
K
2
3
DA1 @ESD@ DA2 @ESD@
SCA00002900 SCA00002900
L03ESDL5V0CC3-2_SOT23-3 L03ESDL5V0CC3-2_SOT23-3
PC Beep
1
EC Beep <30> EC_BEEP#
CA31
1 2 PC_BEEP_R
Reserve for ESD request.
B
.1U_0402_16V7K RA19
47K_0402_5%
INT_MIC_R GNDA HP_OUTR_R HP_OUTL_R
Jack detect +MIC2_VREFO
B
Combo Mic = High
3
SB Beep 1 2 1 2 1 2 PC_BEEP CA34
<9> HDA_SPKR
1
2
3
CA33 .1U_0402_16V7K DA4
Normal HP = Low
1
.1U_0402_16V7K YSLC05CH_SOT23-3 DA6

SCA00002900 YSLC05CH_SOT23-3 RA17
RA20 SCA00000U10 2.2K_0402_5%
ESD@
10K_0402_5%
2
@ESD@ MIC_JD 1 2 INT_MIC
2
Close to Codec pin12 RA18

22K_0402_5%
M
10U_0603_6.3V6
CA32
1
2
1
1
GNDA
COMBO AUDIO JACK

RA27 1 @ 2 0_0402_5% EMI@
HPR, HPL, 15mil Keep 30mil JHP1
INT_MIC RA21 1 2 BLM15AG601SN1D_2P INT_MIC_R 3
6
RA28 1 @ 2 0_0402_5% EMI@
HP_OUTL RA22 1 2 BLM15AG601SN1D_2P HP_OUTL_R 1
1 2 EMI@ 2
CA40 @EMI@ HP_OUTR RA23 1 2 BLM15AG601SN1D_2P HP_OUTR_R 4
.1U_0402_16V7K
<PV>RA21~23 change to PLUG_IN#
5
1 2 Main : SM01000II00 J
100P_0402_50V8
CA35
J
10P_0402_50V8
CA36
J
10P_0402_50V8
CA37
1 1 1
1
CA38 @EMI@ 2nd : SM01000I000

A .1U_0402_16V7K RA24 @EMII@ SINGA_2SJ-E960-001F A
@EMII@
@EMII@
22K_0402_5%
2 2 2 GNDA CONN@
1 2 Delete ESD Diode
2
CA39 @EMI@ Pin6 and Pin5

.1U_0402_16V7K Normal OPEN
1 2 GNDA GNDA GNDA GNDA
CA29 EMI@
.1U_0402_16V7K
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.

CA30 EMI@ 2013/01/04 2015/01/04 Title
Issued Date Deciphered Date
.1U_0402_16V7K
AUDIO ALC3227-CG
C 0.1
GNDA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-B972P
5 4 3 2 1
<30> KSI[0..7]
KSI7 Keyboard conn
KSI6
KSI5
KSI4
Touch pad conn KSI3
KSI2 CONN@ JKB1
KSI1 KSI1 1
KSI0 1
KSI7 2 2
KSI6 3
3
KSO9 4
KSI4 5 4
5
<30> KSO[0..17] KSI5 6 6
KSO17 KSO0 7 7
KSO16 KSI2 8 8
KSO15 KSI3 9
9
KSO14 KSO5 10 10
ESD@ KSO13 KSO1 11
11
KSI0 C193 2 1 100P_0402_50V8J KSO12 KSI0 12 12
KSO11 KSO2 13
13
KSO10 KSO4 14
KSO9 KSO7 15 14
KSO8 15
KSO8 16 16
KSO7 KSO6 17 17
KSO6 KSO3 18 18
KSO5 KSO12 19
KSO4 19
KSO13 20 20
KSO3 KSO14 21 21
KSO2 KSO11 22 22
KSO1 KSO10 23 23
KSO0 KSO15 24 24
KSO16 25 25
KSO17 26 26
+5VS 27 27
<30> CAP_LOCK# CAP_LOCK# R203 1 2 3.3K_0402_5% 28 28
<25> MUTE_LED MUTE_LED R207 1 2 3.3K_0402_5% 29 29
WL_WHIT 30 30
WL_AMBER 31 31 33
32 32 G1 34
+5VS G2
ACES_50690-0320N-P01
+5VALW +5VALW
+3VALW
JTP1
1 1
1 @EMI@
<30> TP_CLK TP_CLK 2
3 2 5 C134
<30> TP_DATA TP_DATA 3 G1 6
4 470P_0402_50V8J CAP_LOCK#
4 G2 2 MUTE_LED
HB_A090420-SAHR21
CONN@
1 1
1
Amber White
2
CC122 CC123
DM5 R157 R158 2 100P_0402_50V8J 2 100P_0402_50V8J
YSLC05CH_SOT23-3 3.3K_0402_5% 3.3K_0402_5% ESD@ ESD@
SCA00000U10
WL_AMBER WL_WHIT
@ESD@
62
32
2N7002KDW_SOT363-6
2N7002KDW_SOT363-6
Q20A
Q20B
1
2 5
<30> WLAN_OFF_LED# WLAN_ON_LED# <30>
4
KB/TP
B
LA-B972P 0.1
A B C D E
Powert Button Connector

+3VL
1
@EMI@ 1 LID_SW#
White 1
remove at SI phase LED10 +3VALW

C166 0.1U_0402_16V7K 220_0402_5% R2744
1
PWR_LED# 2 1 1 2
2 CC124 <30> PWR_LED#
JPWR1
1 2 100P_0402_50V8J @ESD@ LTW-110DC5-C_WHITE
ESD@ 1
3
LID_SW# 2 1
<30> LID_SW# 2
5
remove at SI phase CS20
0.1U_0402_16V7K
<30> ON/OFF# ON/OFF# 3
4 3 G1 6
4 G2
HB_A090420-SAHR21
+3VL 2
White
CONN@ LED9 +3VS
R215
220_0402_5% R2743
ON/OFF# 2 1 SATA_LED# 2 1 1 2
<6,9> SATA_LED#
100K_0402_5% @ESD@ 1 LTW-110DC5-C_WHITE
3
remove at SI phase CS19 0.1U_0402_16V7K
2
2 2
<SI> Del New Lid SW conn
3 3
+FAN_POWER
40mil FAN conn +3VS

2.2U_0603_6.3V6K
1
+FAN_POWER
1
RE50
CE22 +5VS 10K_0402_5%
CE25
2
2.2U_0603_6.3V6K 40milCONN@ JFAN1
2
1 2 1
1
2
<30> FAN_SPEED1 2
3
3
UE3
1 8 1 4
2 VEN GND 7 5 GND
3 VIN GND 6 CE24 GND
4 VO GND 5 0.01U_0402_16V7K ACES_85204-0300N
<30> EN_DFAN1 VSET GND 2
APE8873M SOP 8P
4 4

Deciphered Date
PWRBTN/FAN
B
LA-B972P 0.1
A B C D E
5 4 3 2 1
+3VS +3VS
ACCELEROMETER + 3V_GSEN
RH411 1 @ 2 + 3V_GSEN
+3VL
TPM1.2 0_0402_5%
@ RH503
0_0402_5%
0.1U_0402_16V4Z
2 1
1@ 1@ 1@
C1060 C1059 C1058 @
D H8
1 SI# 2012.04.10 Change ACCEL_INT# to INT1
0.1U_0402_16V4Z @ 1 2
2 2 2 C1061 * + 3V_GSEN ACCEL_INT# <9>
ACCEL_INT#_R
0.1U_0402_16V4Z @ 0.1U_0402_16V4Z
U70 2 @ CH751H-40PT_SOD 323-2
24
19
5
U25
VD D
VD D
VD D
VSB
1 9 + 3V_GSEN
10
Vdd_IO INT2 11
D LPC_AD0 26 28 EC _SMB_C K1 4 INT1 14 D
<30,7> LPC_AD0 LAD 0 LPCPD# <30,45,46> EC _SMB_C K1 SCL/SPC VD D
LPC_AD1 23 9 BAD D 1 2 PLT_RST# EC _SMB_D A1 6
<30,7> LPC_AD1 LAD 1 TESTB1/BADD <30,45,46> EC _SMB_D A1 SDA/SDI/SDO
LPC_AD2 20 8 7 5
<30,7> LPC_AD2 LAD 2 TEST1 SDO/SA0 GND
LPC_AD3 17 @ R1413 0_0402_5% 2 @ R208 1 8 12
<30,7> LPC_AD3 LAD3 + 3V_GSEN CS GND
14 10K_0402_5% 10
XTALO RES
1
13 13 1 1
TPM XTALI @ R227 2 RES
15 C231
LCLK NC RES
21 SLB 9656 TT 1.2 @ 0_0402_5% 3 16 C232
<7> CLK_PCI_TPM NC RES
LPC _FRAME# 22 2 T48 PAD 0.1U_0402_16V7K 10U_0603_6.3V6M
<30,7> LPC _FRAME# LFRAME# GPIO2 2
PLT_RST# 16 6 2
<21,23,30,32,8> PLT_RST# LRESET# GPIO HP3D C 2TR
SERIRQ 27 T47 PAD
<30,9> SERIRQ SERIRQ @
15 @ @
CLKRUN#
7 1
+3VS 1 @ 2 PP NC
R1383 3
NC 12 @R209
4.7K_0402_5%
NC
0_0402_5%
GND
GND
GND
GND
212
@ SLB 9656 TT 1.2
4
11
18
25
R1414
0_0402_5%
2 1
Screw Hole
H3 H4 H5 H6 H7
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
HOLEA HOLEA HOLEA HOLEA HOLEA
C @ @ @ @ @ C
1
H9 H10 H11 H13 H15 H16

H_5P0 H_5P0 H_5P0 H_5P0 H_5P0 H_5P0
H14 H1 H2 H12 H17 H18 H19 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA FD3 FD4 FD2 FD1
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P0 H_2P0X2P5
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA @ @ @ @ @ @ @ @ @ @
1
1
1
FIDUCIAL_C 40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ @ @ @ @ @ @
Compal Electronics, Inc.
1

LED/Screwhole
THIS SHEET OF ENGINEERI NG DRAW ING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAI NS CONFIDEN TI
AL
AND TRAD E SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPETEN T DIVISION OF R&D
DEPARTMEN T EXC EPT AS AUTHORI ZED BY COMPAL ELECTRONIC S, INC. NEITHER THIS SHEET NOR THE INFORMATION IT C ONTAI NS LA-B972P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W I THOUT PRIOR W RI TTEN CONSENT OF COMPAL ELECTRONIC S, INC.
B B
A A
5 4 3 2 1
5 4 3 2 1
Use 0 ohm for material shortage Use 0 ohm for material shortage
If Vp-p small than 50mV +IVDDO_1.8V +RXIVDD_1.8V +IVDDO_1.8V +DAC_1.8V
+3VS +3VS_OVDD change L4106 to 0 ohm L4107 L4108
BLM15PD600SN1D_2P BLM15PD600SN1D_2P
+RXVCC_1.8V 1 2 1 2
R4110 2 1 0_0603_5% +IVDDO_1.8V L4106 CRT@ CRT@
Rated current 500mA, DC 0.1ohm Rated current 500mA, DC 0.1ohm
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
BLM15PD600SN1D_2P
C4106 CRT@
C4109 CRT@
C4136 CRT@
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
C4107 CRT@
short@ 1 1 1 1 1
1U_0402_6.3V6K
1 1 1 CRT@ Note: Depend on Note: Depend on
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Project, if Vp-p small Project, if Vp-p small
C4105
CRT@ C4108
CRT@ C4101
CRT@ C4110
1U_0402_6.3V6K
the 50mV change to 0 the 50mV change to 0
CRT@ C4115
1 1 1 1 1 2 2 2 2 2
CRT@ C4111
CRT@ C4103
CRT@ C4104
CRT@ C4112
2 2 2 ohm @ ohm
2 2 2 2 2
Note: Place close pin 24

Note: Place close pin 10
D D
+3VS_IVDD33 Note: Place close pin 38,39
LDO input Note: Place close pin 22,15,31,32
R4109 2 1 0_0603_5%
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C4113 CRT@
C4114 CRT@
C4125 CRT@
short@ 1
CRT@ C4100
1 1 1
ISPSCL_R
ISPSDA_R
2 +3VS_IVDD33
2 2 2 DT4 @ESD@
1
1
CRT@ CRT@ SC300001G00
CRT_HSYNC_2 6 3 CRT_VSYNC_2
22_0402_5%
R4100
R4101
22_0402_5%
+3VS_OVDD +RXIVDD_1.8V I/O4 I/O2
+HDMI_5V_OUT
+3VS R4102
2
2
4.7K_0402_5% +IVDDO_1.8V Note: Place close pin 12,14,44,46 5 2
1 @ 2 VDD GND
1 @ 2
R4103 Pin38,39 LDO output +IVDDO_1.8V.
4.7K_0402_5% CRT_DATA 4 1 CRT_CLK
I/O3 I/O1
UT5
12
14
44
46
38
39
35
36
13
48
AZC099-04S.R7G_SOT23-6
DDCSCL 2
1.52mA +HDMI_5V_OUT
IVDD33
IVDD33
IVDD
IVDD
IVDD
IVDD
IVDDO
IVDDO
DDCSDA
OVDD
OVDD
VGA_HPD 40
HPD C4116 @ DT3 @ESD@
4.2mA 100.5mA 45 1 2 0.1U_0402_16V4Z SC300001G00
CRT@ C4123 2 1 0.1U_0402_16V7K PCH_DPC_C_P0 26 MCUVDDH +HDMI_5V_OUT 6 3
CRT_R_2 CRT_G_2
<4> PCH_DPC_P0
CRT@ C4119 2 1 0.1U_0402_16V7K PCH_DPC_C_N0 27 RX0P I/O4 I/O2
<4> PCH_DPC_N0 RX0N +HDMI_5V_OUT
<4> PCH_DPC_P1 CRT@ C4120 2 1 0.1U_0402_16V7K PCH_DPC_C_P1 29 47 MCURSTN
RX1P MCURSTN @ T4102
1
CRT@ C4124 2 1 0.1U_0402_16V7K PCH_DPC_C_N1 30 5 2
2.2K_0402_5%
2.2K_0402_5%
<4> PCH_DPC_N1 RX1N VDD GND
R4124
CRT@
R4125
CRT@
CPU DDI1 URDBG
28 @ T4101
+3VS R4108 2 CRT@ 1 1M_0402_5%
RP4102
(2-Lane only) R4104 2 @ 1 100K_0402_5% C4121 CRT@ 15 ISPSCL_R CRT@ 4 1 CRT_B_2
2
0.1U_0402_16V7K ISPSCL ISPSDA_R 1 8 I/O3 I/O1
16
2 1 DDI1_AUX_C_DP 20 ISPSDA 2 7
<8> DDI1_AUX_DP RXAUXP AZC099-04S.R7G_SOT23-6
2 1 DDI1_AUX_C_DN 19 23 3 6 CRT_CLK CRT_CLK
<8> DDI1_AUX_DN RXAUXN VGADDCCLK
C4122 CRT@ 21 4 5 CRT_DATA CRT_DATA
0.1U_0402_16V7K VGADDCSDA
+3VS R4113 2 @ 1 100K_0402_5% DDI1_AUX_DP 18 3 VSYNC
R4114 2 1 1M_0402_5% CRT@ DDI1_AUX_DN DCAUXP VSYNC HSYNC 22_0804_8P4R_5%
17 4
DCAUXN HSYNC Note: ISPSCL/ISPSDA for F/W update
+RXIVDD_1.8V +RXVCC_1.8V RGB Trace must less than 2000mils.

+DAC_1.8V
C C
CRB1.0 use 33ohm@100Mhz Bead
25
31 AVCC
56.95mA 65.5mA
VDDC
10 CRT Connector
AVCC
R_out & B_out can be swapped.
22
PVCC 41.6mA
IT6513FN L4103
PBY160808T-600Y-N @
T4103 6
11
JCRT1
11 CRT_R CRT_R 1 2 CRTEMI@ CRT_R_2 1

IORP L4104 7
PBY160808T-600Y-N CRT_DATA 12
9 CRT_G CRT_G 1 2 CRTEMI@ CRT_G_2 2
+HDMI_5V_OUT IOGP L4105 8
DVDD18 47.3mA
24 PBY160808T-600Y-N CRT_HSYNC_2 13
8 CRT_B CRT_B 1 2 CRTEMI@ CRT_B_2 3
IOBP +HDMI_5V_OUT 9
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
1 1 1 1 1 1 +HDMI_5V_OUT
41 VGADETECT CRT_VSYNC_2 14
NC/VGADETECT @ T4104
1
8
7
6
5
CRT@ CRT@ CRT@ SM010005N00 4
C4126
C4127
C4128
C4129
C4130
C4131
5 1
W=40mils 10
R4123 R4126 RP4100 G 16
CRTEMI@
CRTEMI@
CRTEMI@
CRTEMI@
CRTEMI@
CRTEMI@
2 1
RSET 2 2 2 2 2 2
ASPVCC 6.158mA G 17
4.7K_0402_5% 4.7K_0402_5% 32 R4118 CRT@ 100_0402_1% CRT_CLK 15
75_0804_8P4R_1%
5
C4132
0.1U_0402_16V4Z
0.293mA VDDA 7 @
2
1
2
3
4
+DAC_1.8V 2 C-H_13-12201560CP
CRT@ CONN@
PCSDA 6 1 2 C4133 DC060006E00
COMP
0.1U_0402_16V4Z
PCSDA 43 0.1U_0402_16V4Z
C4137 CRT@
PCSCL PCSCL 42 PCSDA
PCSCL 1
Note: need external PU to 2K ~ 10K 34 XTALIN_6513 Pin41_VG AD ET ECT is not use in IT6513. <MV> EMI fine tune Pi-filiter to 60-ohm and 6.8pf .
XTALIN 33 XTALOUT_6513
XTALOUT
2
PW DNB
PAD
IT6513FN_QFN48_6X6
49
37
+HDMI_5V_OUT CRT@
CRT@
R4120 1 2 0_0402_5%
1 2 +HDMI_5V_OUT
+5VS R4121 10K_0402_5% CRT@
CRT@ RT26 1 CRT@ 2 CRT_HSYNC_2
<PV>Add R4121 by vender recommand. 1 2 CRT@ 2 1 LT14 33_0402_5%
CT27 0.1U_0402_16V4Z
2
10K_0402_5% 1 CRT@ 2 CRT_VSYNC_2

G
1
UT2 CRT@ LT15 33_0402_5% 1 1
B <8> DDI1_HPD 3 1 VGA_HPD 74AHCT1G125GW_SOT353-5 B
OE#
HSYNC 2 4 CRT_HSYNC_1 @ @
S
A Y
1
5
CT26 CT28
G P
Q4100 R4122 10P_0402_50V8J 2 2 10P_0402_50V8J
L2N7002LT1G_SOT23-3 4.7K_0402_5%
3
@ CRT@
+HDMI_5V_OUT
2
CT25 1 2 0.1U_0402_16V4Z
CRT@
5
1
OE#
VSYNC 2 4 CRT_VSYNC_1
A Y
G P
R4127
1M_0402_5% UT4 CRT@
XTALOUT_6513 @ XTALIN_6513 74AHCT1G125GW_SOT353-5
3
X4100 @
27MHZ_10PF_X3G027000BA1H-U
Crystal
3 4
OUT GND
2 1
GND IN
1
18P_0402_50V8J
1
18P_0402_50V8J
@
C4134 @
2 C4135
2
A A

Deciphered Date
THI S SHEET OF ENGI NEE R I N G D RAW I NG IS THE PROPRI E TA R Y PROPE R TY OF C OMPAL ELEC TRONI C S, I NC . AND C ONTAI NS C ONFI D ENTI AL
eDP to CRT
AND TRAD E SEC RET I NFORMATI ON. THI S SHEET MAY NOT BE TRANS FE R ED FROM THE C USTOD Y OF THE C OMPETENT DIVISION OF R&D
Custom 0.1
D EPARTMENT EXC EPT AS AUTH O RI ZED BY C OMPAL ELEC TRONI C S, I NC . NEI THER THI S SHEET NOR THE I NFORMA TI O N IT C ONTAI NS
MAY BE USED BY O R D I SC LOSED TO ANY THI RD PARTY W I THOUT PRI OR W RI TTEN C ONSENT OF C OMPAL ELEC TRONI C S, I NC .
LA-B972P
5 4 3 2 1
5 4 3 2 1
+3VL +3VALW _EC 15" 14"

LK1 +3VALW _EC
DB SI PV MV DB SI PV MV
short@ RK57 FBMA-L11-160808-800LMT_0603 UMA UMA
1 2 1 2 +EC_VCCA
0.1U_0402_16V7K
0.1U_0402_16V7K
+3VALW _EC 0 ohm
12k ohm 20K ohm 33K ohm 56K ohm 15K ohm 27K ohm 43K ohm
2
RK13 RK13
CK2
CK3
1 1 1
0_0603_5% RK6
CK7
DIS 160k ohm 240k ohm 330k ohm 560k ohm DIS
100K_0402_5%
RK13 130k ohm 200k ohm 270k ohm 430k ohm
RK13
ECAGND
2 2 2 0.1U_0402_16V7K
PV# 2013.01.29 Add CK4 for ESD protection
1
BOARD_ID
Board ID control
+3V_EC_VDD
<DB>RK13 change to 160K ==>for 15" DIS
2
ESD@ CK4 RK12 short@
2 1 DIS@
D
2 1 PLT_RST#
+3VL
RK13
<DB>RK13 change to 12K ===>for 15" UMA D
0_0402_5% 560K_0402_1% UMA@

SD034560380 RK13
0.1U_0402_16V7K
1
111
125
56K_0402_1% CH751H-40PT_SOD323-2
22
33
96
67
9
UK1 SD034560280 EC_ACIN 2 1
ACIN <44,45,46,8>
DK1
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
CK8 2 1 100P_0402_50V8J
1 330K_0402_5% EC_RST#
+3VALW _EC RK15 2
<35,53,9> DGPU_PW R_EN 1 21 GPU_HOT # <53>
2 EC_KBRST# GAT EA20/GPIO 00 GPIO0F
1 <7,9> EC_KBRST# 2 23 EC_BEEP# <25>
0.1U_0402_16V7K SERIRQ KBRST #/GPIO 01 BEEP#/G PIO 10 short@ RK17
CK9 <28,9> SERIRQ 3 26 TS_GPIO_EC <19>
LPC_FRAME# SERIRQ GPIO12 0_0402_5%
4 27 AC_AND_CHAG <45>
<28,7> LPC_FRAME# LPC_AD3 LPC_FRAME# ACOFF/GPIO13 VR_HOT # 1 2
5 <50> VR_HOT # PROCHOT# <4,44>
<28,7> LPC_AD3 LPC_AD3
LPC_AD2 7 PWMOutput
<28,7> LPC_AD2 LPC_AD2
LPC_AD1 8 63 B/I#
<28,7> LPC_AD1 LPC_AD1 BAT T _T EMP/AD0/GPIO 38 B/I# <44,45>
LPC_AD0 BOARD_ID
LPC_ADLL0 PC & MISC
<28,7> LPC_AD0 10 64
AD1/GPIO39 ADP_I
65
ADP_I/AD 2/G PIO 3A ADP_I <44,46> D
1
CLK_PCI_LPC 12 AD Input 66
<7> CLK_PCI_LPC
PLT_RST# 13 CLK_PCI_EC AD3/GPIO3B
75 ADP_ID H_PROCHOT#_EC 2
<21,23,28,32,8> PLT_RST# ADP_ID <44> <44> H_PROCHOT#_EC
EC_RST# 37 PCIRST #/GPIO05 AD4/GPIO42
76 ENBKL G
EC_SCI# 20 EC_RST # IMON/AD5/G PIO 43 ENBKL <8> QK1 S
<9> EC_SCI#
3
1 @ 2 PM_CLKRUN#_R EC_SCII#/GPIO0E 2N7002_SOT23-3
<8> PM_CLKRUN# 38
RK59 1 2 0_0402_5% GPIO1D
<21> EC_PCIE_W AKE# short@ RK53 1 2 0_0201_5% <PWR>
+1.05V_VS_PG_PW R <49>
RK61 short@ 0_0402_5% 68 +1.05V_VS_PG_PW R
+3VALW _EC DAC_BRIG/GPIO3C 70
<26> KSI[0..7] DA Output EN_DFAN1/GPIO 3D 71 EN_DFAN1 <27>
KSI0 55
KSI1 56 KSI0/GPIO30 IREF/GPIO3E 72 DGPU_HOLD_RST# <32,9>
+3VS 57 KSI1/GPIO31 CHGVADJ/GPIO3F SYS_PW ROK <8>
KSI2
KSI3 58 KSI2/GPIO32 83
KSI3/GPIO33 EC_MUT E#/GPIO4A EC_MUT E# <25> +3VALW _EC
RP7 1 8 EC_SMB_CK1 KSI4 59 84 PM_SLP_S4#
C KSI4/GPIO34 USB_EN#/GPIO4B PM_SLP_S4# <8> C
2 7 EC_SMB_DA1 KSI5 60 85 W LAN_OFF_LED#
EC_SMB_CK2 KSI6 61 KSI5/GPIO35 CAP_INT #/GPIO4C 86 W LAN_OFF_LED# <26>
3 6 PS2 Interface
4 5 EC_SMB_DA2 KSI7 62 KSI6/GPIO36 EAPD/GPIO 4D 87 TP_CLK
<26> KSO[0..17] 39 KSI7/GPIO37 T P_CLK/GPIO4E 88 TP_CLK <26>
KSO0 TP_DATA
KSO0/GPIO 20 T P_DAT A/GPIO4F TP_DATA <26>
KSO1 40
2.2K_0804_8P4R_5% KSO2 41 KSO1/GPIO 21
KSO3 42 KSO2/GPIO 22 97 EC_PME# EC_FB_CLAMP_TGL_REQ# RK60 1 @DIS@ 2 10K_0402_5%
KSO3/GPIO 23 CPU1.5V_S3_GAT E/GPXIOA00 98 EC_PME# <23,9>
KSO4 43
KSO5 44 KSO4/GPIO 24
Int. K/B W OL_EN/GPXIOA01 99 HDA_SDO W L_PW REN_EC <21> <PV>N15V don,t support GC6,RK60 change to @DIS@.
45 KSO5/GPIO 25 ME_EN/GPXIO A02 109 HDA_SDO <6>
KSO6 VCIN0_PH
KSO7 46 KSO6/GPIO 26 Matrix V C IN 0_PH/GPXIOD00 VCIN0_PH <44>
KSO7/GPIO 27 SPI Device Inte r fa ce
KSO8 47
KSO9 48 KSO8/GPIO 28 119 <SI> Update Pin119 and Pin120 net name
49 KSO9/GPIO 29 SPIDI/GPIO5B 120 EC_SPI_SO <7>
KSO10 +3VALW
KSO10/GPIO 2A EC_SPI_SI <7>
KSO11 50
KSO11/GPIO 2B
SPI Flash ROM SPIDO/GPIO5C 126
SPICLK/G PIO 58 EC_SPI_CLK <7>
KSO12 51 128 TP_CLK RK2 1 2 4.7K_0402_5%
KSO12/GPIO 2C SPICS#/G PIO 5A EC_SPI_CS0# <7>
KSO13 52
KSO14 53 KSO13/GPIO 2D TP_DATA RK4 1 2 4.7K_0402_5%
KSO15 54 KSO14/GPIO 2E 73 T OUCH_ON#
KSO15/GPIO2F ENBKL/AD6/G PIO 40 T OUCH_ON# <19>
KSO16 81 74 EC_FB_CLAMP_TGL_REQ#
KSO16/GPIO48 PECI_KB930/ AD 7/G PIO 41 EC_FB_CLAMP_TGL_REQ# <9>
@ KSO17 82 89 AOAC_PME#
KSO17/GPIO 49 FST CHG/GPIO50 90 AOAC_PME# <8>
+3VS RK36 1 2 10K_0402_5% EC_SCI#
BAT T _CHG_LED#/GPIO52 BAT _CHG_LED <44>
91 CAP_LOCK#
CAPS_LED#/GPIO53 92 CAP_LOCK# <26>
EC_SMB_CK1 77 GPIO PW R_LED#
<28,45,46> EC_SMB_CK1 EC_SMB_C K1/G PIO44 PW R_LED#/GPIO54 93 PW R_LED# <27>
EC_SMB_DA1 78
<28,45,46> EC_SMB_DA1 EC_SMB_D A1/G PIO45 BAT T _LOW _LED#/GPIO55 W LAN_ON_LED# <26>
EC_SMB_CK2 RK39 1 short@ 2 0_0402_5% EC_SMB_CK2_R 95 SYSON
EC_SMB_CK2/GPIOSS46M Bus
<18,32,7> EC_SMB_CK2 79 SYSON <40,48>
EC_SMB_DA2 RK40 1 2 0_0402_5% EC_SMB_DA2_R SYSON/GPIO 56 121 BT _ON_EC +3VL
<18,32,7> EC_SMB_DA2 80 BT _ON_EC <21>
short@ EC_SMB_D A2/G PIO47 VR_ON/GPIO57 127 PCH_DPW ROK
PM_SLP_S4#/G PIO 59 PCH_DPW ROK <8>
RP8
PCH_RSMRST # <8>
PM_SLP_S3# 6 100 PCH_RSMRST # CK10 2 1 100P_0402_50V8J ECAGND PCH_PW R_EN 8 1
<8> PM_SLP_S3# PM_SLP_S3#/G PIO04 EC_RSMRST #/GPXIO A03
PM_SLP_S5# 14 101 PLT_RST# 7 2
<8> PM_SLP_S5# PM_SLP_S5#/G PIO07 EC_LID_OUT #/GPXIO A04 EC_LID_OUT# <9>
B SUSACK# 15 102 VCIN1_PH EC_ON 6 3 B
<8> SUSACK# EC_SMI#/G PIO08 PROCHOT _IN/GPXIO A05 VCIN1_PH <44>
16 103 H_PROCHOT#_EC EC_ACIN 5 4
<21> MINI1_LED# 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 MAINPW ON
PCH_SUSW ARN#
<8> PCH_SUSW ARN# GPIO0B MAINPW ON <47>
18
GPIO0C
GPO VCOUT0_PH/GPXIOA07
BKOFF#/GPXIO A08
105 EC_BKOFF#
EC_BKOFF# <18> 100K_0804_8P4R_5%
19 GPIO 106 PBT N_OUT #
<6> EC_+1.05VS_PG GPIO0D PBT N_OUT #/GPXIOA09 PBT N_OUT # <8>
25 107 PCH_PW R_EN
<19> EC_INVT _PW M 28 EC_INVT _PW M/GPIO 11 PCH_APW ROK/GPXIO A10 108 PCH_PW R_EN <42>
FAN_SPEED1 USB_ON#
<27> FAN_SPEED1 FAN_SPEED1/G PIO 14 SA_PGOOD/GPXIO A11 USB_ON# <24>
PM_SLP_SUS# 29
<8> PM_SLP_SUS# E51TXD_P80DATA 30 EC_PME#/G PIO 15
<21> E51TXD_P80DATA E51RXD_P80CLK 31 EC_T X/GPIO16 110 EC_ACIN
<21> E51RXD_P80CLK PCH_PW ROK 32 EC_RX/GPIO 17 AC_IN/GPXIOD 01 112 EC_ON
<8> PCH_PW ROK 34 PCH_PW ROK/GPIO18 EC_ON/GPXIOD 02 114 EC_ON <47>
AC_LED# ON/OFF#
<44> AC_LED# 36 SUSP_LED#/GPIO 19 ON/OFF/GPXIOD03 115 LID_SW # ON/OFF# <27>
NUM_LED#/GPIO1A GPI LID_SW #/GPXIOD04 116 LID_SW # <27>
SUSP#
SUSP#/GPXIOD 05 117 NMI_DBG# SUSP# <40,48,49,52,55>
GPXIOD06 118 EC_PECI RK34 1 2
PECI_KB9012/G PXIOD 07 H_PECI <4>
GPU_T HERMAL_DET # 122 43_0402_1%
<32> GPU_T HERMAL_DET #
AGND/AGND
123 XCLKI/GPIO 5D 124 +V18R +3VALW _EC

GND/GND
GND/GND
GND/GND
GND/GND
XCLKO/GPIO 5E V18R
1
GND0
CK17
LID_SW # RK44 2 1 47K_0402_5%
4.7U_0603_6.3V6K
KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
69
113
Part Number = SA00004OB30

20mil
LK2
ECAGND 2 1
FBMA-L11-160808-800LMT_0603
@ RK49 100K_0402_5% +3VALW _EC

1 2 PCH_DPW ROK
ECAGND <44>
@ RK50 100K_0402_5%
1
A A
1 2 PCH_PW ROK
RK18
10K_0402_5%
2
NMI_DBG# 1 2
DK2
NMI_DBG#_CPU <9> Security Classification Compal Secret Data Compal Electronics, Inc.
CH751H-40PT_SOD323-2
THIS SHEET OF ENGINEERING DRAW ING IS T HE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number
EC ENE-KB9012
Rev
AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM T HE CUSTODY OF T HE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY THIRD PART Y W IT HOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B972P
5 4 3 2 1
5 4 3 2 1
BOM control
Platform Silego P/N Compal PN 25MHz(A) 32.768KHz 24MHz(B) 27MHz 8MHz Remark
D
Intel ULT UMA SLG3NB3375V SA00006RE00 1 1 1 X X GCLKUMA@ D
Intel ULT Dis SLG3NB3374V SA00006RD00 1 1 1 1 X GCLKDIS@
Base on A32 32.768KHz use 10ppm, G‐CLK 25MHz X'TAL use10ppm.
+RTCBATT
+RTCVCC
1
RG106 GCLK@
1
330_0402_5%
+3VGS +1.05VS +LAN_VDD_3V3 +3VL +3VALW RG107 @
0_0402_5%
2
GCLKDIS@ 1 1 GCLK@ 1 GCLK@ 1 GCLK@ 1 GCLK@
2
Depop if GCLK
CG47 CG48 CG49 CG50 CG51
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
with UMA 0.1U_0402_10V7K
2.2U_0603_6.3V6
C 1 C
CG52 1
2 2 2 2 2 22U_0805_6.3V6M
GCLK@
K CG53
GCLK@ 2 GCLKDIS@
UG2 2
GCLK_VRTC 10 14 RTC_VOUT
VBAT VDD_RTC_OUT
Place close +3VL 15 +V3.3A CPU 32.768M(P.6)
to UG2.8 Place RG114 close to YC1
+3VALW 2 VDD @ <SI> Change RG109 to 33 ohm recommend by vender
9 PCH_RTCX1_R 1 2
PCH_RTCX1 <6>
VGA 27M(P.32)
32kHz RG114 0_0402_5% Place RG110 close to YV1 <CPU RTC>
GCLKDIS@ GCLKDIS@
11 12 VGA_X1_R RG109 1 2 33_0402_5% XTALIN_R 1 2
+3VGS VDDIO_27M 27MHz
RG110 0_0402_5%
XTALIN <32> <GPU>
Check Power Rail 8 6 LAN_X1_R RG1111 2 33_0402_5% XTLI_R 1 2
+LAN_VDD_3V3 VDDIO_25M_A 25MHz_A
GCLK@ RG112 GCLK@ 0_0402_5%
XTLO <23> <LAN>
3 5 PCH_X1_R RG1131 2 0_0402_5%
+1.05VS VDDIO_25M_B 25MHz_B
GCLK@
CPU_XTAL24_IN <7>
LAN 25M(P.23)
<CPU>
CLK_X1 1 XTAL_IN CPU_CLK 24M(P.7) Place RG112 close to YL1
CLK_X2 16 CG54 Place RG113 close to YC2
2 1
XTAL_OUT
GND4
5P_0402_50V8C
GND
GND
GND
GCLK@
3
S CRYSTAL 25MHZ 12PF +-10PPM FL2500048
SJ10000G600 S IC SLG3NB3374VTR TQFN 16P CRYSTAL RG3, RG7,RG8, RG6 0ohm_0402
4
7
13
17
SA00006RD00 for isolated CLK tail
YG1 GCLK@
4 3 CLK_X2
GND OUT
2 2
GCLK@ 1 2 GCLK@
IN GND
CG59 CG58 VGA_X1_R
UG2 GCLKUMA@
1 18P_0402_50V8J 1 18P_0402_50V8J
SA00006RE00
CLK_X1 S IC SLG3NB3375VTR TQFN 16P CRYSTAL CG57
2 1
B 5P_0402_50V8C B
<SI> Change CG58, CG59 to 18pf recommend by vender @
Reserve CG57 for vendor

Place close to RG109
A A

Deciphered Date
TH IS S H E E T O F E N G IN E E RIN G D R AW IN G IS TH E P R O P R IE TA RY P R O P E R TY O F C O M P A L E L E CTR O N IC S, INC. A N D C O N TA IN S CONFIDENTI A L
GCLK
A N D TR A D E S E C R E T IN F O R M A TIO N . TH IS S H E E T M A Y N O T B E TR A N S F E R E D F R O M TH E C U S TO D Y O F TH E C O M P E TE N T DIVISION O F R & D
0.1
D E P A RTM E NT E X C E P T A S A U TH O R IZ E D B Y C O M P A L E L E C TR O N IC S, INC. NEITHER TH IS S H E E T N O R TH E IN F O R M A TIO N IT CONTAINS
M A Y B E U S E D B Y O R DISCLOSED TO A N Y TH IR D P A R TY W ITH O U T P R IO R W R ITTE N C O N S E N T O F C O M P A L E L E C TR O N IC S, INC.
LA-B972P
5 4 3 2 1
1 2 3 4 5
+3VGS
#9/2 , Add RV191 between.

2 100K_0402_5%
GPU_PWR_LEVEL# and GPU_THERMAL_DET#
UV1A GPU_PW R_LEVEL# RV62 1 DIS@
Part 1 of 5
PEG_HTX_C_GRX_P7 AG6 GPU_GPIO6 RV43 1 DIS@ 2 10K_0402_5%
<10> PEG_HTX_C_GRX_P7 PEX_RX0
PEG_HTX_C_GRX_N7 AG7 C6 GPU_GPIO0
<10> PEG_HTX_C_GRX_N7 PEX_RX0_N GPIO0 NVVDD_PSI RV44 1 DIS@ 2 10K_0402_5%
PEG_HTX_C_GRX_P8 AF7 B2
<10> PEG_HTX_C_GRX_P8 PEX_RX1 GPIO1
PEG_HTX_C_GRX_N8 AE7 D6
<CPU> <10>
<10>
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P9 AE9
PEX_RX1_N GPIO2 C7 GPU_GPIO8 RV46 1 DIS@ 2 10K_0402_5%
PEG_HTX_C_GRX_N9 PEX_RX2 GPIO3 F9
<10> PEG_HTX_C_GRX_N9 AF9
PEG_HTX_C_GRX_P10 PEX_RX2_N GPIO4 A3 2 10K_0402_5%
<10> PEG_HTX_C_GRX_P10 AG9 GPU_GPIO9 RV48 1 DIS@
PEG_HTX_C_GRX_N10 PEX_RX3 GPIO5 A4 GPU_GPIO6
A <10> PEG_HTX_C_GRX_N10 AG10 A
PEX_RX3_N GPIO6 B6
AF10
PEX_RX4 GPIO7
GPIO
AE10 A6 GPU_GPIO8
PEX_RX4_N GPIO8 F8 GPU_GPIO9
AE12
PEX_RX5 GPIO9 C5
AF12
PEX_RX5_N GPIO10 E7 NVVDD_PWM_VID
AG12 NVVDD_PWM_VID <53>
PEX_RX6
AG13
AF13
PEX_RX6_N
GPIO11
GPIO12
D7
B4
GPU_PW R_LEVEL# RV191 1 DIS@ 2 0_0402_5%
NVVDD_PSI
GPU_THERMAL_DET# <30> CHECK!! GPU_GPIO0 RV49 1 DIS@ 2 10K_0402_5%
PEX_RX7 GPIO13 NVVDD_PSI <53>
AE13 B3
AE15 PEX_RX7_N GPIO14 C3
NC GPIO15
AF15 D5
NC GPIO16
AG15 D4
NC GPIO17
AG16 C2
NC GPIO18
AF16 F7
NC GPIO19
AE16 E6
NC GPIO20
AE18 C4
NC GPIO21
AF18
NC
AG18
NC
AG19
NC
AF19
AE19
NC
NC
DACA_HSYNC
DACA_VSYNC
AE3
AE4 #8/19 ,N15V-GM didn't support GC6,
AE21
AF21
NC
AG3 unpop QV13 ,QV14.
DACA
NC DACA_RED
AG21 AF3
NC DACA_BLUE
AG22 AF4
NC DACA_GREEN
PEG_GTX_C_HRX_P7 CV1 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P7 AC9 AE2
<10> PEG_GTX_C_HRX_P7 PEX_TX0
PCI EXPRESS
PEG_GTX_C_HRX_N7 CV2 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N7 AB9 DACA_VREF AF2
<10> PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_P8 CV3 DIS@ 1 PEX_TX0_N DACA_RSET
<10> PEG_GTX_C_HRX_P8 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P8 AB10
PEG_GTX_C_HRX_N8 CV4 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N8 AC10 PEX_TX1
<CPU> <10>
<10>
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P9 CV5 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P9 AD11 PEX_TX1_N
PEG_GTX_C_HRX_N9 CV6 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N9 AC11 PEX_TX2 AE5 GPU_JTAG_TCK
<10> PEG_GTX_C_HRX_N9 PEX_TX2_N JTAG_TCK
PEG_GTX_C_HRX_P10 CV7 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_P10 AC12 AE6
<10> PEG_GTX_C_HRX_P10 PEX_TX3 JTAG_TDI T1402
PEG_GTX_C_HRX_N10 CV8 DIS@ 1 2 0.22U_0402_6.3V6K PEG_GTX_HRX_N10 AB12 AF6
<10> PEG_GTX_C_HRX_N10 T1403
TEST
PEX_TX3_N JTAG_TDO AD6
AB13 T1404
B PEX_TX4 JTAG_TMS AG4 GPU_JTAG_TRST B
AC13
PEX_TX4_N JTAG_TRST_N
AD14
PEX_TX5 AD9 TESTMODE
AC14
PEX_TX5_N T EST MODE
AC15
PEX_TX6
AB15
PEX_TX6_N
AB16
PEX_TX7 B7 I2CA_SCL RV14 1 DIS@ 2 2.2K_0402_5%
AC16
AD17 PEX_TX7_N I2CA_SCL A7 I2CA_SDA RV15 1 DIS@ 2 2.2K_0402_5%
#08/22,unused I2C change to pull‐down.
NC I2CA_SDA
AC17
NC +3VGS
AC18 C9 I2CB_SCL DIS@ RV16
NC I2CB_SCL I2CB_SDA 1 8
AB18 C8 I2CB_SDA
NC I2CB_SDA I2CB_SCL 2 7
AB19
NC
I2C
AC19 A9 I2CC_SCL I2CC_SDA 3 6
NC I2CC_SCL +3VGS I2CC_SCL 4 5
AD20 B9 I2CC_SDA DIS@ RV36
NC I2CC_SDA
AC20 GPU_JTAG_TCK 1 8
NC
AC21 D9 I2CS_SCL RV21 1 DIS@ 2 2.2K_0402_5% TESTMODE 2 7 2.2K_0804_8P4R_5%
NC I2CS_SCL
AB21 D8 I2CS_SDA RV22 1 DIS@ 2 2.2K_0402_5% GPU_JTAG_TRST 3 6 #08/22,unused I2C change to pull‐down.
NC I2CS_SDA
AD23 GPU_CLKREQ#_R 4 5
NC
AE23
NC Internal Thermal Sensor
AF24
NC
AE24 A10 XTALSSIN RV23 1 DIS@ 2 10K_0402_5% 10K_0804_8P4R_5%
NC XTAL_SSIN
AG24
NC
AG25 XTAL_OUTBUFF C10 XTALOUT RV25 1 DIS@ 2 10K_0402_5%
NC
CLK
AE8 XTAL_OUT B10 XTAL_OUT
<7> CLK_PCIE_GPU PEX_REFCLK
AD8
<CPU> <7> CLK_PCIE_GPU# PEX_REFCLK_N
XTAL_IN C11 XTALIN
1 DIS@ 2 PEX_TSTCLK_OUT AF22
AE22 PEX_TSTCLK_OUT
Differential signal RV26 200_0402_1% PEX_TSTCLK_OUT#
PEX_TSTCLK_OUT_N +3VGS
1 2 PEX_TERMP AF25 AB6
PEX_T ERMP NC
RV27 DIS@ 2.49K_0402_1%
PLT_RST_VGA# AC7 D10 RV58 1 DIS@ 2 10K_0402_5%
PEX_RST_N NC
C GPU_CLKREQ#_R AC6 E9 C
PEX_CLKREQ_N NC
5
N15V-GM
DIS@ QV2B DIS@
I2CS_SCL 4 3
EC_SMB_CK2 <18,30,7>
2N7002KDWH_SOT363-6
+3VGS
10K_0402_5% RV13 1 @ 2 0_0402_5%
+3VGS +3VGS RV182
DIS@
1 2
2
CV12
0.01U_0402_16V7K
1 QV2A DIS@
SI 11/05 change RV182.1 I2CS_SDA 1 6
EC_SMB_DA2 <18,30,7>
1
RV183 1 2 change to +3VGS from GPU_PWR_EN

@ 0_0402_5% RV184 2N7002KDWH_SOT363-6
DIS@
10K_0402_5% 2
@ RV20 1 @ 2 0_0402_5%
5
2
UV11
PU AT EC SIDE, +3VS AND 4.7K
2
PLT_RST# 1
G
P
<21,23,28,30,8> PLT_RST# B
4 PLT_RST_VGA#
Y 1 3 GPU_CLKREQ#_R
DGPU_HOLD_RST# 2
<30,9> DGPU_HOLD_RST# A <7,8> GPU_CLKREQ#
G
S
1
TC7SH08FUF_SSOP5 1
3
1
DIS@ RV186 @ CV17 QV10 DIS@ XTALIN XTALDIS@
EC or CPU control 10K_0402_5% 2N7002K_SOT23-3 RV187
XTALIN <31>
RV24 1 2 10M_0402_5%
DIS@ 0.1U_0402_16V7K 10K_0402_5%
2 1@ 2 @ XTALDIS@
2
YV1
2
RV188 0_0402_5%
XTALIN 1 3 XTAL_OUT
1 3
GND GND
10P_0402_50V8J
10P_0402_50V8J
1 1
CV9 CV10
D 2 4 D
XTALDIS@ XTALDIS@
2 27MHZ 10PF 5YEA27000102IF50Q3 2
<PV>CV9,CV10 change to 10pf.

Title
Issued Date 2011/07/12 Deciphered Date 2012/07/01
TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTIAL N15V-GM PCIE/DAC/GPIO
Custom 0.1
Date:
LA-B972P
Thursday, March 20, 2014 Sheet 32 of 54
1 2 3 4 5
1 2 3 4 5
UV1C
Part 3 of 5
AC3 D1 STRAP0
IFPA_TXC STRAP0 STRAP0 <39>
AC4 D2 STRAP1
STRAP
IFPA_TXC_N STRAP1 E4 STRAP2 STRAP1 <39>
Y4 IFPA_TXD0 STRAP2
Y3 E3 STRAP3 STRAP2 <39>
A AA3 IFPA_TXD0_N STRAP3 D3 STRAP4 STRAP3 <39> A
IFPA_TXD1 STRAP4 C1 STRAP4 <39>
AA2 IFPA_TXD1_N NC
AB1 IFPA_TXD2
AA1 IFPA_TXD2_N
AA4 IFPA_TXD3
AA5 IFPA_TXD3_N
DIS@
GENERAL
D11 RV28 1 2 100K_0402_5%
AB5 BUFRST_N
IFPB_TXC
AB4 E12
IFPB_TXC_N THERMDN
AB3 IFPB_TXD4 F12
AB2 THERMDP
AD3 IFPB_TXD4_N
IFPB_TXD5
LVDS / TMDS
AD2
IFPB_TXD5_N DIS@
AE1 IFPB_TXD6
AD1 D12 ROM_CS RV29 1 2 10K_0402_5% +3VGS
AD4 IFPB_TXD6_N ROM_CS_N
IFPB_TXD7 C12 ROM_SCLK
AD5 ROM_SCLK ROM_SCLK <39>
IFPB_TXD7_N
SERIAL
ROM_SI B12 ROM_SI
ROM_SI <39>
N4
N5 IFPC_AUX_I2CW_SCL A12 ROM_SO
IFPC_AUX_I2CW_SDA_N ROM_SO ROM_SO <39>
T2
T3 IFPC_L0
B B
T1 IFPC_L0_N
R1 IFPC_L1 AA6
IFPC_L1_N IFPAB_RSET
R2
R3 IFPC_L2 IFPC_RSET T6
N2 IFPC_L2_N
IFPC_L3 IFPD_RSET U6
N3
IFPC_L3_N
K6
P3 NC
P4 IFPD_AUX_I2CX_SCL
V3 IFPD_AUX_I2CX_SDA_N
V4 IFPD_L0 AD10
U3 IFPD_L0_N NC
AD7
U4 IFPD_L1 NC
B19
T4 IFPD_L1_N NC
T5 IFPD_L2 G1
R4 IFPD_L2_N NC_G1 G2
R5 IFPD_L3 NC_G2 G3
IFPD_L3_N NC_G3 G4
NC_G4 G5
J2 NC_G5 G6
J3 IFPE_AUX_I2CY_SCL NC_G6 G7
N1 IFPE_AUX_I2CY_SDA_N NC_G7
C M1 NC V1 C
M2 NC_V1 V2
NC
M3 NC_V2 V5
NC NC_V5
K2 V6
NC NC_V6
K3 NC
K1 W1
NC NC_W1 W2
J1
NC NC_W2 W3
NC NC_W3 W4
H3 NC_W4
H4
M4 IFPF_AUX_I2CZ_SCL
M5 IFPF_AUX_I2CZ_SDA_N
L3 NC E10
L4 NC NC
F10
K4 NC NC
K5 NC
J4 NC
J5 NC
NC
NC
N15V-GM
D D

Title
N15V-GM LVDS/HDMI/DP/THM
T H I S S H E E T O F E N G I N E E R I N G D R A W I N G IS T H E P R O P R I E T A R Y P R O P E R T Y O F C O M P A L E L E C T R O N I C S , INC. A N D C O N T A I N S C O N F I D E N T I A L
A N D T R A D E S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T B E T R A N S F E R E D F R O M T H E C U S T O D Y O F T H E C O M P E T E N T DIVISION O F R&D
B 0.1
Date:
LA-B972P
1 2 3 4 5
1 2 3 4 5
+1.5VGS
UV1D
Part 4 of 5
B26 K10
FBVDDQ VDD +VGA_CORE
C25 K12
FBVDDQ VDD
K14
CV28 DIS@
0.1U_0402_10V7K
CV20 DIS@
0.1U_0402_10V7K
CV21 DIS@
1U_0402_6.3V6K
CV22 DIS@
1U_0402_6.3V6K
CV23 DIS@
4.7U_0603_6.3V6K
CV24 DIS@
4.7U_0603_6.3V6K
CV29 DIS@
10U_0603_6.3V6M
CV26 DIS@
22U_0805_6.3V6M
E23 VDD
FBVDDQ K16
1 1 1 1 1 1 1 1 E26 VDD
FBVDDQ K18
F14 VDD
FBVDDQ L11
F21 VDD
FBVDDQ L13
G13 VDD
2 2 2 2 2 2 2 2 FBVDDQ L15
G14 VDD
FBVDDQ L17
G15 VDD
FBVDDQ M10
G16 VDD
FBVDDQ M12
G18 VDD
FBVDDQ
Reference circuit: G19
FBVDDQ VDD
M14
A G20 M16 A
0.1uF *2 G21
FBVDDQ VDD
M18
FBVDDQ VDD
1 uF*2 H24
FBVDDQ VDD
N11
H26 N13
4.7uF*2 J21
FBVDDQ VDD
N15
VDD
10uF*1 K21
FBVDDQ
VDD
N17
FBVDDQ P10
22uF*1 L22
FBVDDQ VDD
P12
L24 VDD
FBVDDQ P14
L26 VDD
FBVDDQ P16
M21 VDD
FBVDDQ P18
N21 VDD
FBVDDQ R11
R21 VDD
FBVDDQ R13
T21 VDD
FBVDDQ R15
V21 VDD
FBVDDQ R17
W 21 VDD
FBVDDQ T10
POWER
VDD
AA10 T12
+1.05VGS PEX_IOVDDQ VDD
AA12 T14
PEX_IOVDDQ VDD
AA13 T16
CV51 DIS@
1U_0402_6.3V6K
CV52 DIS@
1U_0402_6.3V6K
CV53 DIS@
4.7U_0603_6.3V6K
CV54 DIS@
10U_0805_6.3V6M
CV55 DIS@
10U_0805_6.3V6M
CV56 DIS@
22U_0805_6.3V6M
CV57 DIS@
22U_0805_6.3V6M
PEX_IOVDDQ VDD
Reference circuit: 1 1 1 1 1 1 1 AA16
PEX_IOVDDQ VDD
T18
AA18 U11
1uF *2 AA19 PEX_IOVDDQ VDD
U13
PEX_IOVDDQ VDD
4.7uF*1 2 2 2 2 2 2 2
AA20
PEX_IOVDDQ VDD
U15
AA21 U17
10uF*2 AB22 PEX_IOVDDQ VDD
V10
VDD
22uF*2 AC23 PEX_IOVDDQ
VDD
V12
AD24 PEX_IOVDDQ V14
PEX_IOVDDQ VDD
AE25 V16
AF26 PEX_IOVDDQ VDD
V18 Power :VDD_SENSE & GND_SENSE
AF27 PEX_IOVDDQ VDD Differential signal
PEX_IOVDDQ VCCSENSE_VGA
F2 VCCSENSE_VGA <53>
VDD_SENSE
Reference circuit:
CV58 DIS@
1U_0402_6.3V6K
CV59 DIS@
1U_0402_6.3V6K
CV60 DIS@
4.7U_0603_6.3V6K
CV61 DIS@
10U_0805_6.3V6M
CV62 DIS@
10U_0805_6.3V6M
CV63 DIS@
22U_0805_6.3V6M
CV69 DIS@
22U_0805_6.3V6M
AA22
PEX_IOVDD short@1 RV30 2
AB23 G10
1uF *2 1 1 1 1 1 1 1 PEX_IOVDD VDD33 0_0603_5%
+3VGS
CV64
0.1U_0402_10V7K
CV65 DIS@
0.1U_0402_10V7K
CV66 DIS@
0.1U_0402_10V7K
CV67 DIS@
1U_0402_6.3V6K
CV68 DIS@
4.7U_0603_6.3V6K
AC24 G12
PEX_IOVDD VDD33
B
4.7uF*1 AD25
PEX_IOVDD VDD33
G8 1 1 1 1 1 B
AE26 G9
10uF*2 2 2 2 2 2 2 2 AE27
PEX_IOVDD VDD33
22uF*2 PEX_IOVDD F11
DIS@
NC 2 2 2 2 2
+PEX_3V3_NV AA8 AB8 +PEX_3V3_NV

PEX_PLL_HVDD PEX_SVDD_3V3
AA9
PEX_PLL_HVDD W6
IFPA_IOVDD Y6
<SI> LV1 use R_0402 footprint +PEXPLL_VDD AA14 IFPB_IOVDD P6
RV34 1 2 0_0402_5% +PEX_3V3_NV DIS@ AA15 PEX_PLLVDD IFPC_IOVDD R6
+3VGS PEX_PLLVDD IFPD_IOVDD H6
short@ LV1 +GPU_SP_PLLVDD N6
BLM18PG121SN1D_060 M6 VID_PLLVDD NC J6
CV70 DIS@
0.1U_0402_10V7K
CV71 DIS@
4.7U_0603_6.3V6K
CV72 DIS@
4.7U_0603_6.3V6K
3 +GPU_PLLVDD L6 SP_PLLVDD NC
1 1 1 +1.05VGS CORE_PLLVDD
1 2 +FB_PLLAVDD F16 V7 Remove IFPC_PLLVDD,IFPD_PLLVDD,IFPC_IOVDD,IFPD_IOVDD,IFPAB_PLLVDD,+DACA_VDD,IFPA_IOVDD
FB_PLLAVDD IFPAB_PLLVDD W 7
#8/19,LV1 change to P22
CV73
0.1U_0402_10V7K
CV74 DIS@
22U_0805_6.3V6M
H22 FB_PLLAVDD IFPAB_PLLVDD
2 2 2 Z=30 ohm , RDC=0.05 1 1 FB_DLLAVDD M7
IFPC_PLLVDD N7
SM01000F100 IFPC_PLLVDD
W5
DIS@
PCB Footprint = R_0402 2 2 DACA_VDD R7

+FB_CAL_PD_VDDQ D22 IFPD_PLLVDD T7
FB_CAL_PD_VDDQ IFPD_PLLVDD
F3 J7
FB_CLAMP NC
RV45 1 2 0_0402_5% +PEXPLL_VDD FB_CLAMP K7
+1.05VGS NC
short@
RV47 1 2 0_0402_5%
CV75 DIS@
0.1U_0402_10V7K
CV76 DIS@
1U_0402_6.3V6K
CV77
4.7U_0603_6.3V6K
<9> DGPU_GC6_EN short@

1 1 1
DIS@
2 2 2 N15V-GM
DIS@
C C
DIS@
LV3
BLM18PG121SN1D_060
3 1 2 +GPU_SP_PLLVDD
+1.05VGS
DG : LV3 ‐>Z=180 ohm , RDC=0.2 ohm.0603

CV82 DIS@
0.1U_0402_10V7K
CV83 DIS@
0.1U_0402_10V7K
CV84 DIS@
4.7U_0603_6.3V6K
CV85 DIS@
22U_0805_6.3V6M
1 1 1 1 DIS@
1 2 +FB_CAL_PD_VDDQ
<PV>LV3,LV4 changePN. +1.5VGS
RV50 40.2_0402_1%
Main:SM01000BW00 2 2 2 2 #7/27 Follow DG to chenge

R1591 to 40.2 ohm
2nd:SM01000CC00
DG:LV4‐>Z=30 ohm , RDC=0.01 ohm.0603 +FB_PLLAVDD

LV4 DIS@
BLM18PG121SN1D_060
+1.05VGS 3 1 2
CV91 DIS@
0.1U_0402_10V7K
CV90 DIS@
0.1U_0402_10V7K
CV88 DIS@
0.1U_0402_10V7K
CV89 DIS@
22U_0805_6.3V6M
1 1 1 1
2 2 2 2
D D

Title
TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTIAL N15V-GM POWER
Custom 0.1
Date:
LA-B972P
1 2 3 4 5
1 2 3 4 5
UV1E
Part 5 of 5
AA7 L10
GND GND
A2 L12
GND GND
A26 L14
GND GND
AB11 L16
GND GND
AB14 L18
GND GND
AB17 L2
GND GND
AB20 L23
GND GND
AB24 L25
GND GND
AC2 L5
GND GND
AC22 M11
GND GND
AC26 M13
GND GND
A AC5 M15 A
GND GND
AC8 M17
GND GND
AD12 N10
GND GND
AD13 N12
GND GND
AD15 N14
GND GND
AD16 N16
GND GND
AD18 N18
GND GND
AD19 P11
GND
GND GND
AD21 P13
GND GND
AD22 P15
GND GND
AE11 P17
AE14
GND GND
P2
#8/20 : N15V‐GM don't support GC6 function. UV20 unpop.
GND GND
AE17 P23
GND GND
AE20 P26
GND GND
AF1 P5
GND GND
AF11 R10
GND GND
AF14 R12
GND GND
AF17 R14
GND GND
AF20 R16
GND GND
AF23 R18
GND GND
AF5 T11
GND GND
AF8 T13
GND GND
AG2 T15
GND GND
AG26 T17
GND GND
B1 U10
GND GND
B11 U12
GND GND
B14 U14
GND GND
B17 U16
GND GND
B20 U18
GND GND
B23 U2
GND GND
B27 U23
GND GND
B5 U26
GND GND
B8 U5
E11 GND GND V11
GND GND
E14 V13
B E17 GND GND V15 B
E2 GND GND V17
E20 GND GND Y2
E22
E25
E5
GND
GND
GND
GND
GND
GND
Y23
Y26
Y5
+1.05VGS=1.6A,4vias.
J2 @
E8 GND GND AB7 2 1
GND GND +1.05V_GPU 2 1 +1.05VGS
H2
H23 GND C24 1 DIS@ 2 JUMP_43X79
H25 GND FB_CAL_PU_GND RV67 42.2_0402_1%
H5 GND B25 1 DIS@ 2
K11 GND FB_CAL_T ERM_GND 51.1_0402_1%
RV68
K13 GND 2 40.2K_0402_1%
F6 1
K15 GND MULTI_STRAP_REF0_GND F4 RV70 @ #8/19.RV70 unpop , N15V‐GM use binary mode. +3VALW to +3VGS
K17 GND NC F5
GND NC Contrl by power
GND_SENSE
F1 VSSSENSE_VGA
VSSSENSE_VGA <53>
+1.05V to +1.05VGS +1.05V_GPU
N15V-GM
DIS@ Power :VDD_SENSE & GND_SENSE
+3VALW +1.05V
Differential signal DIS@
QV12
1 14
Power on 2 VIN1 VOUT1 13
RV92 VIN1 VOUT1
DGPU_PWROK DIS@ 3 12 CV181 1 2 680P_0402_50V7K
ON1 CT1
DGPU_PWR_EN +5VALW 20K_0402_5% 4 11 DIS@
VBIAS GND
<30,53,9> DGPU_PWR_EN DGPU_PWR_EN 5 10 CV182 1 2 100P_0402_50V8J
+3VGS
+1.5VGS=3.6A,8vias. 6
ON2
VIN2 VOUT2
CT2
9 DIS@
C
+VGA_CORE 2
J3 @
1
7
VIN2 VOUT2
8
C
+1.5VGS_GPU 2 1 +1.5VGS
15
GPAD
DGPU_PWROK JUMP_43X118
#8/19.QV15 change to TPS22967 TPS22966DPUR_SON14_2X3-D
+3VGS
+1.05VGS +1.5V to +1.5VGS +3VGS=0.5A,2vias.

+1.5VGS_GPU
+1.5VGS +1.5VS QV15
1 7 +1.05VGS
2 VIN VOUT 8
40us < Rt < 2ms 1
VIN VOUT +3VALW
DIS@ CV81 3 6
ON CT
2
1 1 1 DIS@
10U_0603_6.3V6M DIS@ CV80 CV79 RC370 DIS@
2 4 CV183 DIS@ 18_0402_5%
+5VALW VBIAS
1
1U 6.3V K X5R 0402
5
GND 2 2 2 RV210 SD028180A80
100P_0402_50V8J
10U_0603_6.3V6M
9
1
GND DIS@
DIS@ 100K_0402_5%
3
<53> DGPU_PWROK DGPU_PWROK RV66 1 2 TPS22967DSGR_SON8_2X2
2
47K_0402_5% 1
#08/20 Don't support GC6,Add RV66. DIS@
CV78 @ 5 QV17B
Unpop QV16,RV41,RV42,CV78. 0.01U_0603_50V7K DMN66D0LDW-7_SOT363-6
6
2
4
DIS@
DGPU_PWROK 2 QV17A
DMN66D0LDW-7_SOT363-6
1
D D
PV# 2013.01.08 Add +1.05VGS discharge circuit

Title
TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTIAL N15V-GM VGA CORE, GND
Custom 0.1
Date:
LA-B972P
1 2 3 4 5
1 2 3 4 5
PU for X16 mode

UV1B
Part 2 of 5
MDA0 E18 C27 CMDA0
<37> MDA0 FBA_D0 FBA_CMD0 CMDA0 <37>
A MDA1 F18 C26 Dummy A
<37> MDA1 FBA_D1 FBA_CMD1
<37> MDA2
MDA2 E16 E24 CMDA2
CMDA2 <37>
Note: DG use 1%
MDA3 F17 FBA_D2 FBA_CMD2 F24 CMDA3
<37> MDA3 FBA_D3 FBA_CMD3 CMDA3 <37>
<37> MDA4 MDA4 D20 D27 CMDA4 CMDA4 <37,38>
MDA5 D21 FBA_D4 FBA_CMD4 D26 CMDA5 DIS@
<37> MDA5 FBA_D5 FBA_CMD5 CMDA5 <37,38>
MDA6 F20 F25 CMDA6 2 RV169 1 CMDA2
<37> MDA6 FBA_D6 FBA_CMD6 CMDA6 <37,38>
<37> MDA7 MDA7 E21 F26 CMDA7 CMDA7 <37,38> 10K_0402_1%
FBA_D7 FBA_CMD7
<37>
<37>
MDA8
MDA9
MDA8
MDA9
E15
D15 FBA_D8 FBA_CMD8
F23
G22
CMDA8
CMDA9
CMDA8 <37,38>
CMDA9 <37,38>
DIS@
2 RV170 1 CMDA18 Mode D Command Mapping
MDA10 F15 FBA_D9 FBA_CMD9 G23 CMDA10 10K_0402_1%
<37> MDA10 CMDA10 <37,38>
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11 DIS@ RANK 0
<37> MDA11 CMDA11 <37,38>
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12 2 RV185 1 CMDA3
<37> MDA12 CMDA12 <37,38>
<37> MDA13 MDA13 B13 FBA_D12
FBA_D13
FBA_CMD12
FBA_CMD13
G25 CMDA13 CMDA13 <37,38> 10K_0402_1% Address 0..31 32..63
<37> MDA14 MDA14 E13 G27 Dummy DIS@
<37> MDA15 MDA15 D13 FBA_D14
FBA_D15
FBA_CMD14
FBA_CMD15
G26 CMDA15
CMDA15 <37,38>
2 RV189 1 CMDA19 FBx_CMD0 CS0#
<37> MDA16 MDA16 B15 M24 CMDA16 10K_0402_1%
CMDA16 <38>
<37> MDA17 MDA17 C16 FBA_D16 FBA_CMD16 M23 Dummy DIS@
2 RV190
FBx_CMD1
<37> MDA18 MDA18 A13 FBA_D17 FBA_CMD17 K24 CMDA18 1 CMDA5
CMDA18 <38>
<37> MDA19 MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19
CMDA19 <38>
10K_0402_1% FBx_CMD2 ODT
<37> MDA20 MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20
CMDA20 <37,38>
<37> MDA21 MDA21 A18 FBA_D20 FBA_CMD20 M26 CMDA21
CMDA21 <37,38> FBx_CMD3 CKE
<37> MDA22 MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22
CMDA22 <37,38>
<37> MDA23 MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23 CMDA23 <37,38> FBx_CMD4 A14 A14
<37> MDA24 MDA24 B24 FBA_D23 FBA_CMD23 K22 CMDA24 CMDA24 <37,38>
<37> MDA25 MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 CMDA25 <37,38> FBx_CMD5 RST RST
MEMORY INTERFACE
<37> MDA26 MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26
<37> MDA27 CMDA26 <37,38>
<37> MDA28
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27 CMDA27 <37,38> FBx_CMD6 A9 A9
MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28
<37> MDA29 CMDA28 <37,38>
<37> MDA30
MDA29 B21 FBA_D28 FBA_CMD28 K25 CMDA29 CMDA29 <37,38> FBx_CMD7 A7 A7
MDA30 C20 FBA_D29 FBA_CMD29 J27 CMDA30 CMDA30 <37,38>
<37> MDA31
<38> MDA32
MDA31 C21 FBA_D30 FBA_CMD30 J26 FBx_CMD8 A2 A2
MDA32 R22 FBA_D31 FBA_CMD31
<38> MDA33
<38> MDA34 MDA33 R24 FBA_D32 FBx_CMD9 A0 A0
MDA34 T22 FBA_D33 D19 DQMA0
<38> MDA35 FBA_DQM0 DQMA0 <37>
B <38> MDA36 MDA35 R23 FBA_D34
FBA_DQM1
D14 DQMA1
DQMA1 <37> FBx_CMD10 A4 A4 B
MDA36 N25 FBA_D35 C17 DQMA2
<38> MDA38 MDA37 N26 FBA_D36
FBA_DQM3
C22 DQMA3 DQMA3 <37> FBx_CMD11 A1 A1
MDA38 N23 FBA_D37 P24 DQMA4
<38> MDA40 MDA39 N24 FBA_D38
FBA_DQM5
W 24 DQMA5 DQMA5 <38> FBx_CMD12 BA0 BA0
<38> MDA41 MDA40 V23 FBA_D39 AA25 DQMA6
FBA_DQM6 DQMA6 <38>
<38> MDA42 MDA41 V22 FBA_D40
FBA_DQM7
U25 DQMA7 DQMA7 <38> FBx_CMD13 WE# WE#
<38> MDA43 MDA42 T23 FBA_D41
<38> MDA44 MDA43 U22 FBA_D42 F19 DQSA#0
DQSA#0 <37>
FBx_CMD14
<38> MDA45 MDA44 Y24 FBA_D43 FBA_DQS_RN0 C14 DQSA#1
DQSA#1 <37>
<38> MDA46 MDA45 AA24 FBA_D44 FBA_DQS_RN1 A16 DQSA#2
DQSA#2 <37> FBx_CMD15 CAS# CAS#
<38> MDA47 MDA46 Y22 FBA_D45 FBA_DQS_RN2 A22 DQSA#3
DQSA#3 <37>
<38> MDA48 MDA47 AA23 FBA_D46 FBA_DQS_RN3 P25 DQSA#4 DQSA#4 <38> FBx_CMD16 CS0#
<38> MDA49 MDA48 AD27 FBA_D47 FBA_DQS_RN4 W 22 DQSA#5 DQSA#5 <38>
<38> MDA50 MDA49 AB25 FBA_D48 FBA_DQS_RN5 AB27 DQSA#6 DQSA#6 <38> FBx_CMD17
<38> MDA51 MDA50 AD26 FBA_D49 FBA_DQS_RN6 T27 DQSA#7 DQSA#7 <38>
<38> MDA52 MDA51 AC25 FBA_D50 FBA_DQS_RN7 FBx_CMD18 ODT
<38> MDA53 MDA52 AA27 FBA_D51 E19 DQSA0
DQSA0 <37>
<38> MDA54 MDA53 AA26 FBA_D52 FBA_DQS_W P0 C15 DQSA1
DQSA1 <37> FBx_CMD19 CKE
<38> MDA55 MDA54 W 26 FBA_D53 FBA_DQS_W P1 B16 DQSA2 DQSA2 <37>
<38>
<38>
MDA56
MDA57
MDA55 Y25 FBA_D54 FBA_DQS_W P2 B22 DQSA3 DQSA3 <37> FBx_CMD20 A13 A13
MDA56 R26 FBA_D55 FBA_DQS_W P3 R25 DQSA4
<38> MDA58 DQSA4 <38>
<38> MDA59
MDA57 T25 FBA_D56 FBA_DQS_W P4 W 23 DQSA5 DQSA5 <38> FBx_CMD21 A8 A8
MDA58 N27 FBA_D57 FBA_DQS_W P5 AB26 DQSA6 DQSA6 <38>
<38> MDA60
<38> MDA61
MDA59 R27 FBA_D58 FBA_DQS_W P6 T26 DQSA7 DQSA7 <38> FBx_CMD22 A6 A6
MDA60 V26 FBA_D59 FBA_DQS_W P7
<38> MDA62
<38> MDA63
MDA61 V27 FBA_D60 D18 FBx_CMD23 A11 A11
MDA62 W 27 FBA_D61 FBA_W CK01 C18
MDA63 W 25 FBA_D62 FBA_W CK01_N D17 FBx_CMD24 A5 A5
FBA_D63 FBA_W CK23 D16
T1405 D23 FBA_W CK23_N T24 FBx_CMD25 A3 A3
FB_VREF_PROBE FBA_W CK45 U24
<37> CLKA0
CLKA0 D24 FBA_W CK45_N V24 FBx_CMD26 BA2 BA2
CLKA0# D25 FBA_CLK0 FBA_W CK67 V25
<37> CLKA0#
FBA_CLK0_N FBA_W CK67_N FBx_CMD27 BA1 BA1
C CLKA1 N22 C
<38> CLKA1 FBA_CLK1
<38> CLKA1#
CLKA1# M22
FBA_CLK1_N FBA_DEBUG0
F22 RV137 1 @ 2 60.4_0402_1% +1.5VGS FBx_CMD28 A12 A12
J22 RV138 1 @ 2 60.4_0402_1%
FBA_DEBUG1
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
N15V-GM
DIS@
D D

Title
TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTIAL N15V-GM MEM Interface
Custom 0.1
Date:
LA-B972P
1 2 3 4 5
1 2 3 4 5
Memory Partition A RANK 0 MDA[0..63] <36,38>
CMDA[30..0] <36,38>
+1.5VGS
Rank 0 Data0~Data31
Rank 0
1
RV139
1.33K_0402_1%
DIS@ UV12 X76@ UV14 X76@
2
+FBA_VREF0 +FBA_VREF0 M8 E3 MDA19 +FBA_VREF0 M8 E3 MDA4
A
H1 VREFCA DQL0 H1 VREFCA DQL0 A
F7 MDA21 F7 MDA0
VREFDQ DQL1 F2 VREFDQ DQL1 F2
CV96 DIS@
0.01U_0402_16V7K
MDA16 MDA5
DQL2 DQL2
1
CMDA9 N3 F8 MDA22 CMDA9 N3 F8 MDA2

RV140
1
CMDA11 P7 A0 DQL3
H3 MDA18
Group 2 CMDA11 P7 A0 DQL3
H3 MDA7
1.33K_0402_1% CMDA8 P3 A1 DQL4
H8 MDA23 CMDA8 P3 A1 DQL4
H8 MDA1 Group 0
DQL5 DQL5
DIS@
2
CMDA25
CMDA10
N2
P8
A2
A3 DQL6
G2
H7
MDA17
MDA20
CMDA25
CMDA10
N2
P8
A2
A3 DQL6
G2
H7
MDA6
MDA3
Mode D Command Mapping
2
CMDA24 P2 A4 DQL7 CMDA24 P2 A4 DQL7

CMDA22 R8 A5
A6
CMDA22 R8 A5
A6
RANK 0
CMDA7 R2 D7 MDA10 CMDA7 R2 D7 MDA31
DQU0 DQU0
CMDA21 T8 A7
A8 DQU1
C3 MDA13 CMDA21 T8 A7
A8 DQU1
C3 MDA27 Address 0..31 32..63
CMDA6 R3 C8 MDA11 CMDA6 R3 C8 MDA30
DQU2 DQU2
CMDA29 L7 A9
A10/AP DQU3
C2 MDA14
Group 1 CMDA29 L7 A9
A10/AP DQU3
C2 MDA25
Group 3 FBx_CMD0 CS0#
CMDA23 R7 A7 MDA8 CMDA23 R7 A7 MDA28
DQU4 DQU4
CLKA0 CMDA28 N7 A11
DQU5
A2 MDA15 CMDA28 N7 A11
DQU5
A2 MDA26 FBx_CMD1
CMDA20 T3 A12 B8 MDA9 CMDA20 T3 A12 B8 MDA29
DQU6 DQU6
CMDA4 T7 A13
DQU7
A3 MDA12 CMDA4 T7 A13
DQU7
A3 MDA24 FBx_CMD2 ODT
1
M7 A14 M7 A14
RV141 A15/BA3 +1.5VGS A15/BA3 +1.5VGS FBx_CMD3 CKE
162_0402_1%
DIS@ CMDA12 M2
BA0 VDD
B2 CMDA12 M2
BA0 VDD
B2 FBx_CMD4 A14 A14
CMDA27 N8 D9 CMDA27 N8 D9
2
VDD VDD
CMDA26 M3 BA1
BA2 VDD
G7 CMDA26 M3 BA1
BA2 VDD
G7 FBx_CMD5 RST RST
CLKA0# K2 K2
VDD VDD
VDD
K8
VDD
K8 FBx_CMD6 A9 A9
#8/19 , change CLK VDD
N1
VDD
N1
termination to 162 ohm. <36> CLKA0 CLKA0 J7
CK VDD
N9 CLKA0 J7
VDD
N9 FBx_CMD7 A7 A7
CLKA0# K7 R1 CLKA0# K7 CK R1
<36> CLKA0# VDD VDD
CMDA3 K9 CK
CKE/CKE0 VDD
R9 CMDA3 K9 CK
VDD
R9 FBx_CMD8 A2 A2
B CKE/CKE0 B
160 ohm:SD00000XP00 FBx_CMD9 A0 A0
CMDA2 K1 A1 CMDA2 K1 A1
VDDQ ODT/ODT0 VDDQ
CMDA0 L2 ODT/ODT0
CS/CS0 VDDQ
A8 CMDA0 L2
CS/CS0 VDDQ
A8 FBx_CMD10 A4 A4
CMDA30 J3 C1 CMDA30 J3 C1
VDDQ RAS VDDQ
CMDA15 K3
RAS
CAS VDDQ
C9 CMDA15 K3
CAS VDDQ
C9 FBx_CMD11 A1 A1
CMDA13 L3 D2 CMDA13 L3 D2
VDDQ VDDQ
WE
VDDQ
E9 WE
VDDQ
E9 FBx_CMD12 BA0 BA0
F1 F1
VDDQ VDDQ
<36> DQSA2
DQSA2 F3
VDDQ
H2
<36> DQSA0
DQSA0 F3
VDDQ
H2 FBx_CMD13 WE# WE#
DQSA1 C7 DQSL H9 DQSA3 C7 DQSL H9
<36> DQSA1 VDDQ <36> DQSA3 VDDQ
DQSU DQSU FBx_CMD14
H:Group 1 <36> DQMA2
DQMA2 E7
DML VSS
A9
L:Group 0 <36> DQMA0
DQMA0 E7
DML VSS
A9 FBx_CMD15 CAS# CAS#
DQMA1 D3 B3 DQMA3 D3 B3
<36> DQMA1 VSS <36> DQMA3 VSS
L:Group 2
DMU
VSS
E1
H:Group 3
DMU
VSS
E1 FBx_CMD16 CS0#
G8 G8
VSS VSS
<36> DQSA#2 DQSA#2 G3
DQSL VSS
J2
<36> DQSA#0 DQSA#0 G3
VSS
J2 FBx_CMD17
DQSA#1 B7 J8 DQSA#3 B7 DQSL J8
<36> DQSA#1 VSS <36> DQSA#3 VSS
DQSU
VSS
M1 DQSU
VSS
M1 FBx_CMD18 ODT
M9 M9
VSS VSS
VSS
P1
VSS
P1 FBx_CMD19 CKE
CMDA5 T2 P9 CMDA5 T2 P9
RESET VSS VSS
VSS
T1 RESET
VSS
T1 FBx_CMD20 A13 A13
L8 T9 L8 T9
ZQ/ZQ0 VSS VSS
ZQ/ZQ0 FBx_CMD21 A8 A8
1
1
J1
NC/ODT1 VSSQ
B1 J1
NC/ODT1 VSSQ
B1 FBx_CMD22 A6 A6
RV145 L1 B9 RV150 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
C
243_0402_1% J9
NC/CE1 VSSQ
D1 243_0402_1% J9
NC/CE1 VSSQ
D1 FBx_CMD23 A11 A11 C
DIS@ L9 D8 DIS@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 FBx_CMD24 A5 A5
2
VSSQ
2
E8 VSSQ E8
VSSQ VSSQ
VSSQ
F9
VSSQ
F9 FBx_CMD25 A3 A3
G1 G1
VSSQ VSSQ
VSSQ
G9
VSSQ
G9 FBx_CMD26 BA2 BA2
96-BALL 96-BALL FBx_CMD27 BA1 BA1
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 FBx_CMD28 A12 A12
FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VGS
L Closed to UV12
+1.5VGS
L Closed to UV14
CV97 DIS@
0.1U_0402_16V7K
CV98 DIS@
0.1U_0402_16V7K
CV99 DIS@
0.1U_0402_16V7K
CV100 DIS@
0.1U_0402_16V7K
CV101 DIS@
0.1U_0402_16V7K
CV102 DIS@
1U_0402_6.3V6K
CV103 DIS@
1U_0402_6.3V6K
CV104 DIS@
1U_0402_6.3V6K
CV105 DIS@
1U_0402_6.3V6K
CV106 DIS@
1U_0402_6.3V6K
2 2 2 2 2 1 1 1 1 1
CV118 DIS@
0.1U_0402_16V7K
CV119 DIS@
0.1U_0402_16V7K
CV120 DIS@
0.1U_0402_16V7K
CV121 DIS@
0.1U_0402_16V7K
CV122 DIS@
0.1U_0402_16V7K
CV123 DIS@
1U_0402_6.3V6K
CV124 DIS@
1U_0402_6.3V6K
CV125 DIS@
1U_0402_6.3V6K
CV126 DIS@
1U_0402_6.3V6K
CV127 DIS@
1U_0402_6.3V6K
1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1
1 1 1 1 1 2 2 2 2 2
D D

Title
T HIS SH EET O F EN G IN EER IN G D R AW IN G IS T H E PR O PR IET AR Y PR O PER T Y O F C O MPAL ELEC T R O N IC S, INC. AN D CONT AINS CONFIDENT IAL
N15V-GM VRAM A Lower
Custom 0.1
Date:
LA-B972P
1 2 3 4 5
1 2 3 4 5
Memory Partition A RANK 0 32 bits MDA[0..63] <36,37>

+1.5VGS
Rank 0
CMDA[30..0] <36,37>
1
RV152
1.33K_0402_1%
DIS@ 2
Data32~Data63 Rank 0
A A
+FBA_VREF1 UV16 X76@ UV18 X76@
+FBA_VREF1 M8 E3 MDA35 +FBA_VREF1 M8 E3 MDA52

CV138 DIS@
0.01U_0402_16V7K VREFCA DQL0 VREFCA DQL0

1
1 H1 F7 MDA37 H1 F7 MDA49
RV153 VREFDQ DQL1 F2 MDA34 VREFDQ DQL1 F2 MDA53
1.33K_0402_1% CMDA9 N3 DQL2 F8 MDA39 CMDA9 N3 DQL2 F8 MDA50
A0 DQL3 A0 DQL3 Group 6
DIS@
2
CMDA11
CMDA8
P7
P3 A1 DQL4
H3
H8
MDA32
MDA38 Group 4 CMDA11
CMDA8
P7
P3 A1 DQL4
H3
H8
MDA54
MDA48 Mode D Command Mapping
2
CMDA25 N2 A2 DQL5 G2 MDA33 CMDA25 N2 A2 DQL5 G2 MDA55

A3 DQL6 A3 DQL6
CMDA10 P8
A4 DQL7
H7 MDA36 CMDA10 P8
A4 DQL7
H7 MDA51 RANK 0
CMDA24 P2 CMDA24 P2
A5 A5
CMDA22 R8
A6
CMDA22 R8
A6
Address 0..31 32..63
CMDA7 R2 D7 MDA56 CMDA7 R2 D7 MDA44
CMDA21 T8 A7 DQU0 C3 MDA60 CMDA21 T8 A7 DQU0 C3 MDA40 FBx_CMD0 CS0#
CMDA6 R3 A8 DQU1 C8 MDA58 CMDA6 R3 A8 DQU1 C8 MDA46
CMDA29 L7 A9
A10/AP
DQU2 C2 MDA61
Group 7 CMDA29 L7 A9
A10/AP
DQU2 C2 MDA41
Group 5 FBx_CMD1
CMDA23 R7 DQU3 A7 MDA57 CMDA23 R7 DQU3 A7 MDA45
CMDA28 N7 A11 DQU4 A2 MDA63 CMDA28 N7 A11 DQU4 A2 MDA43 FBx_CMD2 ODT
CMDA20 T3 A12 DQU5 B8 MDA59 CMDA20 T3 A12 DQU5 B8 MDA47
CMDA4 T7 A13
A14
DQU6 A3 MDA62 CMDA4 T7 A13
A14
DQU6 A3 MDA42 FBx_CMD3 CKE
CLKA1 M7 DQU7 M7 DQU7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS FBx_CMD4 A14 A14
FBx_CMD5 RST RST
1
CMDA12 M2 B2 CMDA12 M2 B2
RV154 CMDA27 N8 BA0 VDD D9 CMDA27 N8 BA0 VDD D9
BA1 VDD BA1 VDD
162_0402_1% CMDA26 M3
BA2 VDD
G7 CMDA26 M3
BA2 VDD
G7 FBx_CMD6 A9 A9
DIS@ K2 K2
VDD VDD
K8 K8 FBx_CMD7 A7 A7
2
VDD N1 VDD N1
310mA VDD VDD
B CLKA1#
<36> CLKA1
CLKA1 J7
CK VDD
N9 CLKA1 J7
CK VDD
N9 FBx_CMD8 A2 A2 B
CLKA1# K7 R1 CLKA1# K7 R1
<36> CLKA1# CK VDD CK VDD
#8/19 , change CLK CMDA19 K9
CKE/CKE0 VDD
R9 CMDA19 K9
CKE/CKE0 VDD
R9 FBx_CMD9 A0 A0
termination to 162 ohm. FBx_CMD10 A4 A4
CMDA18 K1 A1 CMDA18 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CMDA16 L2
CS/CS0 VDDQ
A8 CMDA16 L2
CS/CS0 VDDQ
A8 FBx_CMD11 A1 A1
CMDA30 J3 C1 CMDA30 J3 C1
RAS VDDQ RAS VDDQ
CMDA15 K3
CAS VDDQ
C9 CMDA15 K3
CAS VDDQ
C9 FBx_CMD12 BA0 BA0
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ WE VDDQ
VDDQ
E9
VDDQ
E9 FBx_CMD13 WE# WE#
F1 F1
VDDQ VDDQ
<36> DQSA4
DQSA4 F3
DQSL VDDQ
H2
<36> DQSA6
DQSA6 F3
DQSL VDDQ
H2 FBx_CMD14
DQSA7 C7 H9 DQSA5 C7 H9
<36> DQSA7 DQSU VDDQ <36> DQSA5 DQSU VDDQ
FBx_CMD15 CAS# CAS#

DQMA4 E7
DML VSS
A9
DQMA6 E7
DML VSS
A9 FBx_CMD16 CS0#
DQMA7 D3 B3 DQMA5 D3 B3
<36> DQMA7 DMU VSS <36> DQMA5 DMU VSS
H:Group 7 VSS
E1
H:Group 5 VSS
E1 FBx_CMD17
G8 G8
VSS VSS
<36> DQSA#4
DQSA#4 G3
DQSL VSS
J2
<36> DQSA#6
DQSA#6 G3
DQSL VSS
J2 FBx_CMD18 ODT
DQSA#7 B7 J8 DQSA#5 B7 J8
<36> DQSA#7 DQSU VSS <36> DQSA#5 DQSU VSS
VSS
M1
VSS
M1 FBx_CMD19 CKE
M9 M9
VSS VSS
VSS
P1
VSS
P1 FBx_CMD20 A13 A13
CMDA5 T2 RESET P9 CMDA5 T2 P9
VSS T1 RESET VSS T1 FBx_CMD21 A8 A8
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS FBx_CMD22 A6 A6
C
FBx_CMD23 A11 A11 C
1
1
J1 B1 J1 B1
RV155 L1 NC/ODT1 VSSQ B9 RV162 L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9
NC/CE1 VSSQ
D1 243_0402_1% J9
NC/CE1 VSSQ
D1 FBx_CMD24 A5 A5
DIS@ L9 D8 DIS@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 FBx_CMD25 A3 A3
2
2
VSSQ E8 VSSQ E8
VSSQ VSSQ
VSSQ
F9
VSSQ
F9 FBx_CMD26 BA2 BA2
G1 G1
VSSQ VSSQ
VSSQ
G9
VSSQ
G9 FBx_CMD27 BA1 BA1
96-BALL 96-BALL FBx_CMD28 A12 A12
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 FBx_CMD29 A10 A10
FBx_CMD30 RAS# RAS#
+1.5VGS
L Closed to UV16 +1.5VGS
L Closed to UV18
CV139 DIS@
0.1U_0402_16V7K
CV140 DIS@
0.1U_0402_16V7K
CV141 DIS@
0.1U_0402_16V7K
CV142 DIS@
0.1U_0402_16V7K
CV143 DIS@
0.1U_0402_16V7K
CV144 DIS@
1U_0402_6.3V6K
CV145 DIS@
1U_0402_6.3V6K
CV146 DIS@
1U_0402_6.3V6K
CV147 DIS@
1U_0402_6.3V6K
CV148 DIS@
1U_0402_6.3V6K
CV160 DIS@
0.1U_0402_16V7K
CV161 DIS@
0.1U_0402_16V7K
CV162 DIS@
0.1U_0402_16V7K
CV163 DIS@
0.1U_0402_16V7K
CV164 DIS@
0.1U_0402_16V7K
CV165 DIS@
1U_0402_6.3V6K
CV166 DIS@
1U_0402_6.3V6K
CV167 DIS@
1U_0402_6.3V6K
CV168 DIS@
1U_0402_6.3V6K
CV169 DIS@
1U_0402_6.3V6K
2 2 2 2 2 1 1 1 1 1
2 2 2 2 2 1 1 1 1 1
1 1 1 1 1 2 2 2 2 2
1 1 1 1 1 2 2 2 2 2
D D

Title
TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTIAL
Size Document Number
N15V-GM VRAM C Lower Rev
Custom 0.1
Date:
LA-B972P
1 2 3 4 5
1 2 3 4 5
+3VGS
Table 123
Strap pin Strap Mapping Resistance Polarity Logical
Name Strapping Bit0
Check Strap pin status ROM_SCLK SMB_ALT_ADDR 10K Pull-down to GND.
1
RV164 RV165 RV166 RV167 RV168 ROM_SI SUB_VENDOR 10K Pull-down to GND if no VBIOS ROM.
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76@ X76@ X76@ X76@ @ ROM_SO VGA_DEVICE 10K Pull-down to GND(no diaplay).
2
STRAP0 RAM_CFG[0] 10K
STRAP0
<33> STRAP0
<33> STRAP1
STRAP1 STRAP1 RAM_CFG[1] 10K
<33> STRAP2 STRAP2
<33> STRAP3 STRAP3 STRAP2 RAM_CFG[2] 10K
A <33> STRAP4 STRAP4 A
STRAP3 RAM_CFG[3] 10K
STRAP4 PCIE_MAX_SPEED 10K Pull-down to GND(PCIE Gen1).
1
RV171 RV172 RV173 RV174 RV175
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76@ X76@ X76@ X76@ DIS@ SMBUS_ALT_ADDR SUB_VENDOR
2
0 0x9E (Default) 0 Disable (Default)
1 0x9C (Multi-GPU usage) 1

+3VGS
VGA_DEVICE
Check SPI pin status 0
1
Non-Primary 3D Acceleration Device(Class Code 302h)(Default)
1
RV176 RV177 RV178
10K_0402_5% 10K_0402_5% 10K_0402_5% 1 Primary Display or VGA Device .
@ @ @
2
2
PCIE_MAX_SPEED
ROM_SI
<33> ROM_SI
<33> ROM_SO
ROM_SO 0 Limit to PCIE Gen1
ROM_SCLK
<33> ROM_SCLK
1 PCIE Gen 2/3 Capable
B B
1
1
ZZZ001 ZZZ001 ZZZ001
RV179 RV180 RV181
10K_0402_5% 10K_0402_5% 10K_0402_5%
DIS@ DIS@ DIS@
2
SAM@ MIC@ HY@

1G SAMSUNG 1G MICRON 1G HYNIX
X7654132L21 X7654132L23 X7654132L22
ROM CFG setup

GPU Project VRAM size CH Description Compal VRAM P/N VRAM description [3...0] RAM_CFG R P/N
128M(X16) CHA DDR3 Hynix 128Mx16 1.5V SA00006H400 H5TC2G63FFR-11C 1000MHz 1100 RV171+RV172+RV167+RV166
ZSO40
ZSO56 128M(X16) CHA DDR3 Micron 128Mx16 1.5V SA000067500 MT41J128M16JT-093G:K 1000MHz 0001 RV164+RV172+RV173+RV174
N15V-GM (23x23) 64bit
(One CH single rank) 128M(X16) CHA DDR3 Samsung 128Mx16 1.5V SA000068U40 K4W2G1646Q-BC1A 1000MHz 1110 RV165+RV166+RV167+RV171
#9/5 RAM_CFG follow RVL‐06891‐001 table 1.

Dule Rank layout with single Rank population. USER Straps
User[3:0]
C 1000-1100 Customer defined C
D D

Title
TH IS S H E E T O F E N G IN E E R IN G D R A W IN G IS TH E P R O P R IE TA R Y P R O P E R T Y O F C O M P A L E L E C TR O N IC S , IN C . A N D C O N TA IN S CONFIDENTIAL N15V-GM MISC
Custom 1.0
Date:
LA-B972P
1 2 3 4 5
A B C D E
<MV>Remove R563, delete net +5VS_IN ,4/10.
+5VS
M
10U_0603_6.3V6
M
22U_0805_6.3V6
1 1
C575
CC56
+3VALW +5VALW
2 2 @
Q21
1 14 <MV>Add 22UF for RF suggestion ,4/10.
2 VIN1 VOUT1 13
+5VALW VIN1 VOUT1
SUSP# 3 12 C554 1 2 100P_0402_50V8J
ON1 CT1 SYSON# SUSP
1 1
4 11
VBIAS GND
3
Q18A Q18B
SUSP# 5 10 C557 1 2 680P_0402_50V7K DMN66D0LDW-7_SOT363-6
ON2 CT2 DMN66D0LDW-7_SOT363-6
6 9 SYSON 2 5 SUSP#
7 VIN2 VOUT2 8 <30,48> SYSON SUSP# <30,48,49,52,55>
VIN2 VOUT2
4
15
GPAD
+3VS
TPS22966DPUR_SON14_2X3-D
1
M
10U_0603_6.3V6
C570
2
<MV>Remove R564, delete net +3VS_IN ,4/10.
+5VALW
RPH16
SYSON 8 1
SUSP 7 2
SYSON# 6 3
SUSP# 5 4
+1.05V TO +1.05VS
100K_0804_8P4R_5%
J1 need to short +1.05VS
+1.05V
J1
1 2
2 1 2 2
AO4430L JUMP_43X79
VGS Max=+/- 20V @
VGS(Th) max=2.5V
Rds Max=5.5m @VGS=10V

Rds Max=7.5m @VGS=4.5V
+V1.05A +V1.05DX_MODPHY
+1.05V +1.05VS_MODPHY
short@ R570 1 20_0805_5%
CPU +V1.05DX_MODPHY
Max Rdson <6m ohm
1840mA
3 3
AO4430L
VGS Max=+/- 20V
VGS(Th) max=2.5V
Rds Max=5.5m @VGS=10V
Rds Max=7.5m @VGS=4.5V
4 4

T HIS SHEET OF ENGINEERING DRAW ING IS T HE PROPRIET ARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIALSize Document Number
DC Interface
AND T RADE SECRET INFORMAT ION. T HIS SHEET MAY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COMPET ENT DIVISION OF R&D Rev
Custom
LA-B972P 0.1

A B C D E
5 4 3 2 1
NGFF and WLAN
D D
+3VS +3VS_WLAN
2
@
RL25
100K_0402_5%
2
G
1
WAKE# 1 3 MC_WAKE# MC_WAKE# <21>
<8> WAKE#
S
@
QB8
2N7002H_SOT23-3
PV# 2013.01.23 Add QB8 abd RL25 to support OBFF

PV# 2013.02.22 Unpop QB4 and RL23 for not supportOBFF
C C
B B
A A

Issued Date Title
Deciphered Date
WAKE and RST-1
Rev
Custom 0.1
LA-B972P
5 4 3 2 1
A B C D E
+3VALW Q30
+3V_PCH
AO3413L_SOT23-3
1 1
+3VALW 3 1
D
20mils
G
2
1
2
C590
R559
100K_0402_5% 1U_0402_6.3V6K
2
1
D
0.1U_0402_16V7K
2 1
<30> PCH_PWR_EN
G
S Q31 @
C591
3
2N7002_SOT23-3
2
2 2
3 3
4 4

DC DC Device-1
Custom 0.1
LA-B972P
A B C D E
5 4 3 2 1
PL1 EMI@ VIN

ADPIN HCB2012KF-121T50_0805
1 2
PL2 EMI@
HCB2012KF-121T50_0805
1 2 @ PR2
0_0402_5%
@ PJP1 1 2ACIN_LED
<30> AC_LED#
1000P_0402_50V7
ACES_59012-0080N-002
100P_0402_50V8
100P_0402_50V8
1000P_0402_50V7
2 1
2 1
1
EMI@ PC2
EMI@ PC4
EMI@ PC1
EMI@ PC3
D D
4 3
4 3
PR3
2
6 5 ADP_SIGNAL 100K_0402_5%
6 5
2
Charge_LED 8 7 ACIN_LED
K
8 7
PR1
10K_0402_5% PR5
ADP_SIGNAL1 2 2K_0402_5%
ADP_ID <30> 1 2 Charge_LED
<30> BAT_CHG_LED
3
1
100P_0402_50V8
1000P_0402_50V7
1
1
GLZ3.6B_LL34-
1
PR8
10K_0402_5
@ PD3
PR7
PC6
100K_0402_5%
@ PC5
2
2
2
2
%
ESD@ PD1 ESD@ PD2
J
2
K
1
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3
+5VS
C +3VALW C
1
@
<30,4> PROCHOT# PR10 @
47K_0402_1% PR11
6
@ PU1A 10K_0402_1%
2
4
PQ2A PC8 LM393DR_SO8
2
L2N7002DW1T1G_SC88-6 0.022U_0402_16V7K 2
G
-
2 1 2 1
O
1
3
100P_0402_50V8
+
1
1
1
P
@
1
PC9
@ @ PR12
PD4 PR13 8 54.9K_0402_1%
2
CD4148WN-1_1206-2 1.5M_0402_5% @
2
2
J
B/I# <30,45>
+5VS
ADP_I <30,46>
+3VALW +3VALW_EC
1
1
1
1
B B
PR17 PR26
47K_0402_1% PU1B PR18 PR25 5.9K_0402_1%
3
LM393DR_SO8 10K_0402_1% 10K_0402_1%

2
PQ2B PC12
2
L2N7002DW1T1G_SC88-6 0.022U_0402_16V7K 5
P
+ VCIN0_PH <30> VCIN1_PH <30>
12
12
5 1 2 7
O
0.1U_0402_16V7
0.1U_0402_16V7
1
1
6
100P_0402_50V8
-
1
1
1
@ PC15
@ PC16
4
PC13
PR21 PH1 PR27 @ PR28

4
PD5 PR20 100K_0402_1% 100K_0402_1%_NCP15WF104F03RC 10K_0402_1% 10K_0402_1%

2
2
CD4148WN-1_1206-2 1.5M_0402_5%
2
2
2
ECAGND<30> H_PROCHOT#_EC<30>
2
K
J
ACIN <30,45,46,8>
A A

Deciphered Date
DC Conn
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIASLize
Document Number Rev
5 4 3 2 1
5 4 3 2 1
@PJPB2
1 2
1 2
EMI@ PL3 JUMP_43X118
D HCB2012KF-121T50_0805 D
BATT++ 1 2 BATT+ BATT
PQ1 @
EMI@ PL4 SI4483ADY-T1-GE3_SO8
@PJPB1 HCB2012KF-121T50_0805 1 8
1 1 2 2 7
1
2 3 6
2
3 5
3
1
4 EMI@ PC10 EMI@ PC11 @ PR14
4
5 1000P_0402_50V7K 0.01U_0402_25V7K 470K_0402_5%
5
6 1 2
6
1 4
7
7
1
8
8
9 PR15 @ PR16 @
GND
10 470K_0402_5% 4.7K_0402_5%
GND PR19
OCTEK_BTJ-08FUAB 100_0402_5%
6 2
1 2
EC_SMB_DA1 <28,30,46>
PR22 PQ3A @
100_0402_5% L2N7002DW1T1G_SC88-6
1 2 2
EC_SMB_CK1 <28,30,46>
1
+3VL
100_0402_5
1
PR30
1
2
PR29 PR23 @
%
100K_0402_5% 220K_0402_5%
3
C 1 2 C
+3VL +3VL
2
B/I# <30,44>
5@
3
1
PQ3B
L2N7002DW1T1G_SC88-6 PR24 @
6
220K_0402_5%
PQ4A @
L2N7002DW1T1G_SC88-6
2
32
1
1
ESD@ PD6 ESD@ PD7
1
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3 PC14 @

100P_0402_50V8J 5
ACIN <30,44,46,8>
2
PQ4B @
L2N7002DW1T1G_SC88-6
4
AC_AND_CHAG <30>
Need to define "AC_AND_CHAG" signal with EC
B B
A A

Deciphered Date
BATT Conn
Document Number Rev
5 4 3 2 1
A B C D
1
2 PQ102
G 2N7002KW_SOT323-3
S
3
PR101 PR102
1 2 1 2
1M_0402_5% 3M_0402_5%
1 1
VIN P1 P2 B+
PQ101 EMI@ PL101
PQ103 PR103 PQ104
AON6414AL_DFN8-5 AON7506_DFN33-8-5 0.01_1206_1% 1.2UH_NRS4018T1R2NDGJ_2.6A_30% AON7506_DFN33-8-5
1 1 1 4 1 2 1
2 2 2
5 3 3 5 2 3 5 3
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PC104
PC105
@EMI@ PC123
1
1
2200P_0402_50V7K
0.01U_0402_50V7K
1
1
VIN
PC101
PC102
4
PC107
2
2
1 2
2
2
3
2
PC106
0.1U_0402_25V6 PR104
ACDRV1_CHG 4.12K_0603_1%
0.1U_0402_25V6
PD101 BATDRV_CHG 1 2 BATDRV1_CHG
0.1U_0402_25V6
PC109
BAS40CW_SOT323-3
1
PC108
PC110
0.047U_0402_25V7K
2
1 2
5
PR105
10_1206_1%
1
2.2_0603_5%
PD102
PR106
RB751V-40_SOD323-2 @ PR107 PQ105
0_0603_5% AON7408L_DFN8-5
2
PC111 DH_CHG 1 2 4
2
2
1U_0603_25V6K
1 2
4.12K_0603_1%
4.12K_0603_1%
1
REGN_CHG
2 BATT 2
VCC_CHG
PR108
PR109
BST_CHG
DH_CHG
PC112 PL102
LX_CHG
3
2
1
1U_0603_25V6K 4.7UH_ETQP3W4R7WFN_5.5A_20% PR110
1 2 0.01_1206_1%
LX_CHG 1 2 CHG 1 4
2
1
2 3
20
19
17
16
18
4.7_1206_5%
@EMI@ PR111
PU101
PQ106
RB551V-30_SOD323-2
VCC
BTST
REGN
HIDRV
PHASE
10U_0805_25V6K
10U_0805_25V6K
21 AON7506_DFN33-8-5
1 CSON1
1 CSOP1
PAD
1
0.1U_0402_25V6
0.1U_0402_25V6
PC114
PC115
1
1
1SNB_CHG 2
ACN_CHG 1 15 DL_CHG 4
PD103
ACN LODRV
PC113
PC116
2
ACP_CHG 2 14 PR112
680P_0603_50V8J
GND
2
ACP
@EMI@ PC117
0_0603_1%
3
2
1
2
BQ24738RGRR_QFN20_3P5X3P5 1 2 CSOP1
CMSRC_CHG 3 13 SRP_CHG
CMSRC SRP
2
PR113 PC118
ACDRV_CHG 4 12 SRN_CHG 0_0603_5% 0.1U_0603_16V7K
ACDRV SRN
2
PR114 1 2 CSON1
10K_0402_1%
+3VL 1 2 5 11 BATDRV_CHG
ACPRES ACDET BATDRV
IOUT
SDA
SCL
ILIM
<30,44,45,8> ACIN
7
10
ACDET_CHG 6
IOUT_CHG
ILIM_CHG
3 3
PR115
357K_0402_1% +3VL
VIN 1 2
0.01U_0402_25V7K
100K_0402_1%
1
422K_0402_1%
PC119
PR116
1
PR117
1
2
2
2
Vin Dectector
EC_SMB_CK1 <28,30,45>
Min. Typ Max.
0.1U_0402_25V6
66.5K_0402_1%
H-->L 17.23V
1
PC120
PR118
1
L-->H 17.63V EC_SMB_DA1 <28,30,45>

@ PR119
2
0_0402_5%
2
ILIM and external DPM 1 2 ADP_I <30,44>

1
3.61A PC121 @ PC122

100P_0402_50V8J 0.1U_0402_10V7K
2
4
locate the RC Near EC chip 4

CHARGER
Custom 0.4
LA‐A992P
Date: Sheet 46 of 55
A B C D
A B C D
PR302
165K_0402_1%
1 2
PR303
56K_0402_1%
1 1 2 1
PR304
@PC302 143K_0402_1%
100P_0402_50V8J 1 2
1 2
PR301 PR305
14K_0402_1% 30K_0402_1%
1 2 1 2
B+ 3/5V_B+ 3/5V_B+
EMI@ PL301
HCB2012KF-121T50_0805
1 2 +3VALW PR306 PR307
20K_0402_1% 19.1K_0402_1%
2200P_0402_50V7K
1 2 1 2
ENTRIP_3V
ENTRIP_5V
10U_0805_25V6K
10U_0805_25V6K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
TON_35V
PC303
PC307
@EMI@ PC318
1
1
1
PR318
PC304
PC308
FB_3V
FB_5V
10K_0402_1%
2
2
2
@
2
@
<8> SPOK
5
PQ301
TON
FB2
FB1
ENTRIP2
ENTRIP1
AON7408L_DFN8-5 21
PC305 6 PAD
PR309
0.1U_0402_10V7K PGOOD 20
2.2_0402_1% PR310 PC306
4 1 2 BST1_3V 1 2 BYP1
2.2_0402_1% 0.1U_0402_10V7K
BST_3V 7 1 2 BST1_5V 1 2 4
BOOT2 19 BST_5V
BOOT1
2
PQ302 2
DH_3V 8 AON7408L_DFN8-5
1
2
3
PL303 UGATE2 18 DH_5V
UGATE1
3
2
1
3.3UH_PCMB063T-3R3MS_6.5A_20% PL302
1 2 LX_3V 9 2.2UH_ETQP3W2R2WFN_8.5A_20%
+3VALWP PHASE2 17 LX_5V 1 2
PHASE1 +5VALWP
1
4.7_1206_5%
@EMI@ PR311
1
LG_3V 10
4.7_1206_5%
@EMI@ PR312
LGATE2
5
16 LG_5V
ENLDO
LGATE1
5
LDO5
LDO3
1
220U_C6_6.3V_M_R15
ENM
VIN
PQ303
+ AON7506_DFN33-8-5
PC316
220U_C6_6.3V_M_R15
1 SNUB_3V 2
PU301
+
11
12
13
14
15
1 SNUB_5V 2
4 RT8243AZQW_WQFN20_3X3
PC317
AON7506_DFN33-8-5
2 4
PQ304
+5VLP
+3VLP
680P_0603_50V8J
PR313 2
@EMI@ PC311
680P_0603_50V8J
+3VLP
@EMI@ PC312
499K_0402_1%
1
2
3
1 2 @ PJ301
3/5V_B+
3
2
1
JUMP_43X39
2
1 2
100K_0402_1%
1U_0603_10V6K
0.1U_0603_25V7K
1 2 +3VL
2
1
PC314
PC313
PR314
1
1
(100mA,40mils ,Via NO.= 2)
1
PC310
2
4.7U_0603_10V6K
2
PR315
2.2K_0402_1%
3
1 2 3
<30> EC_ON
@ PR316 @ PJ304
0_0402_5% JUMP_43X39
1 2 1 2
1 +VL
<30> MAINPWON 2
4.7U_0603_6.3V6K
(100mA,40mils ,Via NO.= 2)
1
@ PC315
1
1
@ PR317 PC309
100K_0402_5% 4.7U_0603_10V6K
2
2
2
@PJ302
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118
@ PJ303
1 2
+5VALWP 1 2 +5VALW
JUMP_43X118
4 4

3VALW/5VALW
Custom 0.4
LA‐A992P
Date: Sheet 47 of 55
A B C D
5 4 3 2 1
EMI@
PLM1
HCB2012KF-121T50_0805 PCM2 PRM1
B+ 1 2 B+_DDR 0.22U_0402_10V6K 2.2_0402_1%
1 2 BST_DDR-1 1 2
D D
1
@EMI@
PCM13 PCM1 PCM3
2200P_0402_50V7K 10U_0805_25V6K 4.7U_0805_25V6-K
+1.35V_VDDQP
2
2
+0.6V_0.675VSP
BST_DDR
DH_DDR
LX_DDR
10U_0805_6.3V6
10U_0805_6.3V6
1
1
PCM4
PCM5
4
PQM1
16
17
18
19
20
2
AON7408L_DFN8-5
BOOT
VTT
VLDOIN
UGATE
PHASE
1
2
3
21
K
PAD
PLM2 DL_DDR 15 1
1.5UH_PCMC063T-1R5MN_9A_20% LGATE VTTGND
1 2
+1.35V_VDDQP 14
PGND VTTSNS
2
1
5
PRM3
@EMI@ 13.3K_0402_1%
PRM2 1 2 CS_DDR 13 PUM1 3
CS GND
4.7_1206_5% RT8207PGQW_WQFN20_3X3
2
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
4 12 4 VTTREF_DDRT
+5VALW VDDP VTTREF
1
1
PCM25
PCM24
PCM23
PCM22
PCM21
PCM26
C PQM2 PRM4 C
1SNB_DDR
AON7506_DFN33-8-5 5.1_0603_5%
1 2 VDD_DDR 11 5 +1.35V_VDDQP
+5VALW
2
VDD VDDQ
2
PGOOD
1
2
3
1
TON
M
@EMI@ PCM8 PCM9 PCM10
FB
S5
S3
PCM7 1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K
2
680P_0603_50V7K
2
6
10
FB_DDR
S5_DDR
S3_DDR
TON_DDR
PRM5
8.06K_0402_1%
1 2 +1.35V_VDDQP
1
PRM8
10K_0402_1%
2
PRM6
432K_0402_1%
B+_DDR 1 2
@ PRM9 @PJPM2
B 0_0402_5% 1 B
2
<30,40> SYSON
1 2 +1.35V_VDDQP 1 2 +1.35V_VDDQ
JUMP_43X118
@ PRM11
0_0402_5%
1 2 @ PJPM1
<30,40,49,52,55> SUSP#
JUMP_43X39
1 2
+0.6V_0.675VSP 1 2 +0.6V_0.675VS
1
@ @
PCM11 PCM12
0.1U_0402_10V7K 0.1U_0402_10V7K
2
A A

Title
1.35V/0.675VS
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CONTAINS Custom 0.4
LA-B972P
5 4 3 2 1
5 4 3 2 1
D D
EN pin don't floating

If have pull down resistor at HW side, pls delete PR2
@ PRH1
0_0402_5%
1 2
SUSP# <30,40,48,52,55>
1
PRH2 @ PCH1
1M_0402_1% 0.22U_0402_10V6K
2
2
@EMI@ @EMI@
PRH3 PCH2
EMI@ 4.7_1206_5% 680P_0603_50V7K
PLH1 PUH1 1 2 SNB_1.05V 1 2
HCB2012KF-121T50_0805 SY8206DQNC_QFN10_3X3
+1.05VSP
B+ 1 2 B+_1.05V 8
IN EN
1 @PRH4
0_0603_5%
PCH3
0.1U_0603_25V7K
+1.05VS
2200P_0402_50V7
10U_0805_25V6
10U_0805_25V6
6 BST_1.05V1 2 BST_1.05Vn1 2 PLH2 @ PJH1
EMI@ PCH4
BS
1
1
1UH_PCMB063T-1R0MS_12A_20% JUMP_43X118
PCH5
PCH6 9 10 LX_1.05V 1 2 1 2
GND LX 1 2
2
47U_0805_6.3V6
47U_0805_6.3V6
1
22U_0805_6.3VA
22U_0805_6.3VA
C C
330P_0402_50V7
1
1
K
4 FB_1.05V
FB
K
PCH7
PRH5
PCH8
PCH9
PCH10
PCH11
PRH6 ILMT_1.05V 3 7 100K_0402_1%
ILMT BYP +3VALW
2
10K_0402_5%
2
4.7U_0603_6.3V6
+3VS 1 2 2
PG LDO
5 LDO_3V
4.7U_0603_6.3V6
M
PCH13
M
1
PCH12
K
2
1
2
PRH7
K
133K_0402_1%
K
<30> +1.05V_VS_PG_PWR
2
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15
continuous 6A
peak 12A
+3VALW
1
PRH8 @
B B
0_0402_5%
2
ILMT_1.05V
1
PRH9 @0@
0_0402_5%
2
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
A A

Deciphered Date
1.05V
Rev
5 4 3 2 1
5 4 3 2 1
100K_0402_1%_NCP15WF104F03RC
VREF
4700P_0402_16V7K
@ PRZ1 EMI@ PLZ1
332K_0402_1%
100K_0402_1%
680K_0402_1%
10K_0402_1% HCB2012KF-121T50_0805
9.31K_0402_1%
1
1
CPU_B+
PHZ1
1 2
B+
1
PCZ1
PRZ2
PRZ3
PRZ4
PRZ5
10U_0805_25V6
10U_0805_25V6
10U_0805_25V6
10U_0805_25V6
2
1 1
100U_25V_
33U_25V_
2
2
+ +
1
@
PCZ8
PCZ5
PCZ10
PCZ11
PCZ6
PCZ7
0.1U_0402_25V
PCZ
4.7U_0805_25V6-
2
2
1
D D
68P_0402_50V8J
PCZ4
PRZ6
M
K EMI@ PCZ3
2200P_0402_50V7
2
2
2
M
2@ 2
6 EMI@
39K_0402_1% @ @ @
K
PCZ2
.001U_0402_50V7-M
1
1
1
9.09K_0402_1
1
39K_0402_1%
150K_0402_1%
100K_0402_1%
150K_0402_1%
2
RF@
PCZ12
PRZ8
PRZ7
PRZ9
PRZ10
PRZ11
K
9
2
2
2
%
B-RAM
PRZ12 SLEWA EMI@ EMI@
OCP-I
10K_0402_1% F-IMAX PCZ13 PRZ13
CPU_B+ 1 2 680P_0402_50V7K 4.7_1206_5%
O-USR 1 2 1 2
CPU_B+
16
15
14
13
12
11
10
9
PUZ1 PLZ2
9
0.15UH_ETQP4LR15AFM_29A_20%
IMON
SLEWA
OCP-I
VBAT
F-IMAX
O-USR
B-RAMP
THERM
PRZ14 5 4 1 4
2.2_0402_1% VIN PGND2 VSW +VCC_CORE
CSP1 17 8 1 2 6 3 2 3
CSP1 VR_ON VR12.5_VR_ON <11> BOOT_R PGND1 +5VS
CSN1 18 7 SKIP 1 2 7 BOOT VDD 2 CSN1
CSN1 SKIP#
10K_0402_1%_TSM0A103F34D1RZ
PRZ15 CSN2 19 6 PWM1 PCZ14 8 1
PWM
0.22U_0402_10V6
0.15U_0402_10V6
CSN2 PWM1 SKIP#
1
2
3K_0402_1
C 0_0402_5% .1U_0402_16V7K @ C
1 2 CSP2 PWM2 PUZ2 PCZ15
PRZ17
20 5 PRZ16
CSP2 PWM2 CSD97374CQ4M_SON8_3P5X4P5 0_0402_5% 1U_0603_10V6K
1
12.1K_0402_1
21 TPS51624RSM_QFN32_4X4 4 PWM1
+3VS
%
CSP3 PWM3
1
PRZ18
PCZ16
PCZ17
1 2
1
@ PRZ19 22 3 VGATE <11>
0_0402_5% CSN3 PGOOD SKIP
K
2
2
1 2 GFB 23 2 @
<13> VSSSENSE
2
GFB VDD
%
VR_HOT#
VFB VR_SVID_DAT
ALERT#
1 2
DROOP
<11> VCCSENSE 24 1
VFB VDIO
1
COMP
10K_0402_1
PHZ2
VREF
PRZ23
VCLK
GND
1_0402_5
PAD
2
V5A
0_0402_5% 2.43K_0402_1%
PRZ22
PRZ21
@ PRZ20 1 2 CSP1
%
30
31
25
26
27
28
29
33
1
PCZ18
%
VR_SVID_ALRT# 32
NTC
2
1U_0402_6.3V6K
B value=3435 K
2
VR_SVID_CLK
@PCZ19
100P_0402_50V8J
VR_HOT#
1 2 PRZ24 @EMI@ @EMI@

4.87K_0402_1% +3VS PCZ20 PRZ26
PRZ25 1 2 680P_0402_50V7K 4.7_1206_5%
10K_0402_1% 1 2 1 2
1 2 VREF
PRZ27 PCZ21 CPU_B+

1
4.87K_0402_1% 4700P_0402_25V7K @PLZ3
9
1 2 1 2 PCZ22 0.15UH_ETQP4LR15AFM_29A_20%
0.33U_0402_10V6K @ PRZ28 5 4 1 4
VIN PGND2 VSW +VCC_CORE
2
B 2.2_0402_1% B
1 2 6 3 2 3
PRZ29
BOOT_R PGND1 +5VS
10_0603_1% 1 2 7 BOOT VDD 2 CSN2
1 2
+5VS +1.05VS_VCCST
10K_0402_1%_TSM0A103F34D1RZ
@PCZ23 8 1
PWM
0.22U_0402_10V6
0.15U_0402_10V6
SKIP#
1
1
2.43K_0402_1
.1U_0402_16V7K @ @
@ PUZ3
PRZ31
PCZ24 PRZ30 PCZ25
1U_0603_10V6K CSD97374CQ4M_SON8_3P5X4P5 0_0402_5% 1U_0603_10V6K
2
1
36K_0402_1
PWM2
PRZ32
1
1
@
PCZ27
PCZ28
PHZ3
54.9_0402_1
1 2
130_0402_1
1
%
SKIP
PRZ34
PRZ33
PCZ26 @
K
2
2
.1U_0402_16V7K
%
@ @ @
2
2
1
2
%
%
@ PRZ35
2
VR_SVID_CLK 1.82K_0402_1%
<11> VR_SVID_CLK 1 2 CSP2
<11> VR_SVID_ALRT# VR_SVID_ALRT#
<11> VR_SVID_DAT VR_SVID_DAT
<30> VR_HOT# VR_HOT#

1
@ PCZ29
47P_0402_50V8J
2
A A

Deciphered Date
CPU_CORE
Document Number Rev
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
220U_D2SX_2VY_R9M
D 1 D
1 1 1 1 1 +
1
1
PCZ50
PCZ51
PCZ52
PCZ53
PCZ54
PCZ55
PCZ56
PCZ57
PCZ58
PCZ59
PCZ70
2
2
@ 2@ 2@ 2@ 2@ @ @ @ 2 2
M
M
acoustic noise
22U_0603_6.3V6
2.2U_0402_10V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
22U_0603_6.3V6
1 1 1 1
1
1
PCZ60
PCZ61
PCZ62
PCZ63
PCZ64
PCZ65
PCZ66
PCZ67
PCZ68
PCZ69
2
2
2 2 2@ @ @ @ 2
M
M
C
acoustic noise C
B B
A A

Deciphered Date
PROCESSOR DECOUPLING
Document Number Rev
5 4 3 2 1
A B C D
@UMA@
PR1502
0_0402_5%
1 2
SUSP# <30,40,48,49,55>
1
1
1 @UMA@ UMA@ 1
PC1502 PR1503
.1U_0402_16V7K 1M_0402_5%
2
UMA@
2
PU1501
9
PGND 8
FB_1.5V 1
FB SGND +1.5VSP +1.5VS
@ UMA@ @
PJ1501 2 7 EN_1.5V PL1501 PJ1502
JUMP_43X79 PG EN 1UH_PH041H-1R0MS_3.8A_20% JUMP_43X79
+3VALW 1 2 VIN_1.5V 3 6 LX_1.5V 1 2 1 2
1 2 IN LX 1 2
4 5
PGND NC
1
UMA@
1
PC1501 @EMIUMA@ UMA@ UMA@ UMA@ UMA@
22U_0805_6.3VAM SY8003DFC_DFN8_2X2 PR1504 PR1505 PC1503 PC1504 PC1505
2
4.7_0603_5% 30.1K_0402_1% 68P_0402_50V8J 22U_0805_6.3VAM 22U_0805_6.3VAM
2
2
2
1
1
@EMIUMA@ UMA@
PC1506 PR1506
680P_0402_50V7K 20K_0402_1%
2
continuous 3A
2
2 2
3 3
4 4

Deciphered Date
1.5VS
Rev
A B C D
5 4 3 2 1
D D
@VGA@
PRV1
1K_0402_5%
1 2 +3VGS
@VGA@
PRV2
0_0402_5%
1 2 NVVDD_PWM_VID <32>
GPU_B+
1
VGA@
Operation phase Number PSI Voltage setting
1
PCV1 Rref1
1U_0402_6.3V6K VGA@ @VGA@ PRV26
2
PRV3 1K_0402_5% 1 phase with DEM 0V to 0.8V EMIVGA@

7.5K_0402_1% 1 2 +3VGS PLV1
C @VGA@ 1 phase with CCM 1.2V to 1.8V HCB2012KF-121T50_0805 B+ C
2
@VGA@ VGA@ PRV6 PSI Pull high on HW side 1 2
PRV4 PRV5 0_0402_5% Active phase with CCM 2.4V to 5.5V
2200P_0402_50V7
1 2
100U_25V_M
0_0402_5% 27K_0402_1% 1
10U_0805_25V6
10U_0805_25V6
1 2 1 2 NVVDD_PSI <32>
VGA@ PCV4
VGA@ PCV6
EMIVGA@ PCV3
Rrefadj @VGA@ PRV28 +
VGA@ PCV19
Rboot
5
10K_0402_5% @VGA@ PRV27
2 1
2 1
2 1
VGA@ 1 2 1K_0402_5%
PCV8 1 2 @VGA@ 2
+3VGS
@VGA@ 5600P_0402_50V7K PRV10
K
PCV7 C VGA@ PRV9 Pull high on HW side 0_0603_5%
0.01U_0402_16V7K 1K_0402_5% U2_UGATE1 1 2 4
12 1 2 VGA@ +VGA_CORE
DGPU_PWR_EN <30,35,9> PQV1
GPU_VI
GPU_FBRTN
VGA@ VGA@ SIR472DP-T1-GE3_POWERPAK8-5 EDP-Continuous 33.5A
Rref2 PRV7 PCV5 EDP-Peak 51.5A
3
2
1
VGA@ VGA@ 2.2_0603_5% 0.22U_0603_25V7K
1
OCP 66A
GPU_REFADJ
PRV8 PRV11 @VGA@ U2_BOOT1 1 2 12
U2_BOOT
U2_UGATE1
6.2K_0402_1% 1.74K_0402_1% PCV9
GPU_PSI
1 2 1 2 0.1U_0402_25V6
GPU_E
2
Reserve Location VGA@ PLV2
1
+VGA_CORE
0.22UH_PCME064T-R22MS_28A_20%
N
U2_PHASE1 1 2
1
@EMIVGA@
6
1
VGA@ PRV14
390U_2.5V_M
390U_2.5V_M
1 1
VGA@ PRV13 VGA@ 4.7_1206_5%
BOOT1
EN
VID
REFADJ
PSI
+ +
UGATE
PRV12 PQV2
VGA@ PCV12
VGA@ PCV10
340K_0402_1%
100_0402_1% GPU_B+ 1 2 MDU1511RH_POWERDFN56-8-5
1SNB_VGA12
1 2 Rton GPU_REFIN 7 24 U2_PHASE1 U2_LGATE1 4
1
1 REFIN PHASE1 2 2
@VGA@
PCV14 GPU_VREF 8 23 U2_LGATE1
VREF LGATE1
1
@VGA@ 0.01UF_0402_25V7K
PRV16 2 GPU_TON 9 22 U2_PWM3 U2_PWM3 VGA@
GND/PWM3
3
2
1
<35> VSSSENSE_VGA TON VGA@ @EMIVGA@
0_0402_5% PRV15
1 2 GPU_FBRTN 10 PUV1 21 12.7K_0402_1% PCV15
RGND
RT8813AGQW_WQFN24_4X4 PVCC Rocset 680P_0603_50V7K
2
B B
GPU_FB 11 20 U2_LGATE2
TALERT/ISEN2
VSNS LAGTE2
@VGA@
Co-Lay Co-Lay
TSNS/ISEN3
VCC/ISNE1
@VGA@ PCV16 GPU_COMP 12 19 U2_PHASE2

SS PHASE2
21
PGOOD
PRV17 47P_0402_50V8J
UGATE
BOOT2
0_0402_5% 1
GND
1 2 @VGA@ GPU_B+
2
PCV17
<34> VCCSENSE_VGA 0.01U_0402_16V7K
25
13
14
15
16
17
18
2200P_0402_50V7
2 Css
10U_0805_25V6
10U_0805_25V6
VGA@ PCV21
VGA@ PCV22
EMIVGA@ PCV20
VGA@
1
1
GPU_DSBL/ISEN
PRV18
GPU_TSNS/ISEN3
5
GPU_HOT#
100_0402_1%
2 1
2 1
1 2
GPU_PGOOD1
U2_UGATE2
2
@VGA@
U2_BOOT2
+VGA_CORE
PRV20
K
0_0603_5%
U2_UGATE2 1 2 4
VGA@
PQV3
VGA@ VGA@ SIR472DP-T1-GE3_POWERPAK8-5
PRV19 PCV18
3
2
1
2.2_0603_5% 0.22U_0603_25V7K
GPU_VREF U2_BOOT21 2 1 2
+3VGS
1
VGA@ VGA@ PLV3 +VGA_CORE

PRV21 0.22UH_PCME064T-R22MS_28A_20%
1. VSNS Soft-Start time (Internal) is 0.7ms (PCV17 un-pop)
1
18.7K_0402_1% U2_PHASE2 1 2
Tss=(Css*Vrefin)/Iss+2.3ms VGA@
2
1
PRV22
=0.01U*0.9V/5uA+2.3ms=4.1ms (PCV17 pop) 10K_0402_1% @EMIVGA@
390U_2.5V_M
1
1
5
PRV23
2
1
4.7_1206_5% +
2. Switching frequency setting: VGA@ VGA@
VGA@ PCV25
PCV23 PHV1 VGA@
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=448Khz 1U_0402_6.3V6K 470K_0402_5%_TSM0B474J4702RE DGPU_PWROK <35> +5VS PQV4
2
MDU1511RH_POWERDFN56-8-5 2
2
2 1SNB_VGA22
A U2_LGATE2 4 A
3. Thermal monitoring: VGA@
PRV24
(VGPU_VREF-VTSNS)/PRV21=VTSNS/Rth 2.2_0603_5% @EMIVGA@
1 2 PCV26
3
2
1
680P_0603_50V7K
T_min T_typical T_max VGA@
PRV25
Co-Lay
1
100K_0402_1% VGA@
PRV21=18.7K 96.73C 100C 103.1C +3VS 1 2 PCV27
1U_0402_6.3V6K Security Classification Compal Secret Data Compal Electronics, Inc.
2

PRV21=13K 106.38C 110C 113.4C <30> GPU_HOT# VGA_CORE
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
S ize Document Number Rev
0.4
LA-B972P
5 4 3 2 1
A B C D E
+VGA_CORE
PLACE UNDER GPU
1 1
1
VGA@ VGA@ VGA@ VGA@ VGA@
PCV51 PCV52 PCV53 PCV54 PCV55
4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
2
1
1
4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
2
2
2 2
1
1
VGA@ VGA@ VGA@ VGA@
PCV61 PCV62 PCV63 PCV64
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
2
PLACE NEAR GPU
1
1
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
2
2
3 3
1
VGA@ VGA@
PCV70 PCV71
22U_0603_6.3V6M 47U_0805_6.3V6M
2
4 4

VGA CHIP DECOUPLING
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , INC. N E I T H E R T H I S S H E E T N O R T H E I N F O R M A T I O N IT C O N T A I N S B LA-B972P 0.4
A B C D E
5 4 3 2 1
@VGA@
PRW1
0_0402_5%
1 2
SUSP# <30,40,48,49,52>
1
D D
1
VGA@ @VGA@
PRW2 PCW1
1M_0402_1% 0.01UF_0402_25V7K
2
2
@EMIVGA@ @EMIVGA@
PRW3 PCW2
EMIVGA@ 4.7_1206_5% 680P_0603_50V7K
PLW1
HCB2012KF-121T50_0805
VGA@
PUW1 @VGA@ VGA@
1 2 SNB_VRAMPWR 1 2
+1.5VDIS +1.5VS
B+ 1 2 B+_VRAMPWR 8
IN EN
1 EN_VRAMPWR PRW4
0_0603_5%
PCW5
0.1U_0603_25V7K
2200P_0402_50V7K
VGA@ @
4.7U_0805_25V6-
4.7U_0805_25V6-
6 BST_VRAMPWR 1 2 BST_VRAMPWR1n 2 PLW2 PJW1
VGA@ PCW4
VGA@ PCW6
EMIVGA@ PCW3
BS
1
1.5UH_PCMC063T-1R5MN_9A_20% JUMP_43X118
9 10 LX_VRAMPWR 1 2 1 2
GND LX 1 2
2
1
4 FB_VRAMPWR VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
K
FB
PRW5 PCW7 PCW8 PCW9 PCW10 PCW11
3 7 30.1K_0402_1% 330P_0402_50V7K 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
ILMT BYP +3VALW
2
2
2 5
PG LDO
1
VGA@
1
SY8206DQNC_QFN10_3X3 VGA@ PCW12
PCW13 4.7U_0603_6.3V6K
1
4.7U_0603_6.3V6K
2
C VGA@ C
PRW6
19.6K_0402_1%
2
continuous 6A
peak 12A
B B
A A

Title
VRAM Power
Rev
Custom 0.4
LA-B972P
5 4 3 2 1

ESQUEMA ELECTRICO HP Pavilion 15-R Compal LA-B972P ASO56 Rev 1.0

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ESQUEMA ELECTRICO HP Pavilion 15-R Compal LA-B972P ASO56 Rev 1.0

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Available Formats

A B C D E

Intel ULV Processor with DDRIIIL

Security Classification Compal Secret Data Compal Electronics, Inc.

Model Name : Haswell

PCI-E Card reader Lane 4 PCI-E Port 1

Int.KBD ENE KB9012 LPC

+3VALWP Jumper +3VALW

BATDRV +1.35V_VDDQP Jumper +1.35V_VDDQ

RT8813 DIS only

SY8208D DIS only

Security Classification Compal Secret Data Compal Electronics, Inc.

+5VALW EC_ON X 0 USB 2.0/3.0(left side) USB 2.0/3.0(left side)

Security Classification Compal Secret Data Compal Electronics, Inc.

UCPU1A HASW EL L _ MCP_ E L CC97~CC102 must closed to connector not CPU

<20> PCH_DPB_N2 C54 C45

RC11 2 1 10K_0402_5% H_CPUPWRGD_R

C RC4 PROC_DETECT# D61 C

PREQ E60 XDP_TCK

Security Classification Compal Secret Data Compal Electronics, Inc.

<15> DDR_A_D[0..63] <16> DDR_B_D[0..63]

UCPU1C HASWELL_MCP_E <DDR3L>

DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D58 AK18 SB_DQ57

Security Classification Compal Secret Data Compal Electronics, Inc.

D MPHY_PW REN RC217 1 2 10K_0402_5% D

PCH_JTAG_TDI XDP_TCK_JTAGX XDP_TDI_CPU 6 7 XDP_TDI_SW ITCH

<XDP> XDP_TDI RC200 1 2 0_0201_5% XDP_TDI_SW ITCH 74AUP1G07GW _TSSOP5

R2 (also known as "Com m on will be chained to form R6,R7,R8,R9

<PCH site> J2D

CPU_XTAL24_IN CPU_XTAL24_IN <31> CPU_XTAL24_IN

remove thernal sensor 10/14

Security Classification Compal Secret Data Compal Electronics, Inc.

T83 short@ RC268 1 20_0201_5% PM_SLP_S0#_R

@ L：Disable DSW ODVREN RC255 2 1 330K_0402_5%

short@ RC114 1 2 0_0402_5% BKL_PW M_CPU_R B8 B9 PCH_DDPB_CLK 10K_0804_8P4R_5%

EC_SMI# U6 <SI>Displayport Port C Enable pin RC102 pull high +3VS

Security Classification Compal Secret Data

Security Classification Compal Secret Data

<32> PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N8 F8 AR8 USB20_N2 <24>

<32> PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N9 H10 AM15 USB20_N4 <19>

<32> PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N10 E6 AP11

<PV>PRH11 change to RPH17.

Security Classification Compal Secret Data

+1.35V_VDDQ L59 C36

VR12.6PG_MCP C59 F56

RC156 close to CPU<500mil 12 OF 19

+1.05VS +1.05VS_VCCST UC8 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Thursday, March 20, 2014 Sheet 11 of 54

+1.05VS_VCCUSB3PLL short@ 1.838A +1.05VS_VCCHSIO short@

VCCAPLL AG14 CC44 @

2.2UH_LQM2MPN2R2NG0L_30% +3V_DSW_P VCCSUS3_3 DCPSUS1 AD8

VCCCLK SUS OSCILLATOR +1.05V_AOSCSUS

+3V_PCH RC182 1 2 0_0402_5% +3V_DSW_P Non Deep S3 RC182-->SMT Total 1.5VS=3mA

2.2UH_LQM2MPN2R2NG0L_30% Total 3V_PCH=99mA

Security Classification Compal Secret Data

A11 AJ35 UCPU1O HASW ELL_MCP_E

Security Classification Compal Secret Data Compal Electronics, Inc.

UCPU1S HASW ELL_MCP_E

PAD @ T59 CFG0 AC60 AV63

Security Classification Compal Secret Data Compal Electronics, Inc.

+V_VDDR_REFA_DQ +1.35V_VDDQ +1.35V_VDDQ

DDR_A_D13 5 VSS2 DQ4 6 DDR_A_D12

DDR_A_D20 149 DQ40 DQ45 150