Mansoura University

Faculty of Computers and Information

Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

LABORATORY MANUAL
Microprocessor
 Mansoura University
Faculty of Computers and Information
Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

LAB 03:
Memory access modes

LAB Objectives
The goal of this lab is to be able to recognize types of memory addressing modes. After completing
this lab students should be able to understand, use and differentiate between:
 Register addressing mode.
 Immediate addressing mode.
 Memory addressing mode.
 Relative addressing mode.
 Implied addressing mode.
LAB Content
Memory access definition
Addressing mode of 8086 processor.
The way of specifying data to be operated by an instruction is known as addressing
modes.
Access memory is the way the processor getting the data from the memory for
operands in the arithmetic and logic operation.
This can be an instruction, an operand, register, memory location, input and output
ports.
We can use assembly language on 8086 to demonstrate addressing different modes.
In assembly instruction is the command that perform a specific operation or action.
It consisted of operation code and one or more operands, up two operands.
Move instruction in assembly is one of most used.
Instruction to preform operation and access memory.
MOV destination, source; used to move data between sources to destination.

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 Mansoura University
Faculty of Computers and Information
Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

Source and destination:

Source of data can be:
Immediate data.
Register.
Memory location.
Destination of data can be:
Register.
Memory location.
Types of memory addressing modes:
Register addressing mode.
Immediate addressing mode.
Memory addressing mode.
Relative addressing mode.
Implied addressing mode.
Register addressing mode:
In this type of addressing mode both the operands are registers.
MOV AX, BX (16-bit transfer).
MOV AL, BL (8-bit transfer).
Immediate addressing mode
Data is part of the instruction itself.
Data consisted of 8-bit or 16-bit is specific in the instruction itself.
Examples:
Mov Al, 33H
Mov Bx, 0513H
Mov Ax, 0005H

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 Mansoura University
Faculty of Computers and Information
Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

Data is accessing and act on directly from the instruction and not from another address
or another registers.
Memory addressing mode:
Memory address is one of the commands operands. To access memory, we must
identify the physical address, we must use a segment register. By default, DS register.
A 16-bits effective address can be defined using different ways:
Direct memory addressing:
Effective address is directly defined in the instructions, displacement amount is
defined directly in the instructions.
Format:
Mov Register, [Displacement]
Examples:
Mov Bx, [5012]
Mov Ax, [0500]
Physical address is defines using 20-bit address using the DS register with the
displacement (offset value) [5012] and [0500].
Register Indirect addressing:
Effective address is in one of the base registers [BX, BP] or In one of the index
registers [SI, DI].
Format:
Mov register, [base or index registers]
Example:
Mov Cx, [Bx]
DS = 1000h, BX=0008h
Content of 10008h memory location is copied to Cx register.

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 Mansoura University
Faculty of Computers and Information
Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

It was also 16–bit µP.

It was created as a cheaper version of Intel’s 8086.
It was a 16–bit processor with an 8–bit external bus.
INTEL 80186 & 80188:
Introduced in 1982.
They were 16–bit µPs.
Clock speed was 6 MHz.
INTEL 80286:
Introduced in 1982.
It was 16–bit µP.
Its clock speed was 8 MHz.
Based Addressing:
Effective address is the sum of 16-bit offset given in instruction along with 8 or 16bit
displacement.
Format:
Mov register, [base register +offset]
Example:
Mov Al, [BP+0100]
Contents of base register Bx or Bp.
Indexed addressing
Effective address is the sum of 16-bit offset given in instruction along with 8 or
16bit displacement.
Format:
Mov register ,[index register +offset]

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 Mansoura University
Faculty of Computers and Information
Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

Example:
Mov Al ,[si+0100]
Mov Ax ,[Di+3000]
Contents of base register SI or DI Introduced in 2000.
Based indexed Addressing
Effective address is sum of base register and index register.
16-bit offset given in base and index registers along with 8- or 16-bit displacement.
Format:
Mov register, [base register + source register]
Example:
Mov al, [BP + SI]
Mov Ax,[Bx + Di]
Relative addressing mode
In this the effective address is calculated with reference to instruction pointer.
Specified the operand as 8- bit signed displacement relative to pc.
Format:
JNZ + displacement
Examples:
JNZ 8H; not zero add to IP (Program Counter)
Ip=Ip+8
Implied addressing mode
In this mode, the operands are implied and are hence not specified in the instruction.
No operands are defined.
Clc
Clear carry flag

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 Mansoura University
Faculty of Computers and Information
Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

STC
This sets the carry flag.
Defining data types in 8086
Format:
data size + ptr
Byte ptr for x variable with size of 8 bits
Word ptr for y variable with size of 16 bits
Examples:
Byte ptr [BX] ; Byte access. or word ptr [BX] ; word access. Emu Assembler
supports shorter prefixes as well.
b. - for byte ptr.
w. - for word ptr.
In certain cases the assembler can calculate the data type automatically.
It was also 32–bit µP.
Mov instruction
Copies the second operand (Source) to the first operand (destination)
Source operand can be an immediate value, general purpose register, or
memory location.
Destination register can be general purpose register, or memory location.
Both operands must be the same size which can be byte or word, Types of
operands in (Mov instructions):
MOV REG, memory
MOV memory, REG
MOV REG, REG
MOV memory, immediate
MOV REG, immediate

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 Mansoura University
Faculty of Computers and Information
Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
memory: [BX], [BX+SI+7], variable
immediate: 5, -24, 3Fh, 10001101b
For segment registers only these types of MOV are supported:
MOV SREG, memory
MOV memory, SREG
MOV REG, SREG
MOV SREG, REG
SREG: DS, ES, SS, and only as second operand: CS.
REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
memory: [BX], [BX+SI+7], variable
Example:
A short program that demonstrates the use of MOV instruction:
ORG 100h; this directive required for a simple 1 segment .com program.
MOV AX, 0B800h; set AX to hexadecimal value of B800h.
MOV DS, AX; copy value of AX to DS.
MOV CL, 'A'; set CL to ASCII code of 'A', it is 41h.
MOV CH, 1101_1111b; set CH to binary value.
MOV BX, 15Eh; set BX to 15Eh.
MOV [BX], CX; copy contents of CX to memory at B800:015E.
RET; returns to operating system.

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 Mansoura University
Faculty of Computers and Information
Information Technology Department
Course: Microprocessor
Code: [IT425P]
Fourth Year

Homework 03:
Student Name:
Student ID:
Section:
Dept.:
Year:
Date:

1. Solve The Following

a. List and explain the Memory access modes.
b. List the data types in 8086 and describe their format with one example.