5 4 3 2 1

www.xinxunwei.com 400-800-9990
GA-F2A68HM-DS2 APU_VDDIO_SUS=DDR15V

APU_VTT_SUS=DDRVTT
PAGE TITLE Revision : 1.01 APU_VDDP_RUN=APU_VDDR_RUN=APU_VDDP

D 01 COVER SHEET +1.1V_RUN=FCH_VDD_11_RUN=VCC_SB D

l
02 BOM & PCB MODIFY HISTORY +3.3V_RUN=VCC3
+3.3V_ALW=3VDUAL

a
03 BLOCK DIAGRAM

ti
04 APU DDRIII MEMORY

n
05 APU CONTROL

e
06 APU UMI, GFX, GPP

i d
07 APU POWER & GND

f
n y
08 DDRIII CHANNEL A

o
C C
09 Bolton D3 UMI, PCIE, PCI, CPU, LPC

C
10 Bolton D3 ACPI, GPIO, USB, AUDIO

p
11 Bolton D3 SATA,SPI,HWM

te o
12 Bolton D3 POWER & GND

y C
13 PCIE x16 , x1

a b o t
14 PCI SLOT

g n
15 ITE 8620 , Dual-BIOS , KB/MS , HWMO

i
G Do
16 COM ,RGB ,DVI
B B

17 FAN , HWMO , F_USB , R_USB

18 ALC887-VD2 CODEC
19 ATX, FRONT PANEL
20 POWER SEQUENCE
21 VCORE (ISL62773)
22 VCORE MOS
23 DDR POWER, 5VDUAL , ERP

A 24 RTL8111G A

25 VCC_SB , APU_VDDP , VCC11_DUAL , VDDA25

Title
COVER SHEET
Size Document Number Rev
Custom GA-F2A68HM-DS2 1.01
Date: Tuesday, October 28, 2014 Sheet 1 of 25
5 4 3 2 1
 5 4 3 2 1

www.xinxunwei.com 400-800-9990
Model Name:GA-F2A68HM-DS2 Circuit or PCB layout change for next version
Version: 1.01 Date Change Item Reason
9MF278MS2-00
Component value change history P-Code: U14076-0 2014.06.23 Rev 3.11 Gerber-out
Change from F2A88XM-DS2 PCB Ver 3.11
VCORE : Remove DAQ4, DBQ4 DCQ4 (H1L1)
D D

Date Change Item Reason

Change from F2A78M-DS2 PCB Ver 3.11
2014.06.20 3.0A New BOM release PCB:3.11 Change From F2A88XM-DS2 3.11 2014.09.xx Rev 1.0 Gerber-out 1. LAN+USB30 change to LAN+USB20
1. VCORE : Remove DAQ4, DBQ4 DCQ4 (H1L1) 2. KB/MS change to KB/MS+USB20
2. FCH Change A78 3. USB30 change port (real)
4. remove 5VSB OVP
5. OR41 , OR45 0402 change to 0603 short-pad

2013.11.28 3.0B New BOM release PCB:3.11 CEC6,CEC2,CEC9,CEC1 Change Chemicon Audio cap
Add BC677 (FUSEVCC for 水水水ISSUE)
2014.10.21 Rev 1.01 Gerber-out Add BC121 for EMI USB
2014.09.15 1.0B New BOM release PCB:1.0 Change from F2A78M-DS2 PCB Ver 3.11 Add UBEC4 for 5VDUAL
1. LAN+USB30 change to LAN+USB20
2. KB/MS change to KB/MS+USB20
3. USB30 change port (real)
4. remove 5VSB OVP
5. OR41 , OR45 0402 change to 0603 short-pad
6. PX2 -->16pf & PC15&PC16 change to 20pf

Add BC677 (FUSEVCC for 水水水ISSUE)

C C
Add BC121 for EMI USB
2014.10.21 1.0B Auto BOM release PCB:1.01 Add UBEC4 for 5VDUAL

2014.10.28 1.0B P-BOM release PCB:1.01 轉P-BOM

B B

A A

Title
BOM & PCB HISTORY
Size Document Number Rev
Custom GA-F2A68HM-DS2 1.01
Date: Tuesday, October 28, 2014 Sheet 2 of 25
5 4 3 2 1
 5 4 3 2 1

www.xinxunwei.com 400-800-9990
AMD FM2/FM2+ APU
DDRIII 1066,1333, 1600, 1866, 2133 UNBUFFERED
1 X16 PCIE VIDEO I/F DDRIII DIMM1
RGB (DP1) to 8

128bit
VGA CON 11,16 1 X4 PCIE I/F WITH
D D
DX11 IGP

l
DVI(DP2) DDRIII 1066,1333, 1600, 1866, 2133 UNBUFFERED
16 DDRIII DIMM2
8

i a
DDRIII FIRST LOGICAL DIMM
Fusion D3 CORE &

t
PCIE POWER
25

n
PCIE SLOT PCIE X16
16X 13

e
DDR3 MEMORY
PCIE SLOT POWER RT8120

d
PCIE X1 PCIE X1 GIGABIT
1X 13 23

i
RTL8111G
24

f
4,5,6,7 APU POWER

n y
ISL62773 + ISL6608
21,22

o
C 4X C

PCIE

C p
ALC887-VD2
HD AUDIO I/F HD AUDIO CODEC

e o
USB-8 USB-9 USB-5 USB-4 USB-3 USB-2 USB 2.0 AMD Bolton D2H 18

t
15 15 17 17 17 17
SATA#0 SATA#1 SATA#2 SATA#3

y C
USB3.0 SATA III I/F
11 11 11 11
USB2.0

t
USB-6 USB-7

b
AZALIA
24 24

o
SATA III

a
LPC I/F

g n
USB3-1 USB3-0 USB 3.0 INT RTC

i
17 17 HW MONITOR

G Do
ACPI
4 1X PCIE I/F
B B
PCI BUS VGA Translator I/F SPI
SPI I/F
Dual-BIOS
11

PCI SLOT #1 9,10,11,12

14

M_BIOS / B_BIOS CTRL

LPC BUS

ITE LPC SIO IT8620

15

A A

COM KBD
MOUSE HW
16 15 MONITOR 15,17
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom GA-F2A68HM-DS2 1.01
Date: Wednesday, October 29, 2014 Sheet 3 of 25
5 4 3 2 1
 5 4 3 2 1

FM2R2B
MEMORY CHANNEL A
MDA[0..63] <8> www.xinxunwei.com 400-800-9990 FM2R2C
MDB[0..63] <8>
MAAA0 V27 MA_ADD0 MA_DATA0 F16 MDA0 MEMORY CHANNEL B
<8> MAAA[0..15] MAAA1 P27 MA_ADD1 MA_DATA1 G16 MDA1 MAAB0 V31 MB_ADD0 MB_DATA0 A16 MDB0
MAAA2 R25 MA_ADD2 MA_DATA2 H18 MDA2 <8> MAAB[0..15] MAAB1 N28 MB_ADD1 MB_DATA1 C16 MDB1
MAAA3 P26 MA_ADD3 MA_DATA3 F19 MDA3 MAAB2 P29 MB_ADD2 MB_DATA2 B18 MDB2
MAAA4 R24 MA_ADD4 MA_DATA4 F15 MDA4 MAAB3 N29 MB_ADD3 MB_DATA3 A19 MDB3
MAAA5 P24 MA_ADD5 MA_DATA5 H15 MDA5 MAAB4 N31 MB_ADD4 MB_DATA4 C15 MDB4
MAAA6 P23 MA_ADD6 MA_DATA6 E18 MDA6 MAAB5 M30 MB_ADD5 MB_DATA5 B15 MDB5
MAAA7 N26 MA_ADD7 MA_DATA7 F18 MDA7 MAAB6 M31 MB_ADD6 MB_DATA6 D17 MDB6
MAAA8 N23 MA_ADD8 MAAB7 M28 MB_ADD7 MB_DATA7 C18 MDB7
MAAA9 M25 MA_ADD9 MA_DATA8 G20 MDA8 MAAB8 M27 MB_ADD8
MAAA10 V24 MA_ADD10 MA_DATA9 H20 MDA9 MAAB9 L30 MB_ADD9 MB_DATA8 D20 MDB8
D MAAA11 N25 MA_ADD11 MA_DATA10 E23 MDA10 MAAB10 W 31 MB_ADD10 MB_DATA9 A20 MDB9 D
MAAA12 M24 MA_ADD12 MA_DATA11 G23 MDA11 MAAB11 L29 MB_ADD11 MB_DATA10 D22 MDB10
MAAA13 Y23 MA_ADD13 MA_DATA12 G19 MDA12 MAAB12 K28 MB_ADD12 MB_DATA11 D23 MDB11
MAAA14 MDA13 MAAB13 MDB12

l
L27 MA_ADD14 MA_DATA13 E20 AB28 MB_ADD13 MB_DATA12 C19
MAAA15 L24 MA_ADD15 MA_DATA14 F22 MDA14 MAAB14 K31 MB_ADD14 MB_DATA13 D19 MDB13
MA_DATA15 G22 MDA15 MAAB15 J31 MB_ADD15 MB_DATA14 A22 MDB14
SBAA0 W 26 C22 MDB15

a
MA_BANK0 MB_DATA15
<8> SBAA0
SBAA1 V25 MA_BANK1 MA_DATA16 F24 MDA16 SBAB0 W 29 MB_BANK0
<8> SBAA1 <8> SBAB0

ti
SBAA2 L26 MA_BANK2 MA_DATA17 H24 MDA17 SBAB1 V30 MB_BANK1 MB_DATA16 C24 MDB16
<8> SBAA2 <8> SBAB1
MA_DATA18 E27 MDA18 SBAB2 K29 MB_BANK2 MB_DATA17 B24 MDB17
<8> SBAB2
DMA0 E17 MA_DM0 MA_DATA19 F27 MDA19 MB_DATA18 B26 MDB18
DMA1 H21 MA_DM1 MA_DATA20 H23 MDA20 DMB0 D16 MB_DM0 MB_DATA19 C27 MDB19
DMA2 F25 MA_DM2 MA_DATA21 E24 MDA21 DMB1 B20 MB_DM1 MB_DATA20 A23 MDB20
DMA3 G29 MA_DM3 MA_DATA22 E26 MDA22 DMB2 A25 MB_DM2 MB_DATA21 B23 MDB21

n
DMA4 AF29 MA_DM4 MA_DATA23 H26 MDA23 DMB3 D29 MB_DM3 MB_DATA22 D26 MDB22
DMA5 AE25 MA_DM5 DMB4 AL29 MB_DM4 MB_DATA23 A26 MDB23
DMA6 AG21 MA_DM6 MA_DATA24 G28 MDA24 DMB5 AH25 MB_DM5

e
DMA7 AF17 MA_DM7 MA_DATA25 E29 MDA25 DMB6 AK21 MB_DM6 MB_DATA24 C28 MDB24
MA_DATA26 H29 MDA26 DMB7 AJ17 MB_DM7 MB_DATA25 D28 MDB25
MA_DATA27 H30 MDA27 MB_DATA26 C31 MDB26

d
DQSA0 H17 MA_DQS_H0 MA_DATA28 H27 MDA28 MB_DATA27 D31 MDB27
-DQSA0 G17 MA_DQS_L0 MA_DATA29 F28 MDA29 DQSB0 A17 MB_DQS_H0 MB_DATA28 B27 MDB28

i
DQSA1 F21 MA_DQS_H1 MA_DATA30 F31 MDA30 -DQSB0 B17 MB_DQS_L0 MB_DATA29 A28 MDB29
-DQSA1 E21 MA_DQS_L1 MA_DATA31 G31 MDA31 DQSB1 B21 MB_DQS_H1 MB_DATA30 B30 MDB30

f
DQSA2 G26 MA_DQS_H2 -DQSB1 C21 MB_DQS_L1 MB_DATA31 C30 MDB31
-DQSA2 G25 MA_DQS_L2 MA_DATA32 AD30 MDA32 DQSB2 D25 MB_DQS_H2
DQSA3 F30 MA_DQS_H3 MA_DATA33 AF30 MDA33 -DQSB2 C25 MB_DQS_L2 MB_DATA32 AJ30 MDB32
-DQSA3 E30 AG27 MDA34 DQSB3 B29 AK30 MDB33

n y
MA_DQS_L3 MA_DATA34 MB_DQS_H3 MB_DATA33
DQSA4 AE28 MA_DQS_H4 MA_DATA35 AF27 MDA35 -DQSB3 A29 MB_DQS_L3 MB_DATA34 AH28 MDB34
-DQSA4 AE29 MA_DQS_L4 MA_DATA36 AD31 MDA36 DQSB4 AJ29 MB_DQS_H4 MB_DATA35 AJ27 MDB35
DQSA5 AG24 MA_DQS_H5 MA_DATA37 AE31 MDA37 -DQSA[0..7] -DQSB4 AH29 MB_DQS_L4 MB_DATA36 AG30 MDB36

o
-DQSA[0..7] <8>
C -DQSA5 AG25 MA_DQS_L5 MA_DATA38 AG28 MDA38 DQSB5 AK25 MB_DQS_H5 MB_DATA37 AH31 MDB37 C
DQSA6 AF20 MA_DQS_H6 MA_DATA39 AD28 MDA39 DQSA[0..7] -DQSB5 AL25 MB_DQS_L5 MB_DATA38 AK28 MDB38
DQSA[0..7] <8>
-DQSA6 AF21 MA_DQS_L6 DQSB6 AJ20 MB_DQS_H6 MB_DATA39 AL28 MDB39
DQSA7 AE16 MA_DQS_H7 MA_DATA40 AF26 MDA40 DMA[0..7] -DQSB6 AJ21 MB_DQS_L6
DMA[0..7] <8>

C
-DQSA7 AD16 MA_DQS_L7 MA_DATA41 AD25 MDA41 DQSB7 AL16 MB_DQS_H7 MB_DATA40 AJ26 MDB40
AF23 MDA42 -DQSB7 AL17 AH26 MDB41

p
MA_DATA42 MB_DQS_L7 MB_DATA41
MA_DATA43 AE23 MDA43 MB_DATA42 AH23 MDB42
MA_DATA44 AD27 MDA44 -DQSB[0..7] MB_DATA43 AJ23 MDB43
-DQSB[0..7] <8>
DCLKA0 U27 AE26 MDA45 AK27 MDB44

e
MA_CLK_H0 MA_DATA45 MB_DATA44

o
<8> DCLKA0 -DCLKA0 U26 MDA46 DQSB[0..7] DCLKB0 MDB45
<8> -DCLKA0 MA_CLK_L0 MA_DATA46 AF24 DQSB[0..7] <8> <8> DCLKB0 U30 MB_CLK_H0 MB_DATA45 AL26
T23 MA_CLK_H1 MA_DATA47 AD24 MDA47 -DCLKB0 U29 MB_CLK_L0 MB_DATA46 AJ24 MDB46

t
DMB[0..7] <8> -DCLKB0
U23 MA_CLK_L1 T29 MB_CLK_H1 MB_DATA47 AK24 MDB47
DMB[0..7] <8>
T25 MA_CLK_H2 MA_DATA48 AG22 MDA48 T28 MB_CLK_L1

C
T26 MA_CLK_L2 MA_DATA49 AD21 MDA49 R31 MB_CLK_H2 MB_DATA48 AK22 MDB48

y
DCLKA3 R27 MA_CLK_H3 MA_DATA50 AE19 MDA50 T31 MB_CLK_L2 MB_DATA49 AH22 MDB49
<8> DCLKA3
-DCLKA3 R28 MA_CLK_L3 MA_DATA51 AG19 MDA51 DCLKB3 P30 MB_CLK_H3 MB_DATA50 AL19 MDB50
<8> -DCLKA3 <8> DCLKB3
MA_DATA52 AD22 MDA52 -DCLKB3 R30 MB_CLK_L3 MB_DATA51 AK19 MDB51
<8> -DCLKB3

t
CKEA0 MDA53 MDB52

b
<8> CKEA0 L23 MA_CKE0 MA_DATA53 AE22 MB_DATA52 AL23
CKEA1 K26 MA_CKE1 MA_DATA54 AE20 MDA54 CKEB0 J30 MB_CKE0 MB_DATA53 AL22 MDB53
<8> CKEA1 <8> CKEB0
MA_DATA55 AD19 MDA55 CKEB1 J28 MB_CKE1 MB_DATA54 AH20 MDB54
<8> CKEB1

o
AA24 AL20 MDB55

a
MA0_ODT0 MB_DATA55
AC27 MA0_ODT1 MA_DATA56 AG18 MDA56 AA30 MB0_ODT0
MODT_A2 AA25 MA1_ODT0 MA_DATA57 AE17 MDA57 AC30 MB0_ODT1 MB_DATA56 AJ18 MDB56
<8> MODT_A2
MODT_A3 AC26 AF15 MDA58 MODT_B2 AA31 AH17 MDB57

n
MA1_ODT1 MA_DATA58 MB1_ODT0 MB_DATA57

g
<8> MODT_A3 MDA59 <8> MODT_B2 MODT_B3 MDB58
MA_DATA59 AG15 <8> MODT_B3 AC29 MB1_ODT1 MB_DATA58 AJ15
MDA60 MDB59

i
Y27 MA0_CS_L0 MA_DATA60 AD18 MB_DATA59 AK15
AB26 MA0_CS_L1 MA_DATA61 AF18 MDA61 Y29 MB0_CS_L0 MB_DATA60 AH19 MDB60
-CSA2 W 23 MA1_CS_L0 MA_DATA62 AG16 MDA62 AB29 MB0_CS_L1 MB_DATA61 AK18 MDB61
<8> -CSA2

G Do
-CSA3 AB25 MA1_CS_L1 MA_DATA63 AD15 MDA63 -CSB2 Y30 MB1_CS_L0 MB_DATA62 AK16 MDB62
<8> -CSA3 <8> -CSB2
-CSB3 AB31 MB1_CS_L1 MB_DATA63 AH16 MDB63
<8> -CSB3
-SRASA W 25 MA_RAS_L
B <8> -SRASA -SCASA -SRASB B
<8> -SCASA Y24 MA_CAS_L
<8> -SRASB W 28 MB_RAS_L
-SWEA Y26 MA_WE_L -SCASB AA27 MB_CAS_L
<8> -SWEA <8> -SCASB
FM2+ / FM2 SEL -SWEB AA28 MB_WE_L
MEM_MA_RST- J25 <8> -SWEB
MA_RESET_L
<8> MEM_MA_RST-
MEM_MA_HOT- U24 MA_EVENT_L MEM_MB_RST- J27 MB_RESET_L
<8> MEM_MA_HOT- AQ2 <8> MEM_MB_RST-
MEM_MB_HOT- V28 MB_EVENT_L
<8> MEM_MB_HOT-

G
K22 M_VREF VOL_SELP 2 D14 MB_VREFDQ
APU_M_VREF MB_VREFDQ
E15 3 MB_ZVDD K25

D
MA_VREFDQ VREFDQ_A MB_ZVDDIO
MA_VREFDQ
MA_ZVDD J24 MA_ZVDDIO 1
VREFDQA FM2r2 REV 0.10

S
FM2b_SOCKET/[10SC1-A01906-01R_10SC1-A01906-02R]
AR23 39.2/4/1 MA_ZVDD 2N7002/SOT23/25pF/5
DDR15V FM2r2 REV 0.10
AR48 1K/4/1 MEM_MA_HOT- 5VDUAL AR27 39.2/4/1 MB_ZVDD
DDR15V DDR15V
FM2b_SOCKET/[10SC1-A01906-01R_10SC1-A01906-02R] DDR15V AR49 1K/4/1 MEM_MB_HOT-
AQ3
G
VOL_SELP 2
CPUVREF DDR15V
AR54
1K/4/1
D
3 VREFDQ_B
VREFDQA 1
S

40 MILS WIDTH
MEM CHA 5VDUAL
VOL_SELP
2N7002/SOT23/25pF/5 MEM CHB
3

APU_M_VREF SAR1
1K/4/1 AQ1
D
2D writing training switcher.
AR56
G S
1K/4/1
2N7002/SOT23/25pF/5
AQ5
2

1
1

SABC1 SABC2 SAR2 VOL_SELN

G

1N/4/X7R/50V/K 0.1U/4/X7R/16V/K SABC3 1K/4/1 VOL_SELN 2

3

1U/6/X7R/16V/K 3
D

VREFDQ_A
2

AQ0 1
A D MA_VREFDQ A
S

G S 2N7002/SOT23/25pF/5
2N7002/SOT23/25pF/5
2

VOL_SEL
<5,25> VOL_SEL AQ4
G

VOL_SELN 2
VOL_SEL 0 1 3
D

VREFDQ_B
1 Title
MB_VREFDQ
KAVERI TRINITY
S

APU DDRIII MEMORY

(FM2R2) (FM2) 2N7002/SOT23/25pF/5 Size Document Number Rev
Layout: Place within
B0 B1 Custom GA-F2A68HM-DS2 1.01
500mils of the CPU socket.
A0 A1
Date: Tuesday, October 28, 2014 Sheet 4 of 25
5 4 3 2 1
 5 4 3 2 1

DDR15V
www.xinxunwei.com 400-800-9990
FM2R2D
ANALOG/DISPLAY/MISC DDR15V AR35 1K/4/1
-CPURST AR47 300/4 N4 DP0_TXP0 DP_AUX_ZVSS G9 DP_A_ZVSS AR26 150/4/1
N5 DP0_TXN0 -PROCHOT AR37 0/4/SHT/M/X
-PROCHOT_CPU <9>
DP_BLON F8
AC25 M2 DP0_TXP1 DP_DIGON G8
100P/4/NPO/50V/J/X AC14

DISPLAY PORT 0
M3 DP0_TXN1 DP_VARY_BL E8
0.1u/4/Y5V/16V/Z/X
L2 DP0_TXP2 DP0_AUXP E1
L1 DP0_TXN2 DP0_AUXN E2

L4 DP0_TXP3 DP1_AUXP F1 DP1_AUXP 3VDUAL

DISPLAY PORT MISC.

DP1_AUXP <11>
L5 DP0_TXN3 DP1_AUXN F2 DP1_AUXN
DP1_AUXN <11>
D D
DP1_TXP0 K2 DP1_TXP0 DP2_AUXP G1 DP2_AUXP
<11> DP1_TXP0 DP1_TXN0 DP2_AUXN DP2_AUXP <16>
K3 DP1_TXN0 DP2_AUXN G2 AR34
<11> DP1_TXN0 DP2_AUXN <16>
8.2K/4
DDR15V AR50 1K/4/1/X APU_SVC DP1_TXP1 J2 DP1_TXP1 DP3_AUXP E5
APU_SVD <11> DP1_TXP1 DP1_TXN1 THERMTRIP_CPU_L
AR51 1K/4/1/X

DISPLAY PORT 1
<11> DP1_TXN1 J1 DP1_TXN1 DP3_AUXN E6 THERMTRIP_CPU_L <10,15>
AR39 1K/4/1 APU_SIC

3
AR40 1K/4/1 APU_SID DP1_TXP2 J4 DP1_TXP2 DP4_AUXP F5
<11> DP1_TXP2
DP1_TXN2 J5 DP1_TXN2 DP4_AUXN F6 AQ6 AC13
<11> DP1_TXN2
MMBT2222A/SOT23/600mA/40 0.1u/4/Y5V/16V/Z/X
DP1_TXP3 H2 DP1_TXP3 DP5_AUXP G5
<11> DP1_TXP3
DP1_TXN3 H3 DP1_TXN3 DP5_AUXN G6 SOT23

1
<11> DP1_TXN3
DP2_TXP0 L7 DP2_TXP0 DP0_HPD E3 DP0_HPD AR32 1K/4/1 THERMTRIP_L
<16> DP2_TXP0 DDR15V
DP2_TXN0 L8 DP2_TXN0 DP1_HPD F3 DP1_HPD DP1_HPD <11>
<16> DP2_TXN0 DP2_HPD
DP2_HPD G3 DP2_HPD <16> DDR15V AR33 300/4
DP2_TXP1 K5 DP2_TXP1 DP3_HPD E7 DP3_HPD
<16> DP2_TXP1 DP2_TXN1 DP4_HPD
<16> DP2_TXN1 K6 DP2_TXN1 DP4_HPD F7
DP5_HPD G7 DP5_HPD
ARN3
DP2_TXP2 K8 DP2_TXP2 DP5_HPD 8 7
<16> DP2_TXP2 DP2_TXN2 DP4_HPD
SVI 2.0 max frequency=20MHz.
Resolution=6.5mV
<16> DP2_TXN2 K9 DP2_TXN2 TEST4
TEST5
T21
U21 DP3_HPD
6
4 ★ 5
3 3VDUAL
DP2_TXP3 J7 DP2_TXP3 TEST6 AD14 DP0_HPD 2 1
<16> DP2_TXP3

DISPLAY PORT 2
SVT=Serial VID Telemetry for DP2_TXN3 J8 DP2_TXN3 TEST9 P21
<16> DP2_TXN3
TEST10 R21 100K/8P4R/6
APU get PWM infomation used. DP2_TXP4 AR53
<16> DP2_TXP4 N7 DP2_TXP4 TEST14 F12
DP2_TXN4 N8 DP2_TXN4 TEST15 E12 8.2K/4
<16> DP2_TXN4
TEST16 F13 ARN2
DP2_TXP5 M5 DP2_TXP5 TEST17 E13 APU_TEST18 8 7 SB_ALERT-
<16> DP2_TXP5 SB_ALERT- <11>
DP2_TXN5 G13 APU_TEST18 APU_TEST19
M6 DP2_TXN5 TEST18 6
★ 5

TEST
<16> DP2_TXN5

3
TEST19 G14 APU_TEST19 APU_TEST20 4 3
C DP2_TXP6 M8 DP2_TXP6 TEST20 F14 APU_TEST20 APU_TEST24 2 1 AQ7 AC35 C
<16> DP2_TXP6
DP2_TXN6 M9 DP2_TXN6 TEST24 E14 APU_TEST24 MMBT2222A/SOT23/600mA/40 0.1u/4/Y5V/16V/Z/X
<16> DP2_TXN6
TEST25_H AJ11 APU_TEST25H AR12 510/4/1 1K/8P4R/6
TEST25_L AH11 APU_TEST25L AR13 510/4/1 APU_VDD12
SOT23

1
<9> APUCLKP APUCLKP AL12 CLKIN_H TEST28_H H10
APU Spread 100Mhz clock APUCLKN AK12 CLKIN_L TEST28_L J10 AR36 1K/4/1

CLK
<9> APUCLKN DDR15V
TEST30_H T22
DP Non-Spread 100Mhz clock <9> DISP_CLKP DISP_CLKP AG12 DISP_CLKIN_H TEST30_L U22 DDR15V AR52 1K/4/1 APU_ALERT-
DISP_CLKN AF12 DISP_CLKIN_L TEST31 AG31 APU_TEST31 AR20 39.2/4/1
<9> DISP_CLKN
TEST32_H V22
APU_SVC C1 SVC TEST32_L R22
<21> APU_SVC
APU_SVD C2 SVD TEST35 AE14 APU_TEST35 AR21 300/4/1/X
<21> APU_SVD
APU_SVT D1 SVT AR22 300/4
<21> APU_SVT DDR15V

SER.
FM2R2 AC10 FM2R2 TEST35: high=>HDMI enable,
FM2R2 <20>
APU_SIC AK14 SIC DMAACTIVE_L AG14 -DMA_ACTIVE
<15> APU_SIC -DMA_ACTIVE <9> low=>HDMI disable.

MISC
APU_SID AL14 SID LDTSTOP_L AD10 LDTSTOP-
<15> APU_SID
IDLEEXIT_L G12 IDLEEXIT- AR14 1K/4/1 DDR15V
<9> -CPURST -CPURST AF10 RESET_L CORETYPE0 AJ13 CORETYPE0
CPU_PWRGD AF14 PWROK CORETYPE1 AH13 CORETYPE1

-PROCHOT AE10 F9

CTRL
PROCHOT_L RSVD1
THERMTRIP_L AH14
★ APU_ALERT- AJ14
THERMTRIP_L
ALERT_L
RSVD3
RSVD4
AD12
K23

RSVD
1K/8P4R/6 FM2R2 AR31 8.2K/4 3VDUAL
ARN1 CPU_TDI G11 TDI RSVD6 AB23
DDR15V 8 7 CPU_TDI E10 TDO RSVD7 AC24 -DMA_ACTIVE AR30 1K/4/1 DDR15V
6 5 CPU_TMS CPU_TCK E11 TCK RSVD8 AG10
4 3 CPU_TCK CPU_TMS F11 TMS LDTSTOP- AR57 1K/4/1/X DDR15V

JTAG
2 1 CPU_TRST- CPU_TRST- F10 TRST_L VDDP_SENSE C3
G10 DBRDY VDDNB_SENSE A3 VNB_FB+ <21>
AR38 1K/4/1 CPU_DBREQ E9 DBREQ_L VDDIO_SENSE A4

SENSE
B PQ10 B
VDD_SENSE B3 COREFB+ <21>
VDDR_SENSE C4 <21> VRM_HOT-
VSS_SENSE B4 -PROCHOT_CPU
COREFB- <21> -PROCHOT_CPU <9>
FM2r2 REV 0.10

FM2b_SOCKET/[10SC1-A01906-01R_10SC1-A01906-02R] BAT54A/SOT23/200mA

SOT23
DDR15V

AR43 FM2+ / FM2 SEL

300/4

CPU_PG_SB AR41 0/4/SHT/M/X F_SDT AR59 0/4/SHT/M/X PWM_PWRGD

<9> CPU_PG_SB PWM_PWRGD <21>
AR60 0/4/SHT/M/X CPU_PWRGD VCC3

PWM_PWRGD Input HIGH Threshold=1.1

AR6
8.2K/4 APU CORETYPE0 CORETYPE1

VOL_SEL TRINITY 1 1
VOL_SEL <4,25>
3

AQ8 KAVERI 0 1

A TBD 1 0 A
MMBT3904/SOT23/200mA/30
SOT23 TBD 0 0
2

AR7 1K/4/1 CORETYPE0

VCC3
AR8 499/4/1 VOL_SEL 0 1
AR9
0/4/X KAVERI TRINITY
CORETYPE1
(FM2R2) (FM2) Title
APU CONTROL
Size Document Number Rev
Custom GA-F2A68HM-DS2 1.01
Date: Tuesday, October 28, 2014 Sheet 5 of 25
5 4 3 2 1