A DETAILED APPLICATION OF TL494 PSPICE MODEL IN DESIGNING
SWITCHING REGULATORS: AN EDUCATIONAL APPROACH
Chandra Shetty1, Anil Kadle2, A.B.Raju3, Member IEEE
1
Dept. of Electrical Engg., National Institute of Technology, Karnataka
2
Dept. of Electrical Engg., Anjuman Institute of Technology and Management, Bhatkal
3
Dept. of Electrical Engg., B.V.B College of Engg. Hubli
E-mail: 1chandra_shetty84@yahoo.com, 2anilkadle@gmail.com, 3abraju@bvb.edu
Abstract: This paper describes the application of
TL494 PSPICE MODEL with OrCAD Capture for
analyzing switching regulators, which can assist
beginners like undergraduate students in understanding
the switching regulators. This paper mainly focuses on
application of simulation model as none of the
literatures provides required information to work with
TL494 simulation model. Although TL494 chip is a
very simple chip as far as hardware is concerned, it is
not easy work with Pspice model of TL494 without
adequate knowledge about the Pspice software. The
application of this chip’s simulation model with OrCAD
Capture is demonstrated with the help of buck
converter. This application report can also be extended
to other non-isolated as well as isolated converters.
Keywords: TL494 Pspice Model, OrCAD Capture,
convergence, RELTOL, V_PWM, INPUT_VTH,
V_DTC.
INTRODUCTION
Pulse width modulation (PWM) is a very important
aspect in power electronics course. There are many
dedicated commercially available PWM chips like
SG1524, TL494 e.t.c. The most popular one is TL494
due to its low cost, simplicity and robustness. In [1], the
application of architecture of TL494 chip in designing
switching regulators is described, but no attention has
been given towards the application of simulation model.
We can obtain pulse width modulation using analog
behavior modeling (ABM) tool in PSPICE [2], but this
approach does not give any required information about
hardware implementation of the chip. The simulation
model of actual device is very important which can
assist in developing physical converter.
The Pspice model of the TL494 IC can be found
in controller.olb library of the OrCAD software
package. Few websites have provided the Pspice model
of TL494, but none of them has furnished required
information about the detailed application of this model
with the OrCAD Capture. The Pspice model provided
by them cannot be guaranteed that the model is going to
work with OrCAD Capture. It is better to work with
model that is readily available in the Pspice Library of
OrCAD software and tested by Cadence Design System.
We can’t directly use Pspice model on schematic page
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based on the information of the dedicated literatures
about TL494 architecture as the employment of TL494
Pspice model on OrCAD Capture is quite different from
hardware application report. For beginners like
undergraduate students, who would like to work in the
field of switching regulators it is not necessary to master
all the commercial PWM Chips. It is sufficient if the
students have adequate knowledge about at least one
PWM chip, which can be employed to analyze all kind
of switching regulators. All PWM chips have their own
merits and demerits. This paper focuses only on
application of TL494 Pspice simulation model for
switching regulators.
The reported work in [3] focus on inclusion of
soft-soft start characteristic into the Pspice model of
different commercially available PWM chips, but it
doesn’t give any information on application of the
simulation model. The Cadence Design System has
furnished a piece of information about the application of
Tl494 Pspice model with OrCAD Capture in its website
[4], which is insufficient for beginners. Students who
are new to the OrCAD Capture find it very difficult to
work with TL494 simulation model without adequate
information about its proper application with the
software while carrying out their academic projects. If a
student becomes familiar with any one of the simulation
model of PWM chips, it would help him to work with
other PWM chips as well, as principle of working of
different PWM chips remain almost same. Considering
all these difficulties to work with the model, we have
made an effort to deal in detail with the application of
TL494 Pspice model.
PSPICE MODEL OF TL494
As it is already mentioned in the introductory part, the
Pspice model of TL494 can be found in controller.olb.
The schematic of this model is shown in Fig. 1. The
attribute V_DTC refers to the dead time control offset
voltage at pin 4 of the controller. This sets the default
dead time controller for the TL494 controller. If there is
a slow ramp connected to the dead time control input,
the dead time between the outputs will change. The
attribute V_PWM refers to the PWM comparator offset
at pin 5 of the controller. The values can range from
minimum = 0.5, typical = 0.7 and maximum 1V. The
attribute PERIOD specifies the time period of the
oscillator. INPUT_VTH is the minimum PWM common emitter configuration (Fig. 3). The frequency
comparator voltage at pin 3. It produces a duty cycle of considered here is 100 KHz i.e. period equal to 10us.
0%. This voltage is sum of the sawtooth voltage and The required settings for the proper simulation of the
the comparator offset voltage (V_PWM). model are shown in Table 1. If we run the simulation
with default settings, the simulation will fail due to
Attributes Used For convergence problem. The iteration limit is increased
from 10 to 100 [5]. Few literatures recommend
DEAD TIME CONTROL changing the default value of RELTOL to solve the
V_DTC convergence problem. We should not change default
OFFSET
relative tolerance RELTOL value 0.001. For TL494
V_PWM PWM COMPARATOR OFFSET Pspice model, changing this value would result in error
message.
MINIMUM PWM
INPUT_VTH
COMPARATOR VOLTAGE

OVERVIEW OF THE SWITCHING SIGNALS

The schematic diagram for producing switching signals

is shown in Fig. 2. The switching signals are shown in
Fig. 3. The switching signal can be obtained either by
emitter follower configuration or common emitter
configuration. The gate signal G1 is obtained from
emitter follower configuration and G2 is obtained from Fig. 1. Pspice model of TL494.

Fig. 2. Schematic diagram for producing switching signals for a converter.

Fig. 3. Switching signals for the converters operation.

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 Parameter New Value Default Value offset (V_PWM) is set to zero and the parameter
INPUT_VTH is assigned with a value, which is equal to
RELTOL 0.001 0.001 peak value of the sawtooth wave so that the value of the
VNTOL 1u 1u dc voltage to be connected at pin no. 3 can be calculated
ABSTOL 1p 1p easily which is described in the above paragraph.
CHGTOL 0.01p 0.01p Schematic of the power stage is shown in Fig. 6. The
GMIN 1.0E-12 1.0E-12 output voltage is shown in Fig. 7.
ITL1 150 150
CLOSED LOOP CONTROL
ITL2 20 20
ITL4 100 10 Fig. 8 shows Pspice schematic of the PWM stage. For
closed loop control, the main switch should be driven
Table 1. Simulation Settings from the signals taken from emitter follower
configuration. If the synchronous rectifier is used in
OPEN LOOP CONTROL place of diodes for rectification, then it must be driven
from the signal taken from common emitter
For the open loop control of switching regulators, ON
configuration. The TL494 Pspice model is having two
period of the gate signal i.e. duty ratio must be adjusted
error amplifiers. Any one of the error amplifier can be
to get the required output that can be accomplished by
used for regulation with proper compensation. The
varying the DC voltage at pin no. 3. The signal for
unused error amplifier terminals must be grounded. For
driving the switch must be obtained from common
the SG1524 family of chips, reference voltage is given
emitter configuration. The unused error amplifier
to positive terminal of the error amplifier. For TL494
terminals must be grounded. As the frequency of the
family of chips, reference voltage must be given to
switching regulator is adjusted in the schematic of the
negative terminal of the error amplifier as it is having
Pspice model, the pin no.5 and 6 can be grounded using
opposite internal sense [7]. The reference voltage,
high value resistances [6]. The physical TL494 IC uses
which is 3.3V for this example, is obtained from
the resistor and capacitor combination to set the
internal voltage source of 5V by using voltage divider
frequency using the following relation:
resistances i.e 1.7kΩ and 3.3kΩ (shown in the Fig. 8).
Soft starting components are also included in the PWM
stage. The procedure for calculation of soft starting
(1)
component values can be found in [1]. Pin no. 13 is
Buck converter is used as a design example to grounded for parallel output.
demonstrate the approach. The design specifications of
the converter are shown in Table 2. Buck Converter with Diode Rectifier

Vs 50V The Table 3 shows design specifications for closed loop

buck converter with diode rectifier. The driving signal
D 0.4 for the switch is obtained from emitter follower
Vo 20V configuration. To avoid the convergence problem,
L 400uH following changes has been made to .OPTIONS
C 100uF settings RELTOL=0.001, VNTOL=10u,
f 20kHz ABSTOL=0.001u, CHGTOL=0.01p, GMIN=0.1n,
R 20Ω ITL1=1000. ITL2=1000, ITL4=1000. If the simulation
carried out with default settings, the simulation will fail
Table 2. Design Specifications Of The Buck Converter with convergence problem. Here, off page connectors
are used for connecting compensating components to
The PWM stage of the converter is shown in Fig. 4. The error amplifier. The power stage of the converter is
duty cycle is controlled by adjusting the voltage source shown in Fig. 9. The output voltage is shown in Fig. 10.
at pin no. 3 in Pspice model. To obtain the desired duty
cycle, the magnitude of the voltage source to be
connected at pin no. 3 is obtained using the following Vs 6V
equation. The required magnitude of the voltage source Vo 3.3V
= duty cycle × peak value of the sawtooth i.e 3V. For L 100uH
this example, the duty cycle is 0.4. So, the required
value of the magnitude of voltage source to be C 100uF
connected at pin no. 3 is 0.4×3=1.2 (Fig. 4). The f 100kHz
corresponding ON period is 20us as shown in Fig. 5. In R 4Ω
the schematic of the Pspice model, PWM comparator
Table 3. Design Specifications

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 Fig. 4. Schematic for producing gate signal for open loop control.

Fig. 5. Switching signal for the converter from common emitter configuration.

Fig. 6. Schematic of the power stage.

Fig. 7. Output voltage.

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 Fig. 8. Schematic of the PWM stage.

Fig. 9. Schematic of the power stage.

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 Fig. 10. Output voltage

Buck Converter with Synchronous Rectifier
Synchronous buck converters are employed for the
improved efficiency. The TL494 PWM chip can also be
used to operate switching regulators with synchronous
rectifiers. This concept is demonstrated by considering
the converter, discussed above, as design example and
replacing diode rectifier by synchronous rectifier in the -
power stage. The PWM stage for this example is same
as above. The driving signal for synchronous rectifier is
obtained by common emitter configuration, described
by the word OFFPAGELEFT-2, as shown in Fig. 11.
The output voltage is shown in Fig. 12.

Fig. 11. Schematic of the power stage.

Fig. 12. Output voltage.

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CONCLUSION
All the aspects of simulation model of TL494 PWM IC
in designing switching regulators have been addressed
in detail with the examples. As all of the literatures
about TL494 PWM IC converge on architecture of this
chip, this article, specifically focus on simulation model,
would be great helpful for beginners like undergraduate
students who undergo power electronics course. The
reported work can also be extended to other converters.
ACKNOWLEDGEMENTS
‘National Institute of Technology Karnataka’, India,
supported this work.
REFERENCES
[1] Patrick Griffith (2005): “Designing switching
regulators with the TL494 (2005)”, Texas
Instruments.
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[2] Rashid. M.H(1995): “SPICE for Circuits and
Electronics Using Pspice”, Prentice - Hall.
[3] Fu-Yan Shih, Yie-Tone Chen, Dan Y Chen (1995):
“Pspice-Compatible Model of PWM IC for
SwitchingPower Converters with Soft-Start
Characteristic”, IEEE Conference on PEDS, Vol.1,
pp. 335-340.
[4] Orcad.com. (2012) Design community in action.
[Online]. Available: http://www.orcad.com/
community.pspice.faq.aspx.
[5] Daniel.W.Hart (2011): “Power Electronics”, Tata
Mcgraw Hill.
[6] “Pspice User’s Guide (2000)”, 2nd edition, Cadence
Design System.
[7] H. Dean Venable, Venable Industries (1983): “The k
factor: a new mathematical tool for stability analysis
and synthesis”, Reference Reading #4.