IEEE Sponsored 2nd International Conference on Innovations in Information,Embedded and Communication systems (ICIIECS)2015
A Quick and Simplified Approach for
Understanding the Dynamics of the SEPIC
Converter for Low Voltage Applications:
Simulation Study
Chandra Shetty, Member, IEEE
Department of Electrical & Electronics Engineering
National Institute of Technology Karnataka, Surathkal, India
chandra shetty84@yahoo.com
Abstract—Designing the feedback compensator for the SEPIC
(single ended primary inductance converter) converter is quite
difficult due to the extreme amount of phase shift in the power
stage and occurrence of double resonance. Hence the current
mode control, which increases the complexity of the system, is the
most commonly adapted for stabilizing the converter. However,
the careful observation of the frequency response of power stage,
which depends on the filter components and equivalent series
resistance of the capacitor, of the power stage makes the process
of controlling the dynamics of the converter easy. Sometimes the
frequency response of the power stage of the converter is free
of double resonance with minimum phase shift and resembles
the second order converter. So, one can develop the compensator
network similar to the second order converter. In this paper, the
design of controller for the SEPIC converter based on single loop
feedback control is presented without the need of current mode
control and its associated complexity. The presented analysis
does not require the complicated methods such as the principal
component analysis and the model order reduction but it is as
simple as observing the bode plot of the power stage of the
converter. The entire simulation is carried out in Pspice.
Index Terms—Fourth order converters, k-factor approach,
small signal model, SEPIC converter, voltage mode control.
I. I NTRODUCTION
Fourth order converters are preferred by power electronics
engineers over second order converters due to their high
performance. As the SEPIC converter consists of four energy
storage elements, it is labeled as fourth order converter. The
SEPIC converter is shown in Fig. 1(a) [1]. It is assumed that
the converter operates in continuous conduction mode (CCM).
The Fig. 1(b) shows the circuit status when the switch is
on and Fig. 1(c) shows SEPIC converter when the switch
is off. When the switch is turned on, the inductor, L1, is
charged from the input voltage source. The second inductor
takes energy from the first capacitor and the output capacitor is
left to provide the load current. When the switch is turned off,
the first inductor charges the capacitor C1 and also provides
current to the load. The second inductor is also connected to
the load during this time.
It has always been believed that the stabilization of fourth
order converter is a tedious process due to the large amount of
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phase shift in the power stage and the voltage mode control
cannot be adapted. Since the current mode control reduces
the order of the power stage by eliminating the effect of
inductance, it is the usual method employed to control the
fourth order converters. However, the current mode control
brings on other complexities. So, the voltage mode control
is the most preferred method due to its simplicity. Since
the power stage of the fourth order converter entails four
energy storage elements, there will be a large amount of
phase shift which makes the voltage mode control unfavorable
for controlling the fourth order converter and hence either
the model reduction method [2] or the principal component
analysis [3] can be employed for adapting the voltage mode
control in controlling the fourth order converters. Both the
method involves complex theory and a lot of mathematics.
This paper deals with the fact how one can employ the voltage
mode control by carefully observing the frequency response
of power stage for low voltage applications.
Some applications, such as portable devices, require low
voltages. Since the size of power stage components is the
function of load voltage, its dimensions will be reduced
considerably. Therefore, phase shift in the power stage will
be truncated. Consequently, the voltage mode control can be
adapted for shaping the dynamics of the converter.
II. M ETHODOLOGY
For understanding the dynamics of a converter, it is com-
mon to adapt frequency domain approach. So, the frequency
response of the converter is necessary. To get the frequency
response, it is essential to have the linear model of the power
stage, since it is inherently non linear, of the converter. After
obtaining the small signal model of the converter through
any of the existing standard methods, frequency response is
plotted. In this paper, bode plot of the converter is obtained
by AC Sweep analysis of the Pspice simulation tool. Once the
plot is available, the feedback components are calculated using
k-factor approach based on gain and phase shift. Eventually,
entire converter simulation for transient response will be
 IEEE Sponsored 2nd International Conference on Innovations in Information,Embedded and Communication systems (ICIIECS)2015

TABLE I
SEPIC C ONVERTER S PECIFICATIONS

Parameter Value Parameter Value

Input Voltage 2.7 V C1 10 µF
Output Voltage 3.3 V ESR of C1 0.382 Ω
Switching Frequency 300 kHz C2 141 µF
L1 5 µH ESR of C2 0.003 Ω
ESR of L1 0.0038Ω Load Resistance 100 Ω
L2 5 µH Bandwidth 10 kHz
ESR of L2 0.109Ω Phase Margin 60 degree

(a)
works approximately as an ideal diode [1] with emission
coefficient n = 0.001. The default value of emission coefficient
in the vendor model is n = 1.

III. AC M ODEL OF THE SEPIC C ONVERTER

(b)
(c)
Fig. 1. (a) SEPIC Circuit; (b) Circuit with the switch closed and the diode
off; (c) Circuit with the switch open and the diode on.
carried in Pspice. The proposed approach is valid only if the
phase shift due to filter components of the power stage is less
than 180 degree. However, as the converter for low voltage
application is considered, the phase shift would be, most of
the times, is less than 180 degree.
For the simulation, the swiches of the converter are im-
plimented using ‘Sbreak Switch’ model [4]–[6]. The PWM
signals are obtained by TL494 Pspice Model. The Pspice
model of this chip is available in controller.olb. For the
capacitor and the inductor, we can use PSPICE model from
PSPICE library breakout.olb. Dbreak, Pspice model of the
diode, is employed for transferring the energy to output which
The small signal model of the PWM dc-dc converters can be
developed with the aid of different modeling techniques, such
as state space averaging, circuit averaging, current injected ap-
proach, averaged switch modeling, etc. State-space averaging
is quite useful for developing the transfer functions of dc-
dc converters and involves the manipulation of equations. In
circuit averaging technique the converter equivalent circuit is
obtained by averaging the converter waveforms. The converter
model can also be obtained by replacing the switches by its
averaged model. In this paper the AC model of the converter
is obtained by replacing the switch network with its average
model [7]. The average model can be found in Pspice library
of averaged models. The library of these models can be
downloaded from the website. The model script is repeated
here.
.subckt CCM1 1 2 3 4 5
Et 1 2 value={(1-v(5))*v(3,4)/v(5)}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)}
.ends
These can be employed in spice model editor to obtain
the capture of the averaged model. This is valid for a dc-dc
converter operating in continuous conduction mode. The small
signal model of power stage can be with respect to change
in duty ratio or with respect to change in line voltage [8].
Here the average model of the power stage is considered with
respect to variation in the duty cycle.
The Table I show the specifications of the converter and
the Fig. 2 shows the small signal model of the power stage
which is employed for determining the frequency response
using computer simulation, Pspice. The bode plot of the power
stage is shown in the Fig. 3. The phase shift in the power stage
is -176 degree and the gain is 7.216 dB at the phase cross over
frequency of 10 kHz.
IV. C OMPENSATOR N ETWORK
For compensating the converter, type III compensator is
used as shown in the Fig. 4 with compensator component

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 IEEE Sponsored 2nd International Conference on Innovations in Information,Embedded and Communication systems (ICIIECS)2015

Fig. 2. Small signal model of the SEPIC converter.

values. Type III error amplifier is commonly referred as V. R ESULT AND D ISCUSSION
PID (proportional plus integral plus derivative) controller in
The output voltage is shown in the Fig. 5. The output
technical literature. The type III compensation is adapted when
voltage reaches steady state voltage of 3.3V after the transient
the phase boost required is more than 90 degree and less than
period dies out. The settling time is around 10.517ms. Here
180 degree. The phase margin indicates the relative stability
settling time is quite long since the converter is not optimized
of the system. The more phase margin is selected, the more
for bandwidth. The bandwidth depends on the amount of
stability is assured. However, one cannot go for high phase
phase shift in the power stage which in turn depends on the
margin which would result in increased settling time. As a
value of passive components. The converter bandwidth can be
compromise between stability and good transient response,
improved with a little more work.
a phase margin of 60 degree is chosen. The compensator
components are calculated with the aid of k-factor approach
[9] at the bandwidth of 10kHz. The compensating components VI. C ONCLUSION
are calculated using the equations as shown below. These The controller design for the fourth order SEPIC converter
equations repeated here from the k-factor approach. using the voltage mode control is discussed. It is observed that
the sensible evaluation of the bode plot of the power stage of
the converter would ease the process of stabilization. Since the
control to output frequency response of the converter approx-
Boost = M − P − 90 (1) imate to the second order converter, type III compensation is
0 2 applied to control the dynamics of the converter. For the given
K = (tan[(Boost/4) + 45 ]) (2)
1 specifications of the converter, the frequency response of the
C2 = (3) converter is free of double resonance. Accordingly, it requires
2πf GR1
neither the principal components analysis nor the model order
C1 = C2 (k − 1) (4)
√ reduction method for stabilizing the converter. In actual fact,
k sometimes it’s the passive components that determine the type
R2 = (5)
2πf C1 of controller which can be applied to govern the dynamics of
R1 the converter.
R3 = (6)
(k − 1) The process, quick and simple, described in the methodol-
1 ogy section can be applied to a SEPIC converter only when
C3 = √ (7)
2πf kR3 the total phase shift in the power stage of the converter is
less than 180 degree. In contrast, the current mode is the
only alternative if the phase shift is more than 180 degree.
G = Amplifier gain at cross-over frequency Another disadvantage of this method is one cannot go for high
M = Desired Phase Margin (degrees) band width to have improvement over transient response since
P = Modulator Phase Shift (degrees) designer has to restrict to a bandwidth frequency where phase

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 IEEE Sponsored 2nd International Conference on Innovations in Information,Embedded and Communication systems (ICIIECS)2015

Fig. 3. Frequency response of the control to output transfer function.

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Fig. 4. Type III error amplifier.. [8] B. Sahu and G. A. Rincón-Mora, “A low voltage, dynamic, noninvert-
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H1–1.

Fig. 5. Transient response of the converter.

shift is less than 180 degree. For the improvement in transient

response, it is necessary to reduce the order of the converter by
measuring the current of the inductor, current mode control,
and selecting a higher bandwidth, which is not possible in the
above discussed method.

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