5 4 3 2 1

AMD APU FS1R2

BATTERY BATT+ PU21 PU27 +CPU_CORE
12.6V CHARGER ISL6277HRTZ-T 0.7~1.475V VDD CORE 60A
+CPU_CORE
BQ24725RGRR 0.7~1.475V VDDNB 37A
+CPU_CORE_NB +CPU_CORE_NB
+2.5VS +2.5VS VDDA 750mA
+2.5VS
+1.5V VDDIO 3.2A
PU26 +1.5V +1.5V
D AC ADAPTOR VIN RT8207MZQW +1.2VS VDDR 8.5A D
19V 90W +0.75VS PU15 +1.2VS
APL5508
RAM DDRIII SODIMMX2
PU17 +1.2VS +1.5V VDD_MEM 4A
RT8209MGQW
B+ +0.75VS VTT_MEM 0.5A

+0.75VS
+0.75VS
VGA ATI
+VGA_CORE Whistler/Seymour/Granville
PU10
+VGA_CORE 0.85~1.1V VDDC 47A
TPS51218DSCR
+VDDCI
0.9~1.0V VDDCI 4.6A
+VDDCI
+1.0VSG DPLL_VDDC: 125 mA
PU14 SPV10: 120 mA
G9731G11U +1.0VSG PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
+1.5VSG VRAM 512/1GB/2GB
U41
+1.5VSG VDDR1: 3400 mA 64M / 128Mx16 * 4 / 8
AO4430L
PU5 +1.1VALW
RT8209MGQW PLL_PVDD: 75 mA +1.5VSG 2.4 A
TSVDD: 20 mA
AVDD: 70 mA
C VDD1DI: 100 mA C
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
PU2 +3VALW
U40 PU7 VDD_CT: 110 mA
RT8205EGQW VDDR4: 170 mA
+5VALW SI4800 SY8033BDBC +1.8VSG +1.8VSG
+1.8VSG
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA

+3VS
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
+INVPWR_B+

+3VS
JUMP +3VSG A2VDD: 130 mA
U38 +3VSG +3VSG VDDR3: 60 mA
SI4800

LCD panel +5VS FCH AMD Hudson M2/M3

15.6"
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
B+ 300mA U39 VDDCR_11: 1007 mA
AO4430L +1.1VS +1.1VS
+3.3 350mA +1.1VS VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA

+5VS VDDAN_11_USB_S: 140 mA

FAN Control VDDCR_11_USB_S: 197 mA
B APL5607 +1.1VALW VDDAN_11_SSUSB_S: 282 mA B
+1.1VALW
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
+5VS 500mA VDDPL_11_SYS: 70 mA
Q63
SI2301
U54 +5VALW VDDIO_33_PCIGP: 131 mA
TPA2301DRG4 VDDPL_33_SYS: 47 mA
+USB_VCCA
VDDPL_33_DAC: 20 mA
+3VS VDDPL_33_ML: 20 mA
+3VS +3VS VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
USB X3 VDDPL_33_SATA: 93 mA
+1.5VS

VDDIO_AZ_S: 26 mA
+5V
Dual+1
2.5A +3VALW VDDPL_33_SSUSB_S: 20 mA
+3VALW VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
+3VALW
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
SATA Audio Codec EC LAN VDDAN_33_HWM_S: 12 mA
HDD*1 ALC271X ENE KB930 BCM57785 Mini Card*2
ODD*1
VDDIO_33_GBE_S
+5V 3A +5V 45mA +3.3VALW 30mA +3.3VALW 201mA +1.5VS 500mA VDDCR_11_GBE_S
+3.3VS 3mA +3.3VS 1A GND VDDIO_GBE_S
+3.3V +3.3VS 25mA +3.3VALW 330mA

RTC
A
Bettary RTC BAT VDDBT_RTC_G A

Security Classification Compal Secret Data

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title
POWER DELIVERY CHART
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8731P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 5 of 47
5 4 3 2 1
 A B C D E

UCPU1A
AP1 P_GFX_RXP[0] P_GFX_TXP[0] AN1
AP2 P_GFX_RXN[0] P_GFX_TXN[0] AN2
AM1 P_GFX_RXP[1] P_GFX_TXP[1] AM4
AM2 P_GFX_RXN[1] P_GFX_TXN[1] AM3
1 1
AK3 P_GFX_RXP[2] P_GFX_TXP[2] AK2
AK4 P_GFX_RXN[2] P_GFX_TXN[2] AK1
AJ1 P_GFX_RXP[3] P_GFX_TXP[3] AH1
AJ2 P_GFX_RXN[3] P_GFX_TXN[3] AH2
AH4 P_GFX_RXP[4] P_GFX_TXP[4] AF3
AH3 P_GFX_RXN[4] P_GFX_TXN[4] AF4
AF2 P_GFX_RXP[5] P_GFX_TXP[5] AE1
AF1 P_GFX_RXN[5] P_GFX_TXN[5] AE2
AD1 P_GFX_RXP[6] P_GFX_TXP[6] AD4
GPU AD2 P_GFX_RXN[6] P_GFX_TXN[6] AD3
AB3 AB2

GRAPHICS
P_GFX_RXP[7] P_GFX_TXP[7]
Delete GPU AB4 P_GFX_RXN[7] P_GFX_TXN[7] AB1 Delete GPU GPU
1202 Calvin AA1 P_GFX_RXP[8] P_GFX_TXP[8] Y1 1202 Calvin
AA2 P_GFX_RXN[8] P_GFX_TXN[8] Y2
Y4 P_GFX_RXP[9] P_GFX_TXP[9] V3
Y3 P_GFX_RXN[9] P_GFX_TXN[9] V4
V2 P_GFX_RXP[10] P_GFX_TXP[10] U1
V1 P_GFX_RXN[10] P_GFX_TXN[10] U2
T1 P_GFX_RXP[11] P_GFX_TXP[11] T4
T2 P_GFX_RXN[11] P_GFX_TXN[11] T3
P3 P_GFX_RXP[12] P_GFX_TXP[12] P2
P4 P_GFX_RXN[12] P_GFX_TXN[12] P1
N1 P_GFX_RXP[13] P_GFX_TXP[13] M1
N2 P_GFX_RXN[13] P_GFX_TXN[13] M2
M4 P_GFX_RXP[14] P_GFX_TXP[14] K3
M3 P_GFX_RXN[14] P_GFX_TXN[14] K4
K2 P_GFX_RXP[15] P_GFX_TXP[15] J1
K1 P_GFX_RXN[15] P_GFX_TXN[15] J2

AH5 AG7 PCIE_FTX_DRX_P0 CC33 1 2 .1U_0402_16V7K

23 PCIE_DTX_C_FRX_P0 P_GPP_RXP[0] P_GPP_TXP[0] PCIE_FTX_C_DRX_P0 23
GLAN/Card reader AH6 AG8 PCIE_FTX_DRX_N0 CC34 1 2 .1U_0402_16V7K GLAN/Card reader
23 PCIE_DTX_C_FRX_N0 P_GPP_RXN[0] P_GPP_TXN[0] PCIE_FTX_C_DRX_N0 23
AG5 AE7 PCIE_FTX_DRX_P1 CC35 1 2 .1U_0402_16V7K
2 21 PCIE_DTX_C_FRX_P1 P_GPP_RXP[1] P_GPP_TXP[1] PCIE_FTX_C_DRX_P1 21
WLAN AG6 AE8 PCIE_FTX_DRX_N1 CC36 1 2 .1U_0402_16V7K WLAN 2
21 PCIE_DTX_C_FRX_N1 P_GPP_RXN[1] P_GPP_TXN[1] PCIE_FTX_C_DRX_N1 21
AE6 P_GPP_RXP[2] P_GPP_TXP[2] AD7
AE5 P_GPP_RXN[2] P_GPP_TXN[2] AD8
AD6 AB6

GPP
P_GPP_RXP[3] P_GPP_TXP[3]
AD5 P_GPP_RXN[3] P_GPP_TXN[3] AB5

AM10 AN6 UMI_FTX_MRX_P0 CC37 1 2 .1U_0402_16V7K

13 UMI_MTX_C_FRX_P0 P_UMI_RXP[0] P_UMI_TXP[0] UMI_FTX_C_MRX_P0 13
AN10 AM6 UMI_FTX_MRX_N0 CC38 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_N0 P_UMI_RXN[0] P_UMI_TXN[0] UMI_FTX_C_MRX_N0 13
AN8 AP6 UMI_FTX_MRX_P1 CC39 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_P1 P_UMI_RXP[1] P_UMI_TXP[1] UMI_FTX_C_MRX_P1 13
UMI AM8 AR6 UMI_FTX_MRX_N1 CC40 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_N1 P_UMI_RXN[1] P_UMI_TXN[1] UMI_FTX_C_MRX_N1 13
AP8 AP4 UMI_FTX_MRX_P2 CC41 1 2 .1U_0402_16V7K UMI
13 UMI_MTX_C_FRX_P2 P_UMI_RXP[2] P_UMI_TXP[2] UMI_FTX_C_MRX_P2 13
AR8 AR4 UMI_FTX_MRX_N2 CC42 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_N2 P_UMI_RXN[2] P_UMI_TXN[2] UMI_FTX_C_MRX_N2 13
AR7 AP3 UMI_FTX_MRX_P3 CC43 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_P3 P_UMI_RXP[3] P_UMI_TXP[3] UMI_FTX_C_MRX_P3 13
AP7 AR3 UMI_FTX_MRX_N3 CC44 1 2 .1U_0402_16V7K

UMI
13 UMI_MTX_C_FRX_N3 P_UMI_RXN[3] P_UMI_TXN[3] UMI_FTX_C_MRX_N3 13

+1.2VS 1 2 P_ZVDDP AR11 AP11 P_ZVSS 1 2

RC1 196_0402_1% P_ZVDDP P_ZVSS RC2 196_0402_1%
TRINITY-A8-SERIES_BGA813

L P_ZVDDP W/S=8/12 mil, <3000mil L P_ZVSS W/S=8/12 mil, <3000mil

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD FP2 PCIE / GFX / UMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 6 of 47

A B C D E
 A B C D E

UCPU1C
UCPU1B 12 DDRB_SMA[15..0] DDRB_SDQ[63..0] 12
DDRB_SMA0 Y33 C16 DDRB_SDQ0
11 DDRA_SMA[15..0] DDRA_SDQ[63..0] 11 MB_ADD[0] MB_DATA[0]
DDRA_SMA0 AA28 F15 DDRA_SDQ0 DDRB_SMA1 R32 B17 DDRB_SDQ1
DDRA_SMA1 MA_ADD[0] MA_DATA[0] DDRA_SDQ1 DDRB_SMA2 MB_ADD[1] MB_DATA[1] DDRB_SDQ2
R29 MA_ADD[1] MA_DATA[1] E15 T31 MB_ADD[2] MB_DATA[2] B20
DDRA_SMA2 T30 H19 DDRA_SDQ2 DDRB_SMA3 P33 C20 DDRB_SDQ3
DDRA_SMA3 MA_ADD[2] MA_DATA[2] DDRA_SDQ3 DDRB_SMA4 MB_ADD[3] MB_DATA[3] DDRB_SDQ4
R28 MA_ADD[3] MA_DATA[3] F19 P32 MB_ADD[4] MB_DATA[4] A16
1 DDRA_SMA4 DDRA_SDQ4 DDRB_SMA5 DDRB_SDQ5 1
R26 MA_ADD[4] MA_DATA[4] E14 P31 MB_ADD[5] MB_DATA[5] B16
DDRA_SMA5 P26 H15 DDRA_SDQ5 DDRB_SMA6 N32 B19 DDRB_SDQ6
DDRA_SMA6 MA_ADD[5] MA_DATA[5] DDRA_SDQ6 DDRB_SMA7 MB_ADD[6] MB_DATA[6] DDRB_SDQ7
P27 MA_ADD[6] MA_DATA[6] E17 M33 MB_ADD[7] MB_DATA[7] A20
DDRA_SMA7 P30 D18 DDRA_SDQ7 DDRB_SMA8 M32
DDRA_SMA8 MA_ADD[7] MA_DATA[7] DDRB_SMA9 MB_ADD[8] DDRB_SDQ8
P29 MA_ADD[8] L32 MB_ADD[9] MB_DATA[8] B22
DDRA_SMA9 M28 G20 DDRA_SDQ8 DDRB_SMA10 AB31 C22 DDRB_SDQ9
DDRA_SMA10 MA_ADD[9] MA_DATA[8] DDRA_SDQ9 DDRB_SMA11 MB_ADD[10] MB_DATA[9] DDRB_SDQ10
AB26 MA_ADD[10] MA_DATA[9] E20 M31 MB_ADD[11] MB_DATA[10] A26
DDRA_SMA11 M26 H23 DDRA_SDQ10 DDRB_SMA12 K32 B26 DDRB_SDQ11
DDRA_SMA12 MA_ADD[11] MA_DATA[10] DDRA_SDQ11 DDRB_SMA13 MB_ADD[12] MB_DATA[11] DDRB_SDQ12
M29 MA_ADD[12] MA_DATA[11] G23 AF33 MB_ADD[13] MB_DATA[12] B21
DDRA_SMA13 AE27 E19 DDRA_SDQ12 DDRB_SMA14 K33 A22 DDRB_SDQ13
DDRA_SMA14 MA_ADD[13] MA_DATA[12] DDRA_SDQ13 DDRB_SMA15 MB_ADD[14] MB_DATA[13] DDRB_SDQ14
L26 MA_ADD[14] MA_DATA[13] H20 J32 MB_ADD[15] MB_DATA[14] C24
DDRA_SMA15 L27 E22 DDRA_SDQ14 B25 DDRB_SDQ15
MA_ADD[15] MA_DATA[14] DDRA_SDQ15 DDRB_SBS0# MB_DATA[15]
MA_DATA[15] D22 12 DDRB_SBS0# AB33 MB_BANK[0]
DDRA_SBS0# AB27 DDRB_SBS1# AA32 A28 DDRB_SDQ16
11 DDRA_SBS0# MA_BANK[0] 12 DDRB_SBS1# MB_BANK[1] MB_DATA[16]
DDRA_SBS1# AA29 H25 DDRA_SDQ16 DDRB_SBS2# K31 B28 DDRB_SDQ17
11 DDRA_SBS1# MA_BANK[1] MA_DATA[16] 12 DDRB_SBS2# MB_BANK[2] MB_DATA[17]
DDRA_SBS2# M30 F25 DDRA_SDQ17 B31 DDRB_SDQ18
11 DDRA_SBS2# MA_BANK[2] MA_DATA[17] 12 DDRB_SDM[7..0] MB_DATA[18]
D28 DDRA_SDQ18 DDRB_SDM0 C18 A32 DDRB_SDQ19
11 DDRA_SDM[7..0] MA_DATA[18] MB_DM[0] MB_DATA[19]
DDRA_SDM0 D16 D29 DDRA_SDQ19 DDRB_SDM1 B23 C26 DDRB_SDQ20
DDRA_SDM1 MA_DM[0] MA_DATA[19] DDRA_SDQ20 DDRB_SDM2 MB_DM[1] MB_DATA[20] DDRB_SDQ21
D20 MA_DM[1] MA_DATA[20] E23 C28 MB_DM[2] MB_DATA[21] B27
DDRA_SDM2 E25 D24 DDRA_SDQ21 DDRB_SDM3 D31 A30 DDRB_SDQ22
DDRA_SDM3 MA_DM[2] MA_DATA[21] DDRA_SDQ22 DDRB_SDM4 MB_DM[3] MB_DATA[22] DDRB_SDQ23
F30 MA_DM[3] MA_DATA[22] D26 AM31 MB_DM[4] MB_DATA[23] C30
DDRA_SDM4 AK29 D27 DDRA_SDQ23 DDRB_SDM5 AN30
DDRA_SDM5 MA_DM[4] MA_DATA[23] DDRB_SDM6 MB_DM[5] DDRB_SDQ24
AL25 MA_DM[5] AR24 MB_DM[6] MB_DATA[24] B33
DDRA_SDM6 AM20 G28 DDRA_SDQ24 DDRB_SDM7 AN18 C32 DDRB_SDQ25
DDRA_SDM7 MA_DM[6] MA_DATA[24] DDRA_SDQ25 MB_DM[7] MB_DATA[25] DDRB_SDQ26
AM16 MA_DM[7] MA_DATA[25] G29 MB_DATA[26] F33
H27 DDRA_SDQ26 DDRB_SDQS0 B18 F32 DDRB_SDQ27
MA_DATA[26] 12 DDRB_SDQS0 MB_DQS_H[0] MB_DATA[27]
DDRA_SDQS0 G17 J29 DDRA_SDQ27 DDRB_SDQS0# A18 B32 DDRB_SDQ28
11 DDRA_SDQS0 MA_DQS_H[0] MA_DATA[27] 12 DDRB_SDQS0# MB_DQS_L[0] MB_DATA[28]
DDRA_SDQS0# H17 E28 DDRA_SDQ28 DDRB_SDQS1 B24 C31 DDRB_SDQ29
11 DDRA_SDQS0# MA_DQS_L[0] MA_DATA[28] 12 DDRB_SDQS1 MB_DQS_H[1] MB_DATA[29]
DDRA_SDQS1 F22 F27 DDRA_SDQ29 DDRB_SDQS1# A24 E32 DDRB_SDQ30
11 DDRA_SDQS1 MA_DQS_H[1] MA_DATA[29] 12 DDRB_SDQS1# MB_DQS_L[1] MB_DATA[30]
DDRA_SDQS1# G22 H29 DDRA_SDQ30 DDRB_SDQS2 B30 F31 DDRB_SDQ31
11 DDRA_SDQS1# MA_DQS_L[1] MA_DATA[30] 12 DDRB_SDQS2 MB_DQS_H[2] MB_DATA[31]
DDRA_SDQS2 E26 H28 DDRA_SDQ31 DDRB_SDQS2# B29
11 DDRA_SDQS2 MA_DQS_H[2] MA_DATA[31] 12 DDRB_SDQS2# MB_DQS_L[2]
DDRA_SDQS2# F26 DDRB_SDQS3 D32 AK32 DDRB_SDQ32
2 11 DDRA_SDQS2# MA_DQS_L[2] 12 DDRB_SDQS3 MB_DQS_H[3] MB_DATA[32]
DDRA_SDQS3 H30 AH29 DDRA_SDQ32 DDRB_SDQS3# D33 AL32 DDRB_SDQ33 2
11 DDRA_SDQS3 MA_DQS_H[3] MA_DATA[32] 12 DDRB_SDQS3# MB_DQS_L[3] MB_DATA[33]
DDRA_SDQS3# G30 AJ30 DDRA_SDQ33 DDRB_SDQS4 AM32 AP32 DDRB_SDQ34
11 DDRA_SDQS3# MA_DQS_L[3] MA_DATA[33] 12 DDRB_SDQS4 MB_DQS_H[4] MB_DATA[34]
DDRA_SDQS4 AL29 AM28 DDRA_SDQ34 DDRB_SDQS4# AM33 AN31 DDRB_SDQ35
11 DDRA_SDQS4 MA_DQS_H[4] MA_DATA[34] 12 DDRB_SDQS4# MB_DQS_L[4] MB_DATA[35]
DDRA_SDQS4# AL30 AM27 DDRA_SDQ35 DDRB_SDQS5 AN28 AK31 DDRB_SDQ36
11 DDRA_SDQS4# MA_DQS_L[4] MA_DATA[35] 12 DDRB_SDQS5 MB_DQS_H[5] MB_DATA[36]
DDRA_SDQS5 AH25 AH27 DDRA_SDQ36 DDRB_SDQS5# AP29 AK33 DDRB_SDQ37
11 DDRA_SDQS5 MA_DQS_H[5] MA_DATA[36] 12 DDRB_SDQS5# MB_DQS_L[5] MB_DATA[37]
DDRA_SDQS5# AJ25 AH28 DDRA_SDQ37 DDRB_SDQS6 AP23 AN32 DDRB_SDQ38
11 DDRA_SDQS5# MA_DQS_L[5] MA_DATA[37] 12 DDRB_SDQS6 MB_DQS_H[6] MB_DATA[38]
DDRA_SDQS6 AK20 AJ29 DDRA_SDQ38 DDRB_SDQS6# AP24 AP33 DDRB_SDQ39
11 DDRA_SDQS6 MA_DQS_H[6] MA_DATA[38] 12 DDRB_SDQS6# MB_DQS_L[6] MB_DATA[39]
DDRA_SDQS6# AL20 AK27 DDRA_SDQ39 DDRB_SDQS7 AR18
11 DDRA_SDQS6# MA_DQS_L[6] MA_DATA[39] 12 DDRB_SDQS7 MB_DQS_H[7]
DDRA_SDQS7 AK15 DDRB_SDQS7# AP18 AP30 DDRB_SDQ40
11 DDRA_SDQS7 MA_DQS_H[7] 12 DDRB_SDQS7# MB_DQS_L[7] MB_DATA[40]
DDRA_SDQS7# AL15 AK26 DDRA_SDQ40 AR30 DDRB_SDQ41
11 DDRA_SDQS7# MA_DQS_L[7] MA_DATA[40] MB_DATA[41]
AJ26 DDRA_SDQ41 DDRB_CLK0 W32 AP27 DDRB_SDQ42
MA_DATA[41] 12 DDRB_CLK0 MB_CLK_H[0] MB_DATA[42]
DDRA_CLK0 W29 AK23 DDRA_SDQ42 DDRB_CLK0# Y32 AN26 DDRB_SDQ43
11 DDRA_CLK0 MA_CLK_H[0] MA_DATA[42] 12 DDRB_CLK0# MB_CLK_L[0] MB_DATA[43]
DDRA_CLK0# Y30 AJ23 DDRA_SDQ43 DDRB_CLK1 V33 AR32 DDRB_SDQ44
11 DDRA_CLK0# MA_CLK_L[0] MA_DATA[43] 12 DDRB_CLK1 MB_CLK_H[1] MB_DATA[44]
DDRA_CLK1 W26 AM26 DDRA_SDQ44 DDRB_CLK1# V32 AP31 DDRB_SDQ45
11 DDRA_CLK1 MA_CLK_H[1] MA_DATA[44] 12 DDRB_CLK1# MB_CLK_L[1] MB_DATA[45]
DDRA_CLK1# W27 AL26 DDRA_SDQ45 U32 AR28 DDRB_SDQ46
11 DDRA_CLK1# MA_CLK_L[1] MA_DATA[45] MB_CLK_H[2] MB_DATA[46]
U29 AM24 DDRA_SDQ46 V31 AP28 DDRB_SDQ47
MA_CLK_H[2] MA_DATA[46] DDRA_SDQ47 MB_CLK_L[2] MB_DATA[47]
V30 MA_CLK_L[2] MA_DATA[47] AL23 T33 MB_CLK_H[3]
U26 T32 AP25 DDRB_SDQ48
MA_CLK_H[3] DDRA_SDQ48 MB_CLK_L[3] MB_DATA[48] DDRB_SDQ49
U27 MA_CLK_L[3] MA_DATA[48] AK22 MB_DATA[49] AN24
AH22 DDRA_SDQ49 DDRB_CKE0 H32 AR22 DDRB_SDQ50
MA_DATA[49] 12 DDRB_CKE0 MB_CKE[0] MB_DATA[50]
DDRA_CKE0 L29 AK19 DDRA_SDQ50 DDRB_CKE1 H33 AP21 DDRB_SDQ51
11 DDRA_CKE0 MA_CKE[0] MA_DATA[50] 12 DDRB_CKE1 MB_CKE[1] MB_DATA[51]
DDRA_CKE1 K30 AH19 DDRA_SDQ51 AP26 DDRB_SDQ52
11 DDRA_CKE1 MA_CKE[1] MA_DATA[51] MB_DATA[52]
AM22 DDRA_SDQ52 DDRB_ODT0 AF31 AR26 DDRB_SDQ53
MA_DATA[52] 12 DDRB_ODT0 MB0_ODT[0] MB_DATA[53]
DDRA_ODT0 AD30 AL22 DDRA_SDQ53 DDRB_ODT1 AH31 AN22 DDRB_SDQ54
11 DDRA_ODT0 MA0_ODT[0] MA_DATA[53] 12 DDRB_ODT1 MB0_ODT[1] MB_DATA[54]
DDRA_ODT1 AG28 AJ20 DDRA_SDQ54 AE32 AP22 DDRB_SDQ55
11 DDRA_ODT1 MA0_ODT[1] MA_DATA[54] MB1_ODT[0] MB_DATA[55]
AE26 AL19 DDRA_SDQ55 AH33
MA1_ODT[0] MA_DATA[55] MB1_ODT[1] DDRB_SDQ56
AG29 MA1_ODT[1] MB_DATA[56] AR20
AK17 DDRA_SDQ56 DDRB_SCS0# AD31 AP19 DDRB_SDQ57
MA_DATA[56] 12 DDRB_SCS0# MB0_CS_L[0] MB_DATA[57]
DDRA_SCS0# AD26 AJ17 DDRA_SDQ57 DDRB_SCS1# AF32 AP16 DDRB_SDQ58
11 DDRA_SCS0# MA0_CS_L[0] MA_DATA[57] 12 DDRB_SCS1# MB0_CS_L[1] MB_DATA[58]
DDRA_SCS1# AE29 AK14 DDRA_SDQ58 AC32 AR16 DDRB_SDQ59
11 DDRA_SCS1# MA0_CS_L[1] MA_DATA[58] MB1_CS_L[0] MB_DATA[59]
AB30 AH14 DDRA_SDQ59 AG32 AN20 DDRB_SDQ60
MA1_CS_L[0] MA_DATA[59] DDRA_SDQ60 MB1_CS_L[1] MB_DATA[60] DDRB_SDQ61
AF30 MA1_CS_L[1] MA_DATA[60] AM18 MB_DATA[61] AP20
3 DDRA_SDQ61 DDRB_SRAS# DDRB_SDQ62 3
MA_DATA[61] AL17 12 DDRB_SRAS# AB32 MB_RAS_L MB_DATA[62] AP17
DDRA_SRAS# AB29 AH15 DDRA_SDQ62 DDRB_SCAS# AD32 AN16 DDRB_SDQ63
11 DDRA_SRAS# MA_RAS_L MA_DATA[62] 12 DDRB_SCAS# MB_CAS_L MB_DATA[63]
DDRA_SCAS# AD29 AL14 DDRA_SDQ63 DDRB_SWE# AD33
11 DDRA_SCAS# MA_CAS_L MA_DATA[63] 12 DDRB_SWE# MB_WE_L
DDRA_SWE# AD28
11 DDRA_SWE# MA_WE_L MEM_MB_RST# H31
12 MEM_MB_RST# MB_RESET_L
MEM_MA_RST# J28 MEM_MB_EVENT# Y31
11 MEM_MA_RST# MA_RESET_L 12 MEM_MB_EVENT# MB_EVENT_L
MEM_MA_EVENT# AA26
11 MEM_MA_EVENT# MA_EVENT_L
TRINITY-A8-SERIES_BGA813
+MEM_VREF G32 M_VREF

+1.5V 1 2 M_ZVDDIO AJ32 M_ZVDDIO

RC3 39.2_0402_1%
TRINITY-A8-SERIES_BGA813

L M_ZVDDIO W/S=8/12 mil, <1000mil 0.75V reference voltage

+1.5V

2
RC4 L +MEM_VREF 15mil
Close to JCPU1
EVENT# pull high 1K_0402_1%

1
+1.5V +MEM_VREF

2
1 2
RC5 CC45
RC6 1 2 1K_0402_5% MEM_MA_EVENT# 1K_0402_1% CC46
1000P_0402_50V7K .1U_0402_16V7K
2 1
RC7 1 2 1K_0402_5% MEM_MB_EVENT#

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD FP2 DDRIII I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 7 of 47

A B C D E
 A B C D E

Place near APU

L Close to APU (JCPU1)
UCPU1D DP0_AUXP 2 1
CC47 1 2 .1U_0402_16V7K DP0_TXP0 H2 M5 DP0_AUXP CC48 1 2 .1U_0402_16V7K To LVDS Translator RC8 1.8K_0402_5%
18 DP0_TXP0_C DP0_TXP[0] DP0_AUXP DP0_AUXP_C 18
CC49 1 2 .1U_0402_16V7K DP0_TXN0 H1 M6 DP0_AUXN CC50 1 2 .1U_0402_16V7K DP0_AUXN 2 1
18 DP0_TXN0_C DP0_TXN[0] DP0_AUXN DP0_AUXN_C 18
To LVDS RC9 1.8K_0402_5%
Translator H3 L5

DISPLAY PORT 0
DP0_TXP[1] DP1_AUXP
H4 DP0_TXN[1] DP1_AUXN L6 12/19 del CC141/CC142, RC10, RC11
F4 J5 APU_HDMI_CLK
DP0_TXP[2] DP2_AUXP APU_HDMI_CLK 20
F3 J6 APU_HDMI_DATA To HDMI
DP0_TXN[2] DP2_AUXN APU_HDMI_DATA 20
F1 DP0_TXP[3] DP3_AUXP P5
F2 DP0_TXN[3] DP3_AUXN P6
1 1

DISPLAY PORT MISC.

E2 DP1_TXP[0] DP4_AUXP R5
E1 DP1_TXN[0] DP4_AUXN R6

D4 U5

DISPLAY PORT 1
+1.5V DP1_TXP[1] DP5_AUXP
D3 DP1_TXN[1] DP5_AUXN U6

D1 M7 DP0_HPD LVDS/eDP
DP1_TXP[2] DP0_HPD DP0_HPD 10
RC12 1 2 1K_0402_5% APU_SIC D2 L7
DP1_TXN[2] DP1_HPD DP2_HPD
DP2_HPD J7 DP2_HPD 20 HDMI
RC13 1 2 1K_0402_5% APU_SID C1 P7
DP1_TXP[3] DP3_HPD
C2 DP1_TXN[3] DP4_HPD R7
RC14 1 2 1K_0402_5% ALERT_L U7
DP5_HPD
20 APU_HDMI_TXD2+ B2 DP2_TXP[0]
A2 C6 DP_ENBKL VDDIO level
20 APU_HDMI_TXD2- DP2_TXN[0] DP_BLON DP_ENBKL 10
DP_DIGON D7 Need Level shift
RC15 2 1 1K_0402_5% ALLOW_STOP B3 A6 DP_INT_PWM

DISPLAY PORT 2
20 APU_HDMI_TXD1+ DP2_TXP[1] DP_VARY_BL DP_INT_PWM 10
RC16 2
To HDMI 20 APU_HDMI_TXD1- A3 DP2_TXN[1]
1 1K_0402_5% DP_AUX_ZVSS B6 DP_AUX_ZVSS RC17 1 2 150_0402_1%
@
Allow_STOP leakage issue
20 APU_HDMI_TXD0+
20 APU_HDMI_TXD0-
B4
A4
DP2_TXP[2]
DP2_TXN[2] TEST6 AL6 L DP_AUX_ZVSS W/S=8/12 mil, <3000mil
TEST9 Y23 TC1
+1.5V_PCIE B5 V23
+1.5V 20 APU_HDMI_TXC+ DP2_TXP[3] TEST10 TC2
20 APU_HDMI_TXC- A5 DP2_TXN[3] TEST14 G9 TC3
1 @ 2 F9 TC4
RC77 0_0402_5% APU_CLKP TEST15
13 APU_CLKP AL9 CLKIN_H TEST16 E9 TC5 10/27 add TP.
1 2 100MHz APU_CLKN AK9 G8 TC6
13 APU_CLKN CLKIN_L TEST17
RC78 0_0402_5% F12 APU_TEST18 RC20 1 2 1K_0402_5%

TEST
TEST18
100MHz APU_DISP_CLKP APU_TEST19 RC21 1K_0402_5%

CLK
13 APU_DISP_CLKP AL7 DISP_CLKIN_H TEST19 E12 1 2
RC18 2 1 300_0402_5% APU_RST# NSS APU_DISP_CLKN AK7 F14 APU_TEST20 RC23 1 2 1K_0402_5%
13 APU_DISP_CLKN DISP_CLKIN_L TEST20
G12 APU_TEST24 RC24 1 2 1K_0402_5%
RC19 2 APU_PWRGD APU_SVC TEST24 TEST25_H
1 300_0402_5% 42 APU_SVC E5 SVC TEST25_H AJ8 RC26 1 2 510_0402_1% TEST35 change to PU for
2 SVI 2.0 APU_SVD E6 AH8 TEST25_L RC27 1 2 510_0402_1% 2
42 APU_SVD SVD TEST25_L +1.2VS HDMI can not output
RC22 1 @ 2 1K_0402_5% APU_SVC (0 ohm G14
TEST28_H 20110126

SER.
APU_SVT D6 H14
RC25 1 @
at Power Side)42 APU_SVT SVT TEST28_L
2 1K_0402_5% APU_SVD
TEST30_H V25 TC7
APU_SIC AJ11 Y25 TC8
RC28 1 @ SIC TEST30_L
2 1K_0402_5% APU_SVT SB-TSI (S5 Domain) APU_SID AH11 SID TEST31 AH32 M_TEST RC29 1 @ 2 39.2_0402_1% +1.5V
Check TEST32_H R25 TC9 RC30 1 2 39.2_0402_1%
APU_RST# RC31 1 2 0_0402_5% APU_RST#_APU AK11 T25 TC10
13 APU_RST# RESET_L TEST32_L
For ESD request close APU side 13,42 APU_PWRGD
APU_PWRGD RC32 1 2 0_0402_5% APU_PWRGD_APU AH9 PWROK TEST35 AL5 TEST35 RC33 1 2 300_0402_5% +1.5V
RC34 1 @ 2 300_0402_5%
RC35 2 1 0_0402_5% APU_PROCHOT# AL12 AP10 ALLOW_STOP

CTRL
36 H_PROCHOT# PROCHOT_L DMAACTIVE_L ALLOW_STOP 13
@ APU_THERMTRIP# AK5
APU_RST# ALERT_L THERMTRIP_L
AR10 ALERT_L TEST4 T23 TC11
CC53 33P_0402_50V8J R23 TC12 TEST35 change to PU for
APU_PWRGD APU_TDI TEST5
E11 TDI HDMI can not output
CC54 33P_0402_50V8J APU_TDO G11
APU_PROCHOT# APU_TCK TDO 20110126
2 1 H12 TCK
CC55 22P_0402_50V8J Internal PU when no use HDT APU_TMS F11 L8

JTAG
APU_THERMTRIP# APU_TRST# TMS RSVD
2 1 H11 TRST_L RSVD P8
CC56 22P_0402_50V8J APU_DBRDY E8 AH12 12/15 change to +1.5V
APU_DBREQ# DBRDY RSVD +1.5V
E7 AJ12 Close to Header

RSVD
DBREQ_L RSVD
RSVD AK12
42 APU_VDD_RUN_FB_L G6 VSS_SENSE
H6 RC36 1 2 1K_0402_5% APU_TDI
APU_VDDNB_SEN VDDP_SENSE
42 APU_VDDNB_SEN H5 VDDNB_SENSE
APU_CLKP RC37 1 2 1K_0402_5% APU_TCK

SENSE
2 1 G7 VDDIO_SENSE
CC1622 122P_0402_50V8J APU_CLKN APU_VDD_SEN G5
42 APU_VDD_SEN VDD_SENSE
CC163 22P_0402_50V8J H7 RC38 1 2 1K_0402_5% APU_TMS
APU_DISP_CLKP VDDR_SENSE
2 1
CC1642 122P_0402_50V8J APU_DISP_CLKN TRINITY-A8-SERIES_BGA813 RC39 1 2 1K_0402_5% APU_TRST#
CC165 22P_0402_50V8J Route as differential with APU_VDD_RUN_FB_L
RC40 1 2 1K_0402_5% APU_DBREQ#
3 12/19 RF request 3
10/27 300 ohm??

CPU TSI interface level shift Asserted as an input to +1.5V +3VS

HDT Debug conn
force processor into 12/19 remove damping 0ohm.
BSH111, the Vgs is: HTC-active state
min = 0.4V

1
Max = 1.3V 12/15 change to +1.5V
2

CC57 1 2 0.1U_0402_16V4Z RC41 RC42 +1.5V

RC43 10K_0402_5% 10K_0402_5%
TC13
1K_0402_5% RC46 JP15
+3VS 1 RC44 2 1 RC45 2 When APU High -> MOS OFF (Vgs < 0.4V ) 1 2 1 2 APU_TCK
1 2

2 2

2
APU Low -> MOS ON (Vgs > 1.3V) 0_0603_5%
1

31.6K_0402_1% 30K_0402_1% 3 4 APU_TMS

B
RC49 QC1 3 4
APU_PROCHOT# 1 2 1 3 5 6 APU_TDI
E
EC_THERM# 13,29,36,42 5 6
Vg = 1.607 V
C
2
G

QC2 0_0402_5% MMBT3904_SOT23-3 7 8 APU_TDO

+1.5V 7 8
APU_SID 3 1 EC_SMB_DA2 APU_TRST# 9 10 APU_PWRGD
EC_SMB_DA2 27,29 9 10
THERMTRIP shutdown Indicates to the FCH that a thermal trip
S

BSH111_SOT23-3 temperature: 115 degree has occurred. Its assertion will cause the FCH 11 12 APU_RST#
11 12
1

to transition the system to S5 immediately APU_DBRDY

13 13 14 14
2

15 16 APU_DBREQ#
15 16
2
G

QC3 RC59 RC56

2 2

1K_0402_5% 10K_0402_5% 17 18 APU_TEST19

APU_SIC EC_SMB_CK2 17 18
B

3 1 EC_SMB_CK2 27,29
1

QC4 19 20 APU_TEST18
S

BSH111_SOT23-3 APU_THERMTRIP# 19 20
E

3 1 1 2 H_THERMTRIP# 15
4 4
C

RC64 0_0402_5%
MMBT3904_SOT23-3 1 2 MAINPWON 36,37
RC65 @ 0_0402_5% SAMTE_ASP-136446-07-B
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD FP2 Display / MISC / HDT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 8 of 47

A B C D E
 A B C D E

Power Name Consumption +APU_CORE Decoupling

VDD
+CPU_CORE 60A On power team page
330uF x 4 @ x1
VDDNB 22uF x 10 UCPU1F

+CPU_CORE_NB 37A 0.22uF x2 A17

A19
VSS VSS Y11
Y12
0.01uF x3 VSS VSS
VDDIO A21 VSS VSS Y14
+1.5V 3.2A 180pF x2 @ x1 A23
A25
VSS VSS Y15
Y17
VSS VSS
VDDP / VDDR A27 VSS VSS Y19
+1.2VS 5A / 3.5A +APU_CORE_NB Decoupling
A29
A31
VSS VSS Y20
Y22
VSS VSS
VDDA B1 VSS VSS AA4
1 1
+2.5VS 0.75A 330uF x2
C3
C4
VSS VSS AA5
AB7
VSS VSS
On power team page 22uF x2 @ x2
C33 VSS VSS AB8
D5 VSS VSS AC1
10uF x1 D9 VSS VSS AC2
D11 VSS VSS AC4
0.22uF x2 D13 VSS VSS AC9
180pF x3 D15 VSS VSS AC11
D17 VSS VSS AC12
D19 VSS VSS AC14
+APU_CORE +APU_CORE D21 AC15
UCPU1E VSS VSS
D23 VSS VSS AC17
J12 VDD VDD V17 D25 VSS VSS AC19
J14 VDD VDD V19 D30 VSS VSS AC20
J15 VDD VDD V20 E4 VSS VSS AC22
J17 VDD VDD V22 Decoupling between CPU and DIMMs E27 VSS VSS AC23
J19 VDD VDD W8 across VDDIO and VSS split E29 VSS VSS AC25
J20 VDD VDD AA8 E30 VSS VSS AE4
J22 VDD VDD AA9 E33 VSS VSS AF9
M11 VDD VDD AA11 +1.5V +1.5V F5 VSS VSS AF11
M12 VDD VDD AA12 +1.5V / VDDIO Decoupling F6 VSS VSS AF12

CC94

CC95

CC96

CC97

CC98

CC99

CC100

CC101

CC102

CC103

CC104

CC105

CC106

CC107

CC149

CC150

CC151

CC152

CC108

CC109

CC153

CC154

CC93

CC148

CC146

CC145

CC147

CC143

CC144

CC110

CC111

CC112

CC113
M14 VDD VDD AA14 1 F7 VSS VSS AF14
M15 VDD VDD AA15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F8 VSS VSS AF15
+
M17 VDD VDD AA17 330uF x1 F17 VSS VSS AF17
M19 AA19 F20 AF19
VDD VDD 22uF x4 VSS VSS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

330U_D2_2V_Y

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

180P_0402_50V8J

180P_0402_50V8J
M20 VDD VDD AA20 F23 VSS VSS AF20
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
M22 VDD VDD AA22 4.7uF x4 F28 VSS VSS AF22
R8 VDD VDD AD9 F29 VSS VSS AF23
R9 VDD VDD AD11 0.22uF x6 G1 VSS VSS AF25
R11 VDD VDD AD12 180pF x1 @x1 G2 VSS VSS AG1
R12 VDD VDD AD14 G4 VSS VSS AG2
R14 VDD VDD AD15 G15 VSS VSS AG4
2 2
R15 VDD VDD AD17 G19 VSS VSS AG9
R17 VDD VDD AD19 G25 VSS VSS AG11
R19 VDD VDD AD20 G26 VSS VSS AG26
R20 VDD VDD AD22 +1.2VS VDDR Decoupling G27 VSS VSS AH7
R22 AG12 G33 AH17
VDD VDD Close JCPU1.AG10,AH8,AH9,AH10 VSS VSS
CC114

CC115

CC116

CC158

CC156

CC157

CC117

CC118

CC155

CC119

CC120

CC121
U8 VDD VDD AG14 H8 VSS VSS AH20
V9 VDD VDD AG15 1 1 1 1 1 1 1 1 1 1 1 1 H9 VSS VSS AH23
V11 AG17 12/22 for RF request H22 AH26
V12
VDD VDD
AG19 10uF x2 H26
VSS VSS
AH30
VDD VDD VSS VSS
10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

.01U_0402_16V7K

.01U_0402_16V7K

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1000P_0402_50V7K

1000P_0402_50V7K

180P_0402_50V8J

180P_0402_50V8J
V14 VDD VDD AG20
2 2 2 2 2 2 2 2 2 2 2 2 0.22uF x2 +APU_CORE_NB
J4 VSS VSS AJ4
V15 VDD VDD AG22 J8 VSS VSS AJ5
1000pF x1 @X1 J9 VSS VSS AJ6
180pF x2 J11 VSS VSS AJ7
+APU_CORE_NB A7 VDDNB VDDNB B11 +APU_CORE_NB J23 VSS VSS AJ9
A8 VDDNB VDDNB B12 0.01uFx2 J25 VSS VSS AJ14
A9 VDDNB VDDNB B13 4.7uFx2 J26 VSS VSS AJ15
A10 VDDNB VDDNB B14 J27 VSS VSS AJ19
A11 B15 VDDP_CAP J30 AJ22
VDDNB VDDNB VSS VSS
A12 VDDNB VDDNB C8 K9 VSS VSS AJ27
A13 C10 @ +1.2VS K11 AJ28
VDDNB VDDNB +1.2VS 1 1 1 1 VSS VSS
C120 C121 C122 C123

CC122

CC123
A14 VDDNB VDDNB C12 VDDP Decoupling K12 VSS VSS AJ33
CC124

CC125

CC126

CC127

CC128

CC129

CC130

CC159

CC131

CC132

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J
CC133
A15 C14 1 1 K14 AK6
B7
VDDNB VDDNB
D8 1 1 1 1 1 1 1 1 1 1 Close JCPU1.AH3~7 1 K15
VSS VSS
AK8
VDDNB VDDNB 2 2 2 2 VSS VSS
B8 VDDNB VDDNB D10 K17 VSS VSS AK25
+

22U_0805_6.3V6M

22U_0805_6.3V6M
B9 D12 K19 AK28
VDDNB VDDNB 22uF x4 2 2 VSS VSS
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1000P_0402_50V7K

1000P_0402_50V7K

180P_0402_50V8J

180P_0402_50V8J
B10 VDDNB VDDNB D14 K20 VSS VSS AK30
2 2 2 2 2 2 2 2 2 2
0.22uF x2 K22 AL1

220U_D2_2VY_R15M
VDDNB_CAP 2 VSS VSS
VDDNB_CAP M9 L1 VSS VSS AL2
VDDNB_CAP N9 1000pF @x1 L2 VSS VSS AL4
CC134

CC135

CC161

CC160

CC136

180pF x2 L4 VSS VSS AL8

+1.5V J33 VDDIO VDDIO W33 1 1 1 1 1 M8 VSS VSS AL11
K23 VDDIO VDDIO AA23 M23 VSS VSS AL27
3 3
K25 VDDIO VDDIO AA25 M25 VSS VSS AL28
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

180P_0402_50V8J

L28 VDDIO VDDIO AA27

2 2 2 2 2 220uF x1 N4 VSS VSS AL33
L30 VDDIO VDDIO AA30 N11 VSS VSS AM5
L33 AA33 FBMA-L11-201209-221LMA30T_0805 N12 AM7
VDDIO VDDIO LC1 VSS VSS
M27 VDDIO VDDIO AB28 N14 VSS VSS AM9
N23 VDDIO VDDIO AC30 +2.5VS 2 1 +APU_VDDA N15 VSS VSS AM11
N25 VDDIO VDDIO AC33 N17 VSS VSS AM15
CC137

CC138

CC139

CC140

N30 VDDIO VDDIO AD23 N19 VSS VSS AM17

N33 VDDIO VDDIO AD25 1 1 1 1 VDDA Decoupling N20 VSS VSS AM19
P28 VDDIO VDDIO AD27 N22 VSS VSS AM21
R27 VDDIO VDDIO AE28
Northbridge Power Pins Power Sequence of APU R1 VSS VSS AM23
47U_0805_4V6

0.22U_0402_10V4Z

3300P_0402_50V7-K

1000P_0402_50V7K

R30 VDDIO VDDIO AE30

2 2 2 2 47uF x1 R2 VSS VSS AM25
R33 AE33 for Remote Decoupling R4 AM29
VDDIO VDDIO 0.22uF x1 VSS VSS
U28
U30
VDDIO VDDIO AG23
AG25 3300pF x1
+1.5V T9
T11
VSS VSS AM30
AN3
VDDIO VDDIO VSS VSS
U33 VDDIO VDDIO AG27 T12 VSS VSS AN4
W28 VDDIO VDDIO AG30 1000pF x1 T14 VSS VSS AN33
W30 VDDIO VDDIO AG33 +1.5V VDDIO: 3200mA +2.5VS Group A T15 VSS VSS AP5
T17 VSS VSS AP9
+1.2VS AM12 VDDP VDDR AN14 +1.2VS T19 VSS VSS AR2

VDDP: 5000mA
AN12 VDDP VDDR AP14 VDDR: 3500mA Change 180p to 1000p by AMD T20 VSS VSS AR5
AP12
AP13
VDDP VDDR AP15
AR14
+1.5VS T22
U4
VSS VSS AR9
AR17
VDDP VDDR VSS VSS
AR12 VDDP VDDR AR15 W1 VSS VSS AR19
AR13 VDDP W2 VSS VSS AR21

VDDP_CAP AA6
+CPU_CORE W4
W5
VSS VSS AR23
AR25
VDDP_CAP VSS VSS
AA7 VDDP_CAP W6 VSS VSS AR27
W7 VSS VSS AR29
+APU_VDDA AM13 VDDA Group B Y9 VSS VSS AR31

VDDA: 750mA
AM14 VDDA +CPU_CORE_NB TRINITY-A8-SERIES_BGA813
4 4
TRINITY-A8-SERIES_BGA813
Decoupling Caps.
+1.2VS
Pop / @ 330uF 220uF 47uF 22uF 10uF 4.7uF 0.22uF 0.01uF 3300pF 1nF 180pF
Pumori 2.0 0 19/11 7 5 17 3 1 1/1 13/3 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title
Comal 7/2 1 1 19/11 7 4 17 3 1 1/1 14/2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD FP2 PWR / GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
P5WS5 7/2 1 1 13 3 8 19 3 1 4 16 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 9 of 47

A B C D E
 5 4 3 2 1

Panel ENBKL
HPD +3VS

Del reserved NMOS

1
2
RC66
D 4.7K_0402_5% D
Translator and eDP HPD RC67 DC1 @

2
From Translator or Conn. 100K_0402_5% 2 1 PLT_RST# 13,29,31

6
LVDS_HPD RC68 1 DP0_HPD RB751V-40_SOD323-2
18 LVDS_HPD 2 0_0402_5% DP0_HPD 8
Q1A
2N7002KDW_SOT363-6
2

MMBT3904_SOT23-3
1
QC6 C

1
8 DP_ENBKL 1 2 2
RC69 2.2K_0402_5% B

2
E

3
RC70
100K_0402_5%

1
DP_ENBKL RC71 1 @ 2 0_0402_5% ENBKL ENBKL 19,29

Reserved RC71
Del reserved NMOS
Del VGA_ENBKL

C eDP Panel ENVDD C

12/06 Del FCH_CRT_HPD

Del eDP panel control

B B
+3VS
Panel PWM

1
1
RC73
4.7K_0402_5%
RC74

2
47K_0402_5%
APU_INVT_PWM 18

3
Q1B

5 2N7002KDW_SOT363-6

RC75

4
1
2.2K_0402_5% C
1 2 2 QC8
8 DP_INT_PWM B
E

3
1

MMBT3904_SOT23-3

RC76
4.7K_0402_5%
2

A A

Security Classification Compal Secret Data

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title
AMD FP2 Singal Level Shifter
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 10 of 47

5 4 3 2 1
 5 4 3 2 1

L +VREF_DQ 15mil
DDR3 SO-DIMM A
+V_DDR_REFA +1.5V +1.5V

All VREF traces should JDIMM1

have 20 mil trace width +V_DDR_REFA 1 2
VREF_DQ VSS1 DDRA_SDQ4
3 VSS2 DQ4 4
DDRA_SDQ0 DDRA_SDQ5

0.1U_0402_16V7K

2.2U_0603_6.3V6K
CD2
5 DQ0 DQ5 6
DDRA_SDQ1

CD1
D 1 1 7 DQ1 VSS3 8 D
DDRA_SDQ[0..63] 9 10 DDRA_SDQS0#
7 DDRA_SDQ[0..63] VSS4 DQS#0 DDRA_SDQS0# 7
DDRA_SDM0 11 12 DDRA_SDQS0
DDRA_SDM[0..7] DM0 DQS0 DDRA_SDQS0 7
7 DDRA_SDM[0..7] 13 VSS5 VSS6 14
2 2 DDRA_SDQ2 DDRA_SDQ6
15 DQ2 DQ6 16
DDRA_SMA[0..15] DDRA_SDQ3 17 18 DDRA_SDQ7
7 DDRA_SMA[0..15] DQ3 DQ7
19 VSS7 VSS8 20
DDRA_SDQ8 21 22 DDRA_SDQ12
DDRA_SDQ9 DQ8 DQ12 DDRA_SDQ13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDRA_SDQS1# 27 28 DDRA_SDM1
7 DDRA_SDQS1# DQS#1 DM1
DDRA_SDQS1 29 30 MEM_MA_RST#
7 DDRA_SDQS1 DQS1 RESET# MEM_MA_RST# 7
31 VSS11 VSS12 32
DDRA_SDQ10 33 34 DDRA_SDQ14
DDRA_SDQ11 DQ10 DQ14 DDRA_SDQ15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDRA_SDQ16 39 40 DDRA_SDQ20
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDRA_SDQS2# 45 46 DDRA_SDM2
7 DDRA_SDQS2# DQS#2 DM2
DDRA_SDQS2 47 48
+1.5V 7 DDRA_SDQS2 DQS2 VSS17
49 50 DDRA_SDQ22
DDRA_SDQ18 VSS18 DQ22 DDRA_SDQ23
51 DQ18 DQ23 52
DDRA_SDQ19 53 54
DQ19 VSS19
1

55 56 DDRA_SDQ28
RD1 DDRA_SDQ24 VSS20 DQ28 DDRA_SDQ29
57 DQ24 DQ29 58
1K_0402_1% DDRA_SDQ25 59 60
+V_DDR_REFA DQ25 VSS21 DDRA_SDQS3#
61 VSS22 DQS#3 62 DDRA_SDQS3# 7
DDRA_SDM3 63 64 DDRA_SDQS3
DM3 DQS3 DDRA_SDQS3 7
2

65 VSS23 VSS24 66
DDRA_SDQ26 67 68 DDRA_SDQ30
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31
69 DQ27 DQ31 70
1

71 VSS25 VSS26 72
RD2
1K_0402_1%

DDRA_CKE0 73 74 DDRA_CKE1
7 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 7
2

75 VDD1 VDD2 76
C 77 78 DDRA_SMA15 C
DDRA_SBS2# NC1 A15 DDRA_SMA14
7 DDRA_SBS2# 79 BA2 A14 80
81 VDD3 VDD4 82
DDRA_SMA12 83 84 DDRA_SMA11
DDRA_SMA9 A12/BC# A11 DDRA_SMA7
85 A9 A7 86
87 VDD5 VDD6 88
DDRA_SMA8 89 90 DDRA_SMA6
DDRA_SMA5 A8 A6 DDRA_SMA4
91 A5 A4 92
93 VDD7 VDD8 94
DDRA_SMA3 95 96 DDRA_SMA2
DDRA_SMA1 A3 A2 DDRA_SMA0
97 A1 A0 98
99 VDD9 VDD10 100
DDRA_CLK0 101 102 DDRA_CLK1
7 DDRA_CLK0 CK0 CK1 DDRA_CLK1 7
Layout Note: DDRA_CLK0# 103 104 DDRA_CLK1#
7 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 7 +1.5V
105 106
Place near JDIMM1.203 & JDIMM1.204 DDRA_SMA10 107
VDD11 VDD12
108 DDRA_SBS1#
DDRA_SBS1# 7
DDRA_SBS0# A10/AP BA1 DDRA_SRAS#
7 DDRA_SBS0# 109 BA0 RAS# 110 DDRA_SRAS# 7
111 VDD13 VDD14 112

1
DDRA_SWE# 113 114 DDRA_SCS0#
7 DDRA_SWE# WE# S0# DDRA_SCS0# 7
DDRA_SCAS# 115 116 DDRA_ODT0 RD3
+0.75VS 7 DDRA_SCAS# CAS# ODT0 DDRA_ODT0 7
117 118 1K_0402_1%
DDRA_SMA13 VDD15 VDD16 DDRA_ODT1 +VREF_CA
119 A13 ODT1 120 DDRA_ODT1 7
DDRA_SCS1# 121 122
7 DDRA_SCS1# S1# NC2

2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126
CD3

1U_0402_6.3V6K

CD4

1U_0402_6.3V6K

CD5

CD6

CD7

10U_0603_6.3V6M

CD8

10U_0603_6.3V6M

CD9

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

127 VSS27 VSS28 128

DDRA_SDQ32 DDRA_SDQ36

0.1U_0402_16V7K
1 1 1 1 1 1 1 129 DQ32 DQ36 130

1
DDRA_SDQ33 DDRA_SDQ37

2.2U_0603_6.3V6K
CD11
131 DQ33 DQ37 132

CD10
133 134 1 1 RD4
DDRA_SDQS4# VSS29 VSS30 DDRA_SDM4 1K_0402_1%
7 DDRA_SDQS4# 135 DQS#4 DM4 136
2 2 2 2 2 2 2 DDRA_SDQS4
7 DDRA_SDQS4 137 DQS4 VSS31 138
139 140 DDRA_SDQ38
VSS32 DQ38

2
DDRA_SDQ34 DDRA_SDQ39 2 2
141 DQ34 DQ39 142
DDRA_SDQ35 143 144
DQ35 VSS33 DDRA_SDQ44
145 VSS34 DQ44 146
DDRA_SDQ40 147 148 DDRA_SDQ45
DDRA_SDQ41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDRA_SDQS5#
B VSS36 DQS#5 DDRA_SDQS5# 7 B
DDRA_SDM5 153 154 DDRA_SDQS5
DM5 DQS5 DDRA_SDQS5 7
155 VSS37 VSS38 156
DDRA_SDQ42 157 158 DDRA_SDQ46
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDRA_SDQ48 163 164 DDRA_SDQ52
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53
Layout Note: 165 DQ49 DQ53 166
167 168
Place near JDIMM1 7 DDRA_SDQS6#
DDRA_SDQS6# 169
VSS41 VSS42
170 DDRA_SDM6
DQS#6 DM6
Layout Note: Place these 4 Caps near Command 7 DDRA_SDQS6
DDRA_SDQS6 171 DQS6 VSS43 172
173 174 DDRA_SDQ54
and Control signals of DIMMA DDRA_SDQ50 175
VSS44 DQ54
176 DDRA_SDQ55
DDRA_SDQ51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDRA_SDQ60
+1.5V DDRA_SDQ56 VSS46 DQ60 DDRA_SDQ61
181 DQ56 DQ61 182
DDRA_SDQ57 183 184
DQ57 VSS47 DDRA_SDQS7#
185 VSS48 DQS#7 186 DDRA_SDQS7# 7
DDRA_SDM7 187 188 DDRA_SDQS7
DM7 DQS7 DDRA_SDQS7 7
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1 189 VSS49 VSS50 190

DDRA_SDQ58 DDRA_SDQ62
CD12

CD13

CD14

CD15

CD16

CD17

CD18

CD19

CD20

CD21

1 1 1 1 1 1 1 1 1 1 191 DQ58 DQ62 192

+ CD22 DDRA_SDQ59 193 194 DDRA_SDQ63
330U_B2_2.5VM_R15M DQ59 DQ63
195 VSS51 VSS52 196
RD5 1 2 10K_0402_5% 197 198 MEM_MA_EVENT# MEM_MA_EVENT# 7
2 2 2 2 2 2 2 2 2 2 2 SA0 EVENT#
+3VS 199 VDDSPD SDA 200 FCH_SDATA0 12,15
2.2U_0603_6.3V6K

0.1U_0402_16V7K

201 SA1 SCL 202 FCH_SCLK0 12,15

CD24

1 1 203 VTT1 VTT2 204 +0.75VS

1
CD23

10K_0402_5%
RD6

205 G1 G2 206
SGA00004400
2 2 LCN_DAN06-K4406-0102
2

DDR3 SO-DIMM A CONN@

+1.5V
A DIMM_A REV H:4mm A

<Address: 00>
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
CD26

CD27

CD28

CD25

1 1 1 1

@ @ @ @
2 2 2 2

LA-8731P
Security Classification Compal Secret Data
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-8661P 0.1

Date: Tuesday, December 27, 2011 Sheet 11 of 47

5 4 3 2 1
 5 4 3 2 1

DDR3 SO-DIMM B
L +VREF_DQ 15mil

All VREF traces should +V_DDR_REFB +1.5V +1.5V

have 20 mil trace width
JDIMM2
+V_DDR_REFB 1 2
VREF_DQ VSS1 DDRB_SDQ4
3 VSS2 DQ4 4
DDRB_SDQ0 DDRB_SDQ5

0.1U_0402_16V7K

2.2U_0603_6.3V6K
CD29
5 DQ0 DQ5 6
DDRB_SDQ1

CD50
1 1 7 DQ1 VSS3 8
DDRB_SDQ[0..63] 9 10 DDRB_SDQS0#
7 DDRB_SDQ[0..63] VSS4 DQS#0 DDRB_SDQS0# 7
DDRB_SDM0 11 12 DDRB_SDQS0
DDRB_SDM[0..7] DM0 DQS0 DDRB_SDQS0 7
7 DDRB_SDM[0..7] 13 VSS5 VSS6 14
2 2 DDRB_SDQ2 DDRB_SDQ6
D
15 DQ2 DQ6 16 D
DDRB_SMA[0..15] DDRB_SDQ3 17 18 DDRB_SDQ7
7 DDRB_SMA[0..15] DQ3 DQ7
19 VSS7 VSS8 20
DDRB_SDQ8 21 22 DDRB_SDQ12
DDRB_SDQ9 DQ8 DQ12 DDRB_SDQ13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDRB_SDQS1# 27 28 DDRB_SDM1
7 DDRB_SDQS1# DQS#1 DM1
DDRB_SDQS1 29 30 MEM_MB_RST#
7 DDRB_SDQS1 DQS1 RESET# MEM_MB_RST# 7
31 VSS11 VSS12 32
DDRB_SDQ10 33 34 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDRB_SDQ16 39 40 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDRB_SDQS2# 45 46 DDRB_SDM2
+1.5V 7 DDRB_SDQS2# DQS#2 DM2
DDRB_SDQS2 47 48
7 DDRB_SDQS2 DQS2 VSS17
49 50 DDRB_SDQ22
DDRB_SDQ18 VSS18 DQ22 DDRB_SDQ23
51 DQ18 DQ23 52
1

DDRB_SDQ19 53 54
RD12 DQ19 VSS19 DDRB_SDQ28
55 VSS20 DQ28 56
1K_0402_1% DDRB_SDQ24 57 58 DDRB_SDQ29
+V_DDR_REFB DDRB_SDQ25 DQ24 DQ29
10/03 change to +V_DDR_REFB 59
61
DQ25
VSS22
VSS21
DQS#3
60
62 DDRB_SDQS3#
DDRB_SDQS3# 7
2

DDRB_SDM3 63 64 DDRB_SDQS3
DM3 DQS3 DDRB_SDQS3 7
65 VSS23 VSS24 66
DDRB_SDQ26 67 68 DDRB_SDQ30
DQ26 DQ30
1

DDRB_SDQ27 69 70 DDRB_SDQ31
RD11 DQ27 DQ31
71 VSS25 VSS26 72
1K_0402_1%
2

DDRB_CKE0 73 74 DDRB_CKE1
7 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 7
75 VDD1 VDD2 76
77 78 DDRB_SMA15
DDRB_SBS2# NC1 A15 DDRB_SMA14
7 DDRB_SBS2# 79 BA2 A14 80
81 VDD3 VDD4 82
DDRB_SMA12 83 84 DDRB_SMA11
DDRB_SMA9 A12/BC# A11 DDRB_SMA7
C 85 A9 A7 86 C
87 VDD5 VDD6 88
DDRB_SMA8 89 90 DDRB_SMA6
DDRB_SMA5 A8 A6 DDRB_SMA4
91 A5 A4 92
93 VDD7 VDD8 94
DDRB_SMA3 95 96 DDRB_SMA2
DDRB_SMA1 A3 A2 DDRB_SMA0
97 A1 A0 98
99 VDD9 VDD10 100
Layout Note: DDRB_CLK0 101 102 DDRB_CLK1
7 DDRB_CLK0 CK0 CK1 DDRB_CLK1 7
DDRB_CLK0# DDRB_CLK1#
Place near JDIMM1.203 & JDIMM1.204 7 DDRB_CLK0#
DDRB_SMA10
103
105
CK0#
VDD11
CK1#
VDD12
104
106
DDRB_SBS1#
DDRB_CLK1# 7
L +VREF_CB 15mil +1.5V
107 A10/AP BA1 108 DDRB_SBS1# 7
DDRB_SBS0# 109 110 DDRB_SRAS#
7 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 7
111 VDD13 VDD14 112

1
DDRB_SWE# 113 114 DDRB_SCS0#
+0.75VS 7 DDRB_SWE# WE# S0# DDRB_SCS0# 7
DDRB_SCAS# 115 116 DDRB_ODT0 RD8
7 DDRB_SCAS# CAS# ODT0 DDRB_ODT0 7
117 118 1K_0402_1%
DDRB_SMA13 VDD15 VDD16 DDRB_ODT1 +VREF_CB
119 A13 ODT1 120 DDRB_ODT1 7
DDRB_SCS1# 121 122
7 DDRB_SCS1# S1# NC2

2
123 VDD17 VDD18 124 15mil
CD41

1U_0402_6.3V6K

CD51

1U_0402_6.3V6K

CD54

CD48

CD53

10U_0603_6.3V6M

CD52

10U_0603_6.3V6M

CD49

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

125 NCTEST VREF_CA 126

1 1 1 1 1 1 1 127 VSS27 VSS28 128
DDRB_SDQ32 DDRB_SDQ36

0.1U_0402_16V7K
129 DQ32 DQ36 130

1
DDRB_SDQ33 DDRB_SDQ37

2.2U_0603_6.3V6K
CD30
131 DQ33 DQ37 132

CD55
133 134 1 1 RD10
2 2 2 2 2 2 2 DDRB_SDQS4# VSS29 VSS30 DDRB_SDM4 1K_0402_1%
7 DDRB_SDQS4# 135 DQS#4 DM4 136
DDRB_SDQS4 137 138
7 DDRB_SDQS4 DQS4 VSS31
139 140 DDRB_SDQ38
VSS32 DQ38

2
DDRB_SDQ34 DDRB_SDQ39 2 2
141 DQ34 DQ39 142
DDRB_SDQ35 143 144
DQ35 VSS33 DDRB_SDQ44
145 VSS34 DQ44 146
DDRB_SDQ40 147 148 DDRB_SDQ45
DDRB_SDQ41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDRB_SDQS5#
VSS36 DQS#5 DDRB_SDQS5# 7
DDRB_SDM5 153 154 DDRB_SDQS5
DM5 DQS5 DDRB_SDQS5 7
155 VSS37 VSS38 156
DDRB_SDQ42 157 158 DDRB_SDQ46
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
B
159 DQ43 DQ47 160 B
161 VSS39 VSS40 162
Layout Note: DDRB_SDQ48 163 164 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
165 166
Place near JDIMM1 167
DQ49 DQ53
168
VSS41 VSS42
Layout Note: Place these 4 Caps near Command 7 DDRB_SDQS6#
DDRB_SDQS6# 169 DQS#6 DM6 170 DDRB_SDM6
DDRB_SDQS6 171 172
and Control signals of DIMMA 7 DDRB_SDQS6
173
DQS6 VSS43
174 DDRB_SDQ54
DDRB_SDQ50 VSS44 DQ54 DDRB_SDQ55
175 DQ50 DQ55 176
DDRB_SDQ51 177 178
+1.5V DQ51 VSS45 DDRB_SDQ60
179 VSS46 DQ60 180
DDRB_SDQ56 181 182 DDRB_SDQ61
DDRB_SDQ57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDRB_SDQS7#
VSS48 DQS#7 DDRB_SDQS7# 7
DDRB_SDM7 DDRB_SDQS7
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1 187 DM7 DQS7 188 DDRB_SDQS7 7

CD37

CD46

CD45

CD40

CD42

CD56

CD44

CD43

CD47

CD39

1 1 1 1 1 1 1 1 1 1 189 VSS49 VSS50 190

+ CD36 DDRB_SDQ58 191 192 DDRB_SDQ62
330U_B2_2.5VM_R15M DDRB_SDQ59 DQ58 DQ62 DDRB_SDQ63
193 DQ59 DQ63 194
195 VSS51 VSS52 196
2 2 2 2 2 2 2 2 2 2 2 RD7 1 MEM_MB_EVENT#
2 10K_0402_5% 197 SA0 EVENT# 198 MEM_MB_EVENT# 7
+3VS 199 VDDSPD SDA 200 FCH_SDATA0 11,15
2.2U_0603_6.3V6K

0.1U_0402_16V7K

201 SA1 SCL 202 FCH_SCLK0 11,15

CD38

1 1 203 VTT1 VTT2 204 +0.75VS

1
CD31

10K_0402_5%
RD9

SGA00004400 205 206

G1 G2
2 2 +3VS LCN_DAN06-K4406-0102

DDR3 SO-DIMM B
2

CONN@

+1.5V

DIMM_B REV H:8mm

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

Standard
CD33

CD34

CD35

CD32

A
1 1 1 1
<Address: 01> <Address(SA1,SA0):10> A

@ @ @ @
2 2 2 2

SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/05/27 Deciphered Date 2011/05/11 Title
DDRIII-DDRH
10/05 change to PH. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 12 of 47
5 4 3 2 1
 A B C D E

UH1A +3VALW
CH1 1 2 150P_0402_50V8J For PCIE device reset on FS1 CH10
HUDSON-2 1 2
APU_PCIE_RST#_C
(GFX,GLAN,WLAN,LVDS Travis)
PCI Host Bus Reset (To EC) AE2 PCIE_RST# PCICLK0 AF3
RH1 1 2 33_0402_5% AD5 AF1 0.1U_0402_16V4Z

PCI CLKS
10,29,31 PLT_RST# A_RST# PCICLK1/GPO36 PCI_CLK1 16

5
PCICLK2/GPO37 AF5
CH2 1 2 .1U_0402_16V7K UMI_MTX_FRX_P0 AE30 AG2 2
6 UMI_MTX_C_FRX_P0 PCI_CLK3 16

P
CH3 .1U_0402_16V7K UMI_MTX_FRX_N0 UMI_TX0P PCICLK3/GPO38 APU_PCIE_RST#_C RH2 B
6 UMI_MTX_C_FRX_N0 1 2 AE32 UMI_TX0N PCICLK4/14M_OSC/GPO39 AF6 PCI_CLK4 16 1 2 33_0402_5% Y 4 APU_PCIE_RST# 18,21,23
CH4 1 2 .1U_0402_16V7K UMI_MTX_FRX_P1 AD33 1
6 UMI_MTX_C_FRX_P1 UMI_TX1P A

G
CH5 1 2 .1U_0402_16V7K UMI_MTX_FRX_N1 AD31 AB5 1 UH2
6 UMI_MTX_C_FRX_N1 UMI_TX1N PCIRST#
CH6 1 2 .1U_0402_16V7K UMI_MTX_FRX_P2 AD28 CH11 RH3 NC7SZ08P5X_NL_SC70-5
6 UMI_MTX_C_FRX_P2 UMI_TX2P

3
CH7 1 2 .1U_0402_16V7K UMI_MTX_FRX_N2 AD29 150P_0402_50V8J @ 8.2K_0402_5%
6 UMI_MTX_C_FRX_N2 UMI_TX2N
CH8 1 2 .1U_0402_16V7K UMI_MTX_FRX_P3 AC30 AJ3
6 UMI_MTX_C_FRX_P3 UMI_TX3P AD0/GPIO0 2
6 UMI_MTX_C_FRX_N3
CH9 1 2 .1U_0402_16V7K UMI_MTX_FRX_N3 AC32 UMI_TX3N AD1/GPIO1 AL5 Delete GPU

1
AD2/GPIO2 AG4 1202 Calvin
1 UMI_FTX_C_MRX_P0 1
6 UMI_FTX_C_MRX_P0 AB33 UMI_RX0P AD3/GPIO3 AL6
UMI_FTX_C_MRX_N0 AB31 AH3

PCI EXPRESS INTERFACES

6 UMI_FTX_C_MRX_N0 UMI_RX0N AD4/GPIO4
UMI_FTX_C_MRX_P1 AB28 AJ5 1 2
6 UMI_FTX_C_MRX_P1 UMI_RX1P AD5/GPIO5
UMI_FTX_C_MRX_N1 AB29 AL1 RH130 @ 0_0402_5%
6 UMI_FTX_C_MRX_N1 UMI_RX1N AD6/GPIO6
UMI_FTX_C_MRX_P2 Y33 AN5
6 UMI_FTX_C_MRX_P2 UMI_RX2P AD7/GPIO7
UMI_FTX_C_MRX_N2 Y31 AN6
6 UMI_FTX_C_MRX_N2 UMI_RX2N AD8/GPIO8
UMI_FTX_C_MRX_P3 Y28 AJ1
6 UMI_FTX_C_MRX_P3 UMI_RX3P AD9/GPIO9
UMI_FTX_C_MRX_N3 Y29 AL8
6 UMI_FTX_C_MRX_N3 UMI_RX3N AD10/GPIO10
AD11/GPIO11 AL3
RH4 1 2 590_0402_1% PCIE_CALRP AF29 AM7 +3VALW
PCIE_CALRP AD12/GPIO12
+PCIE_VDDR_FCH RH5 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRN AD13/GPIO13 AJ6
AD14/GPIO14 AK7
L PCIE_CALRP R=50ohm, 4mil,<1000mil
PCIE_CALRN R=50ohm, 4mil,<1000mi
V33
V31
GPP_TX0P
GPP_TX0N
AD15/GPIO15
AD16/GPIO16
AN8
AG9

1
W30 GPP_TX1P AD17/GPIO17 AM11 2.2K_0402_5%
W32
AB26
AB27
GPP_TX1N
GPP_TX2P
AD18/GPIO18
AD19/GPIO19
AJ10
AL12
AK11
2.2K_0402_5%
RH70
RH71 Board ID
GPP_TX2N AD20/GPIO20
AA24 AN12
GPP_TX3P AD21/GPIO21 FCH_GPIO30 FCH_GPIO31

2
Del GPP PCI-E AA23 GPP_TX3N AD22/GPIO22 AG12 FCH_GPIO30
FCH_GPIO31
AD23/GPIO23 AE12 PCI_AD23 16
AA27 AC12
ABO connect to USB3.0 PHY. AA26
GPP_RX0P
GPP_RX0N
AD24/GPIO24
AD25/GPIO25 AE13
PCI_AD24
PCI_AD25
16
16
PX4 0 0
W27 AF13

PCI INTERFACE
GPP_RX1P AD26/GPIO26 PCI_AD26 16
V27 GPP_RX1N AD27/GPIO27 AH13 PCI_AD27 16 Reserve 0 1

1
V26 AH14 VGA_PWRGD_R Change to GPIO51
GPP_RX2P AD28/GPIO28 TH1 RH77
W26 AD15 HDDHALT_LED# 23 RH76
GPP_RX2N AD29/GPIO29 FCH_GPIO30 100K_0402_5%
W24
W23
GPP_RX3P
GPP_RX3N
AD30/GPIO30
AD31/GPIO31
AC15
AE16 FCH_GPIO31 Board ID
100K_0402_5% DIS 1 0
CBE0# AN3

2
20mil CBE1# AJ8
AN10
UMA 1 1
2 CBE2#
+1.1VS_CKVDD RH6 1 2 2K_0402_1% CLK_CALRN F27 CLK_CALRN CBE3# AD12 @ @ 2

FRAME# AG10
DEVSEL# AK9
IRDY# AL10
G30 PCIE_RCLKP TRDY# AF10
SS For "EXT" CLK mode, input to PCIE, G28 PCIE_RCLKN PAR AE10

APU_DISP_CLKP STOP# AH1 Del USB3.0_CLKREQ# PH.

8 APU_DISP_CLKP R26 DISP_CLKP PERR# AM9
+RTCBATT
APU DISP 8 APU_DISP_CLKN
APU_DISP_CLKN T26 DISP_CLKN SERR# AH8 GPIO0 29
REQ0# AG15
NSS H33
H31
DISP2_CLKP REQ1#/GPIO40 AG13
AF15
20mils
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 CRCLK_REQ# RH7
REQ3#/CLK_REQ5#/GPIO42 AM17 1 2 8.2K_0402_5% +3VS JRTC1 @
APU_CLKP T24 AD16 1
8 APU_CLKP APU_CLKP GNT0# 1
APU 8 APU_CLKN
APU_CLKN T23 APU_CLKN GNT1#/GPO44 AD13 2 2
GNT2#/SD_LED/GPO45 AD21
Delete GPU J30 SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46 AK17 TH2 3 GND
VGA 1202 Calvin K29 SLT_GFX_CLKN CLKRUN# AD19 R512 2 @ 1 PM_CLKRUN# PM_CLKRUN# 31 For EMI Requirement Close to U25 4 GND
AH9 0_0402_5%
LOCK#
H27 GPP_CLK0P ACES_50271-0020N-001
H28 GPP_CLK0N INTE#/GPIO32 AF18
INTF#/GPIO33 AE18 11/08 Reserved BIOS setting
J27 GPP_CLK1P INTG#/GPIO34 AC16
K26 GPP_CLK1N INTH#/GPIO35 AD18 ACCEL_INT# 31
@
CLK_PCIE_MINI1 F33 CH12 1 2 10P_0402_50V8J
CLOCK GENERATOR

21 CLK_PCIE_MINI1 GPP_CLK2P
Wireless LAN 21 CLK_PCIE_MINI1#
CLK_PCIE_MINI1# F31 GPP_CLK2N
RH10
LPC_CLK0_EC_R LPC_CLK0_EC
SS CLK_PCIE_LAN E33
LPCCLK0 B25 1 2
0_0402_5%
LPC_CLK0_EC 16,21,29,31
APU_PG/APU_RST#/LDT_STP# : OD pin
23 CLK_PCIE_LAN GPP_CLK3P
Ethernet LAN 23 CLK_PCIE_LAN#
CLK_PCIE_LAN# E31 GPP_CLK3N LPCCLK1 D25 LPC_CLK1
LPC_CLK1 16 DMA_ACTIVE# : IN/OD, 0.8V threshold
D27 LPC_AD0 PROCHOT# : IN, 0.8V threshold
LAD0 LPC_AD0 21,29,31
M23 C28 LPC_AD1 LDT_STP : No use, NC
3 GPP_CLK4P LAD1 LPC_AD1 21,29,31 3
M24 A26 LPC_AD2 LPC_AD2 21,29,31 DMA active. The FCH drives the DMA_ACTIVE# to
GPP_CLK4N LAD2 LPC_AD3
A29
LPC

LAD3 LPC_AD3 21,29,31 APU to notify DMA activity. This will cause the APU
M27 A31 LPC_FRAME#
GPP_CLK5P LFRAME# LPC_FRAME# 21,29,31 to reestablish the UMI link quicker.
M26 GPP_CLK5N LDRQ0# B27
Del MIN2,Card reader, USB 3.0 IC LDRQ1#/CLK_REQ6#/GPIO49 AE27
SERIRQ
Del USB3.0_CLKREQ#
N25 GPP_CLK6P SERIRQ/GPIO48 AE19 SERIRQ 29,31
N26 GPP_CLK6N APU_PWRGD
R23 CH13 33P_0402_50V8J
GPP_CLK7P ALLOW_STOP APU_RST#
R24 GPP_CLK7N DMA_ACTIVE# G25 ALLOW_STOP 8
E28 EC_THERM_R# 1 @ 2 CH14 33P_0402_50V8J
PROCHOT# EC_THERM# 8,29,36,42
N27 E26 APU_PWRGD RH11 0_0402_5% for ESD Close FCH Side
GPP_CLK8P APU_PG APU_PWRGD 8,42
R27 G26
APU

GPP_CLK8N LDT_STP# APU_RST#

APU_RST# F26 APU_RST# 8
+RTCBATT

L 25M_X1 and 25M_X1_R=50ohm, 4mil J26 14M_25M_48M_OSC

1
TH7 H7
25M_X2=50ohm, 4mil S5_CORE_EN
F1 RTC_CLK_R 1 2 RTC_CLK 16,29
RH13
RTCCLK RH12 22_0402_5%
INTRUDER_ALERT# F3 1K_0402_5%
1 2 25M_X1_R 1 2 25M_X1 C31 E6 RTCVCC_R RTC_CLK_R=50ohm, 4mil
CH15 RH14 0_0402_5% 25M_X1 VDDBT_RTC_G
L
S5 PLUS

RTC_CLK=50ohm, 4mil

2
1

27P_0402_50V8J G2 32K_X1
RH15 32K_X1
X2 25M_X2
W>=15mils
1M_0402_5% C33 25M_X2
W>=15mils +RTCVCC D62
2

G4 32K_X2 W>=15mils 2
32K_X2
1 2 1 2 1
CH16 25MHZ_20PF_7A25000012 RH16 510_0402_5% 3 +3VLP
27P_0402_50V8J

0.1U_0402_16V4Z
1 1

2
HUDSON-M2_FCBGA656 CH17 CH18 1 BAV70W_SOT323-3
0.1U_0402_16V4Z 1U_0402_6.3V6K RH17 CH19 Update to +3VLP
@
4 2 2 0_0603_5% 4
1 2 32K_X1 R860 for Clear CMOS
2 L D23 close to U25 (FCH)

1
CH20
C1205,C1206 15P_0402_50V8J X3
1

Change for G3 4 OSC NC 3

L 32K_X1=50ohm, 4mil,<1500mil
32K_X2=50ohm, 4mil,<1500mil
RTC timing issue RH18 1 OSC NC 2
<improve amplitude> 20M_0402_5%
32.768KHZ_12.5PF_Q13MC14610002 Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

CH21
1 2 32K_X2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
15P_0402_50V8J Close to HUDSON-M2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 13 of 47

A B C D E
 A B C D E

UH1B
4MB SPI ROM +3VALW

HUDSON-2 & Non-share ROM. 0.1U_0402_16V4Z

2
CH22
1
SATA_STX_DRX_P0 AK19 AL14 +3VALW RH19
22 SATA_STX_DRX_P0 SATA_TX0P SD_CLK/SCLK_2/GPIO73
SATA_STX_DRX_N0 AM19 AN14 10K_0402_5% UH3
22 SATA_STX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74
HDD1 AJ12 1 2 FCH_SPI_CS1# 1 8 FCH_SPI_VCC
SATA_DTX_SRX_N0 SD_CD/GPIO75 FCH_SPI_MISO CS# VCC FCH_SPI_HOLD#
22 SATA_DTX_SRX_N0 AL20 SATA_RX0N SD_WP/GPIO76 AH12 2 SO/SIO1 HOLD# 7 2 1

SD CARD
SATA_DTX_SRX_P0 AN20 AK13 1 2 FCH_SPI_WP# 3 6 FCH_SPI_CLK RH20
22 SATA_DTX_SRX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 WP# SCLK
AM13 RH21 4 5 FCH_SPI_MOSI 10K_0402_5%
SD_DATA1/SDATO_2/GPIO78 10K_0402_5% GND SI/SIO0
AN22 SATA_TX1P SD_DATA2/GPIO79 AH15
AL22 AJ14 MX25L3206EM2I-12G_SO8
SATA_TX1N SD_DATA3/GPIO80 Check CS# PU R 1kor10k and pop/nopop
AH20 AC4 SCL v1.20 : If an SPI ROM is shared between
1 SATA_RX1N GBE_COL 1
AJ20 SATA_RX1P GBE_CRS AD3 the FCH and the Embedded Controller
GBE_MDCK AD9 a 10-K pull-up resistor to +3.3V_S5 is installed.
AJ22 SATA_TX2P GBE_MDIO W10
AH22 SATA_TX2N GBE_RXCLK AB8
12/12 del mSATA by customer GBE_RXD3 AH7
AM23 SATA_RX2N GBE_RXD2 AF7
AK23 AE7 @ RH22 @ CH23
SATA_RX2P GBE_RXD1 FCH_SPI_CLK
GBE_RXD0 AD7 1 2 1 2
AH24 AG8 10_0402_5%
SATA_TX3P GBE_RXCTL/RXDV 10P_0402_50V8J
AJ24 SATA_TX3N GBE_RXERR AD1
AB7 Add for EMI 201011291330

GBE LAN
GBE_TXCLK
AN24 SATA_RX3N GBE_TXD3 AF9
AL24 AG6 GBE_COL / GBE_CRS / GBE_MDIO
SATA_RX3P GBE_TXD2
AE8 GBE_RXERR / Left unconnected.
GBE_TXD1
AL26 SATA_TX4P GBE_TXD0 AD8 FCH SCL V1.20 19-35
AN26 SATA_TX4N GBE_TXCTL/TXEN AB9
AC2

SERIAL ATA
GBE_PHY_PD GBE_PHY_INTR
AJ26 SATA_RX4N GBE_PHY_RST# AA7
AH26 W9 GBE_PHY_INTR Pulled-up to +3.3V_S5 with a 10-KΩ 5% resistor. +3VALW
SATA_RX4P GBE_PHY_INTR
FCH SCL v1.20 #19-85
AN29 SATA_TX5P
AL28 V6 FCH_SPI_MISO GBE_PHY_INTR 1 2
SATA_TX5N SPI_DI/GPIO164 FCH_SPI_MOSI RH23 10K_0402_5%
SPI_DO/GPIO163 V5

SPI ROM
AK27 V3 FCH_SPI_CLK_R RH24 1 2 0_0402_5% FCH_SPI_CLK
SATA_RX5N SPI_CLK/GPIO162 FCH_SPI_CS1# Removed RGMII/MII support and updated termination
AM27 SATA_RX5P SPI_CS1#/GPIO165 T6
V1 FCH_SPI_WP# requirements for GBE_COL, GBE_CRS, GBE_RXERR
ROM_RST#/SPI_WP#/GPIO161
AL29 NC6 and GBE_MDIO when RGMII/MII interface is not used.
AN31 NC7 FCH DGv1.20 / SCL v1.20
VGA_RED L30
AL31 NC8
AL33 NC9
VGA_GREEN L32
2 2
AH33 NC10
AH31 NC11
VGA_BLUE M29
AJ33

VGA DAC
NC12
L SATA_CALRP=35ohm,<1000mil
SATA_CALRN=35ohm,<1000mi
AJ31 NC13
VGA_HSYNC/GPO68 M28
VGA_VSYNC/GPO69 N30

VGA_DDC_SDA/GPO70 M33
1K_0402_1% 2 1 RH25 SATA_CALRP AF28 N32
SATA_CALRP VGA_DDC_SCL/GPO71

+AVDD_SATA 931_0402_1%2 1 RH26 SATA_CALRN AF27 SATA_CALRN

VGA_DAC_RSET K31 1 2
FCH Schematics Check List V1.20 RH27 715_0402_1%
SATA_LED# AD22
23 SATA_LED# SATA_ACT#/GPIO67
AUX_VGA_CH_P V28
+3VS RH28 1 2 10K_0402_5% V29
AUX_VGA_CH_N
AF21

VGA MAINLINK
SATA_X1
@ AUXCAL U28

ML_VGA_L0P T31
ML_VGA_L0N T33 12/19 remove RH29, RH31 for HW request
AG21 SATA_X2 ML_VGA_L1P T29
ML_VGA_L1N T28
+3VS 2 1 BT_ON# R32
RH30 10K_0402_5% ML_VGA_L2P
ML_VGA_L2N R30
ML_VGA_L3P P29
ML_VGA_L3N P28

ML_VGA_HPD/GPIO229 C29
3
Del WL_OFF#_2 3
AH16 FANOUT0/GPIO52 VIN0/GPIO175 N2 1
RH32
2
10K_0402_5%
Check?
AM15 FANOUT1/GPIO53
BT_ON# HW MONITOR
Confirm BT_ON# or BT_ON 21 BT_ON# AJ16 FANOUT2/GPIO54 VIN1/GPIO176 M3 1
RH33
2
10K_0402_5%
Del W_DISABLE#_2 WL_OFF#
AK15 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177 L2 1
RH34
2
10K_0402_5%
21 WL_OFF# AN16 FANIN1/GPIO57
AL16 FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 N4 1 2
RH35 10K_0402_5%
VIN4/SLOAD_1/GPIO179 P1 1 2
K6 RH36 10K_0402_5%
TEMPIN0/GPIO171
VIN5/SCLK_1/GPIO180 P3 1 2
RH37 10K_0402_5%
1 2 K5 TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 M1 1 2
RH38 10K_0402_5% RH39 @ 10K_0402_5% Enabled integrated pull-down/up and left unconnected.
VIN7/GBE_LED3/GPIO182 M5 1 2
1 2 K3 RH40 10K_0402_5%
RH41 10K_0402_5% TEMPIN2/GPIO173

NC1 AG16
1 2 M6 TEMPIN3/TALERT#/GPIO174 NC2 AH10
RH42 10K_0402_5% A28
NC3
NC4 G27
NC5 L4

HUDSON-M2_FCBGA656

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-SATA/GBE/HWM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 14 of 47

A B C D E
 A B C D E

UH1D

HUDSON-2
FCH_PCIE_RST# IS FOR PCIE AB6 G8 TH5

USB MISC
TH3 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
EC_LID_OUT# R2
DEVICES ON Hudson-M2/M3 29 EC_LID_OUT#
W7
RI#/GEVENT22#
B9 USB_RCOMP RH43 1 2 11.8K_0402_1%
SLP_S3# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
29 SLP_S3# T3 SLP_S3#
SLP_S5# W2 H1
29 SLP_S5# SLP_S5# USB_FSD1P/GPIO186
PBTN_OUT# J4 H3 Hudson-M2/M3
29 PBTN_OUT# PWR_BTN# USB_FSD1N
FCH_PWRGD N7 OHCI CTL
29 FCH_PWRGD PWR_GOOD

USB 1.1
H6 DEV 20, Fn 5

ACPI / WAKE UP EVENTS

TEST0 USB_FSD0P/GPIO185
T9 TEST0 USB_FSD0N H5 <Disable CTL>
TEST1 T10
TEST2 TEST1/TMS
V9 TEST2 USB_HSD13P H10
1 USB_HSD13N G10 1
EC_GA20 AE22
29 EC_GA20 GA20IN/GEVENT0#
USB_HSD12P K10 Hudson-M2 Hudson-M3
EC_KBRST# AG19 J12 EHCI CTL xHCI CTL
29 EC_KBRST# KBRST#/GEVENT1# USB_HSD12N
EC_SCI# R9 DEV 22, Fn 2 DEV 16, Fn 1
THERMTRIP:
Check with BIOS 29 EC_SCI#
EC_SMI# C26
LPC_PME#/GEVENT3#
G12 USB20_P11 <Disable CTL of M2> xHCI CTL
29 EC_SMI# LPC_SMI#/GEVENT23# USB_HSD11P USB20_P11 24
SUS_STAT# T5 F12 USB20_N11 USB 2.0 port(Right-2) DEV 16, Fn 0
Need level shift from +3VALW to +1.5V 31 SUS_STAT#
SYS_RESET# LPC_PD#/GEVENT5# USB_HSD11N USB20_N11 24
U4
Note: Ensure FCH internal pull-up resistor FCH_PCIE_WAKE# K1 SYS_RESET#/GEVENT19#
K12 USB20_P10
21,23 FCH_PCIE_WAKE# WAKE#/GEVENT8# USB_HSD10P USB20_P10 24
to +3.3V S5 is disabled to prevent leakage V7 K13 USB20_N10
USB20_N10 24 USB 2.0 port(Right-1)
H_THERMTRIP# IR_RX1/GEVENT20# USB_HSD10N
when APU is powered down. 8 H_THERMTRIP# R10 THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD AF19 B11
WD_PWRGD USB_HSD9P
USB_HSD9N D11 Del USB port 9 Hudson-M2/M3
EC_RSMRST# U2 EHCI CTL
29 EC_RSMRST# RSMRST#
E10 USB20_P8 DEV 19, Fn 2
USB_HSD8P USB20_P8 21
SM bus 0-->S0 PWR domain Del MINI2_CLKREQ# AG24 F10 USB20_N8 Mini1-WLAN
CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N USB20_N8 21
LAN_CLKREQ# AE24
SM bus 1-->S5 PWR domain 23 LAN_CLKREQ# CLK_REQ3#/SATA_IS1#/GPIO63
AE26 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P C10
AF22 A10 Del USB port 7

USB 2.0
CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N
FCH GEVENT (S5 domain) AH17 SATA_IS4#/FANOUT3/GPIO55
with isolation circuit to avoid leakage PC_BEEP use. FCH_SPKR
AG18 SATA_IS5#/FANIN3/GPIO59 USB_HSD6P H9
25 FCH_SPKR AF24 SPKR/GPIO66 USB_HSD6N G9
FCH_SCLK0 AD26

GPIO
11,12 FCH_SCLK0 SCL0/GPIO43
FCH_SDATA0 AD25 A8 USB20_P5
11,12 FCH_SDATA0 SDA0/GPIO47 USB_HSD5P USB20_P5 19
FCH_SCLK1 T7 C8 USB20_N5 Camera
30 FCH_SCLK1 SCL1/GPIO227 USB_HSD5N USB20_N5 19
FCH_SDATA1 R7
30 FCH_SDATA1 SDA1/GPIO228
MINI1_CLKREQ# AG25 F8
21 MINI1_CLKREQ# CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P
AG22 CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N E8 Hudson-M2/M3
Del ODD_DA# J2 IR_LED#/LLB#/GPIO184 EHCI CTL
AG26 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P C6 DEV 18, Fn 2
V8 DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N A6 <Support Wakeup>
W8 GBE_LED0/GPIO183
Y6 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P C5
V10 GBE_LED2/GEVENT10# USB_HSD2N A5
AA8 GBE_STAT0/GEVENT11#
AF25 CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P C1
USB_HSD1N C3

2 Del SIMB output SMIB M7 E1 USB20_P0 2

RH44 BLINK/USB_OC7#/GEVENT18# USB_HSD0P USB20_P0 24
R8 E3 USB20_N0 USB 2.0 port(Left-1)
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 24
2 1CARD_DET_FCH T1

USB OC
+3VALW USB_OC5#/IR_TX0/GEVENT17# USBSS_CALRP RH45 1 2 1K_0402_1%
10K_0402_5%
TH4
CARD_DET_FCH
P6
F5
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USBSS_CALRP
USBSS_CALRN
C16
A16 USBSS_CALRN RH46 1 2 1K_0402_1% +FCH_VDD_11_SSUSB_S
L USBSS_CALRP=35ohm,<1000mil
USBSS_CALRN=35ohm,<1000mi
P5 USB_OC2#/TCK/GEVENT14#
@ USB_OC1# J7 A14
24 USB_OC1# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
USB_OC0# T8 C14
24 USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
Hudson-M3
USB_SS_RX3P C12 xHCI CTL
USB_SS_RX3N A12 DEV 16, Fn 1
xHCI CTL
Confirm CR det or not. RH47 1 2 33_0402_5% HDA_BITCLK AB3 D15 DEV 16, Fn 0
25 HDA_BITCLK_AUDIO AZ_BITCLK USB_SS_TX2P
RH48 1 2 33_0402_5% HDA_SDOUT AB1 B15
25 HDA_SDOUT_AUDIO AZ_SDOUT USB_SS_TX2N
HDA_SDIN0 AA2

HD AUDIO
25 HDA_SDIN0 AZ_SDIN0/GPIO167
33ohm termination HDA_SDIN1 Y5 E14

USB 3.0
HDA_SDIN2 AZ_SDIN1/GPIO168 USB_SS_RX2P
resistor at CODEC side Y3 AZ_SDIN2/GPIO169 USB_SS_RX2N F14
HDA_SDIN3 Y1
RH49 1 HDA_SYNC AZ_SDIN3/GPIO170 USB3_TX1_P
25 HDA_SYNC_AUDIO 2 33_0402_5% AD6 AZ_SYNC USB_SS_TX1P F15 USB3_TX1_P 24
RH50 1 2 33_0402_5% HDA_RST# AE4 G15 USB3_TX1_N
+3VALW 25 HDA_RST_AUDIO# AZ_RST# USB_SS_TX1N USB3_TX1_N 24
H13 USB3_RX1_P USB 3.0 port(Right-2)
USB_SS_RX1P USB3_RX1_P 24
Change GPIO fellow Pumori G13 USB3_RX1_N
USB_SS_RX1N USB3_RX1_N 24

Del FCH_GPIO187 K19 J16 USB3_TX0_P

PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB3_TX0_P 24
1 2 USB_OC0# J19 H16 USB3_TX0_N
PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB3_TX0_N 24
RH69 100K_0402_5% J21 USB 3.0 port(Right-1)
USB_OC1# SPI_CS2#/GBE_STAT2/GPIO166 USB3_RX0_P
1 2 USB_SS_RX0P J15 USB3_RX0_P 24
RH51 100K_0402_5% K15 USB3_RX0_N
USB_SS_RX0N USB3_RX0_N 24
1 2 H_THERMTRIP#
RH52 10K_0402_5% D21
FCH_SCLK1 TH6 PS2KB_DAT/GPIO189 RH54 10K_0402_5%
1
RH53
2
2.2K_0402_5%
12/20 Del DDR3L_EN C20 PS2KB_CLK/GPIO190 SCL2/GPIO193 H19
RH56
1 2
10K_0402_5%
D23 PS2M_DAT/GPIO191 SDA2/GPIO194 G19 1 2
1 2 FCH_SDATA1 C22 EMBEDDED CTRL G22 RH59 1 2 10K_0402_5%
RH57 2.2K_0402_5% PS2M_CLK/GPIO192 SCL3_LV/GPIO195 RH60 10K_0402_5%
SDA3_LV/GPIO196 G21 1 2
1 @ 2 EC_LID_OUT# E22
RH61 100K_0402_5% EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198 H22
1 2 FCH_PCIE_WAKE# F21 J22 EC_PWM2
3 KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 EC_PWM2 16 3
RH62 10K_0402_5% E20 H21
@ SYS_RESET# KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
1 2 F20 KSO_2/GPIO211
RH63 10K_0402_5% A22 K21
@ SMIB KSO_3/GPIO212 KSI_0/GPIO201
1 2 E18 KSO_4/GPIO213 KSI_1/GPIO202 K22 For PCIE device reset on FS1
RH64 10K_0402_5% A20 F22
LAN_CLKREQ# KSO_5/GPIO214 KSI_2/GPIO203 (GFX,GLAN,WLAN,LVDS Travis)
1 2 J18 KSO_6/GPIO215 KSI_3/GPIO204 F24
RH65 8.2K_0402_5% H18 E24
KSO_7/GPIO216 KSI_4/GPIO205
G18 KSO_8/GPIO217 KSI_5/GPIO206 B23
B21 KSO_9/GPIO218 KSI_6/GPIO207 C24
For FCH internal debug use K18 KSO_10/GPIO219 KSI_7/GPIO208 F18
D19 KSO_11/GPIO220
1 @ 2 TEST0 A18
RH66 2.2K_0402_5% KSO_12/GPIO221
C18 KSO_13/GPIO222
1 @ 2 TEST1 B19
RH67 2.2K_0402_5% KSO_14/GPIO223
B17 KSO_15/GPIO224
1 @ 2 TEST2 A24
RH68 2.2K_0402_5% KSO_16/GPIO225
D17 KSO_17/GPIO226

+3VS HUDSON-M2_FCBGA656

1 2 FCH_SCLK0
RH72 2.2K_0402_5%
1 2 FCH_SDATA0
RH73 2.2K_0402_5%
1 2 MINI1_CLKREQ#
RH74 8.2K_0402_5%
Del MINI2_CLKREQ# PH. Del FCH_GPIO187 R57 R55
1 2 WD_PWRGD
RH78 10K_0402_5%
1 2 LAN_CLKREQ#
RH80 @ 8.2K_0402_5% 12/06 Del VGA_PWRGD
1 2 EC_RSMRST#
RH81 2.2K_0402_5%
1 @ 2 HDA_BITCLK
4 RH83 10K_0402_5% 4
1 @ 2 HDA_SDIN0
RH85 10K_0402_5%
1 @ 2 HDA_SDIN1
RH86 10K_0402_5%
1 @ 2 HDA_SDIN2
RH87 10K_0402_5%
1 @ 2 HDA_SDIN3
RH88 10K_0402_5%

CH98
1 2
22P_0402_50V8J
HDA_BITCLK
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 HDA_SDOUT 2011/07/08 2015/07/08 Title
Issued Date Deciphered Date
CH99 22P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-ACPI/USB/EC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 15 of 47

A B C D E
 A B C D E

Change to SPI

STRAP PINS
PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK

1 1
PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS
HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE
STRAPS DISABLED
DEFAULT DEFAULT DEFAULT

PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS

LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE
STRAP MODE DEFAULT ENABLED
DEFAULT DEFAULT DEFAULT

+3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW

RH89

RH90 10K_0402_5%

RH91 10K_0402_5%

RH92 10K_0402_5%

RH93 10K_0402_5%

RH94 10K_0402_5%

RH95 10K_0402_5%
1

1
@ @ @ @
10K_0402_5%
2

2
Remove VGA_PD
13 PCI_CLK1

2 13 PCI_CLK3 2

13 PCI_CLK4

13,21,29,31 LPC_CLK0_EC

13 LPC_CLK1

15 EC_PWM2

13,29 RTC_CLK
RH97 10K_0402_5%

RH98 10K_0402_5%

RH99 10K_0402_5%

RH100 10K_0402_5%

RH101 10K_0402_5%

RH102 2.2K_0402_5%

RH103 2.2K_0402_5%
1

1
@ @ @
2

2
DEBUG STRAPS Remove VGA_PD

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

3 3

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI

PULL PLL ILA PLL PCIE STRAPS MEM BOOT
HIGH AUTORUN
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI

LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
AUTORUN

13 PCI_AD27

13 PCI_AD26

13 PCI_AD25

13 PCI_AD24

13 PCI_AD23

4 4
RH104 2.2K_0402_5%

RH105 2.2K_0402_5%

RH106 2.2K_0402_5%

RH107 2.2K_0402_5%

RH108 2.2K_0402_5%
1

@ @ @ @ @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 16 of 47

A B C D E
 A B C D E

+VCC_FCH_R +1.1VS
UH1C 1007mA
131mA 10mils 1 2
HUDSON-2 RH109 0_0805_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z

22U_0805_6.3V6M
+VDDIO_33_PCIGP
50mils

CH27

CH28

CH29

CH30

CH31

CH32
+3VS 1 2 AB17 VDDIO_33_PCIGP_1 VDDCR_11_1 T14
+3VS RH110 0_0603_5%

22U_0805_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
AB18 VDDIO_33_PCIGP_2 VDDCR_11_2 T17 1 1 1 1 1 1
LH2 UH1E

CH33

CH34

CH35

CH36
AE9 T20

PCI/GPIO I/O
+VDDPL_3.3V VDDIO_33_PCIGP_3 VDDCR_11_3
1 2 1 1 1 1 AD10 VDDIO_33_PCIGP_4 VDDCR_11_4 U16
MBK1608221YZF_2P HUDSON-2

2.2U_0603_6.3V4Z
AG7 U18

.1U_0402_16V7K
VDDIO_33_PCIGP_5 VDDCR_11_5 2 2 2 2 2 2

CORE S0
CH37

CH38
220 ohm AC13 VDDIO_33_PCIGP_6 VDDCR_11_6 V14 A3 VSS VSS T25
1 1
1 1 AB12 VDDIO_33_PCIGP_7 VDDCR_11_7 V17 A33 VSS VSS T27
2 2 2 2
AB13 VDDIO_33_PCIGP_8 VDDCR_11_8 V20 B7 VSS VSS U6
AB14 VDDIO_33_PCIGP_9 VDDCR_11_9 Y17 B13 VSS VSS U14
AB16 +1.1VS_CKVDD +1.1VS D9 U17
2 2 VDDIO_33_PCIGP_10 VSS VSS
47mA 10mils 20mils 340mA D13 VSS VSS U20
+VDDPL_3.3V H24 H26 +1.1VS_CKVDD 1 2 E5 U21
VDDPL_33_SYS VDDAN_11_CLK_1 RH111 0_0603_5% VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
20mA 10mils VDDAN_11_CLK_2 J25 E12 VSS VSS U30

CH39

CH40

CH41

CH42

CH43
1 2 V22 K24 E16 U32

CLKGEN I/O
VDDPL_33_DAC VDDAN_11_CLK_3 VSS VSS
20mA RH112 0_0402_5% 10mils VDDAN_11_CLK_4 L22 1 1 1 1 1 E29 VSS VSS V11
12/19 change to GND 1 2 U22 VDDPL_33_ML VDDAN_11_CLK_5 M22 F7 VSS VSS V16
200mA RH114 0_0402_5% 10mils VDDAN_11_CLK_6 N21 F9 VSS VSS V18
1 2 T22 VDDAN_33_DAC VDDAN_11_CLK_7 N22 F11 VSS VSS W4
RH113 0_0402_5% 2 2 2 2 2
20mA 10mils VDDAN_11_CLK_8 P22 F13 VSS VSS W6
+FCH_VDDPL_33_SSUSB_S L18 F16 W25
VDDPL_33_SSUSB_S VSS VSS
VDDPL_33_SSUSB_S M3 only 17mA 10mils F17 VSS VSS W28
+FCH_VDDPL_33_USB_S +PCIE_VDDR_FCH +1.1VS
For Hudson3 USB3.0 only D7 VDDPL_33_USB_S 50mils F19 VSS VSS Y14
43mA 10mils AB24 1088mA F23 Y16
For Hudson2, connect to GND +VDDPL_33_PCIE AH29
VDDAN_11_PCIE_1
Y21 +PCIE_VDDR_FCH 1 2 F25
VSS VSS
Y18
VDDPL_33_PCIE VDDAN_11_PCIE_2 VSS VSS

PCI EXPRESS
RH115 0_0805_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
93mA 10mils VDDAN_11_PCIE_3 AE25 F29 VSS VSS AA6
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA

CH47

CH48

CH49

CH50

CH51
AG28 VDDPL_33_SATA VDDAN_11_PCIE_4 AD24 G6 VSS VSS AA12
supply for the RGB outputs VDDAN_11_PCIE_5 AB23 1 1 1 1 1 G16 VSS VSS AA13
For A11: Cap = 1nF @ AA22 G32 AA14
+3VALW VDDAN_11_PCIE_6 VSS VSS
For A12, Cap = DNI 1 2 M31 LDO_CAP VDDAN_11_PCIE_7 AF26 H12 VSS VSS AA16
LH4 CH46 2.2U_0603_6.3V4Z AG27 H15 AA17
VDDAN_11_PCIE_8 2 2 2 2 2 VSS VSS
1 2 +FCH_VDDPL_33_SSUSB_S 7mA 10mils H29 AA25

GROUND
MBK1608221YZF_2P VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

1 2 V21 VDDPL_11_DAC J6 VSS VSS AA28

RH116 0_0402_5% +1.1VS
CH52

CH53

226mA 60mils J9 VSS VSS AA30

220 ohm 1 1 VDDAN_11_SATA_1 AA21 1337mA+AVDD_SATA J10 VSS VSS AA32
20mils Y20 +AVDD_SATA 1 2 J13 AB25
VDDAN_11_SATA_4 RH118 0_0805_5% VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

22U_0805_6.3V6M
Y22 VDDAN_11_ML_1 VDDAN_11_SATA_2 AB21 J28 VSS VSS AC6

MAIN LINK

CH57

CH58

CH59

CH60

CH61
V23 AB22 J32 AC18

SERIAL ATA
2 2 RH117 VDDAN_11_ML_2 VDDAN_11_SATA_3 VSS VSS
V24 VDDAN_11_ML_3 VDDAN_11_SATA_5 AC22 1 1 1 1 1 K7 VSS VSS AC28
2 2
M3 only 12/19 change to GND 0_0603_5% V25 VDDAN_11_ML_4 VDDAN_11_SATA_6 AC21 K16 VSS VSS AD27
VDDAN_11_SATA_7 AA20 K27 VSS VSS AE6
VDDAN_11_SATA_8 AA18 K28 VSS VSS AE15
2 2 2 2 2

1
+VDDAN_33_USB AB20 L6 AE21
LH6 VDDAN_11_SATA_9 VSS VSS
VDDAN_11_SATA_10 AC19 L12 VSS VSS AE28
1 2+FCH_VDDPL_33_USB_S AB10 +3VALW L13 AF8
MBK1608221YZF_2P VDDIO_33_GBE_S VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

10mils 59mA L15 VSS VSS AF12

+VDDIO_33_S
CH62

CH63

220 ohm AB11 VDDCR_11_GBE_S_1 VDDIO_33_S_1 N18 1 2 L16 VSS VSS AF16

GBE LAN
RH119 0_0402_5%

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
1 1 AA11 VDDCR_11_GBE_S_2 VDDIO_33_S_2 L19 L21 VSS VSS AF33

CH64

CH65

CH66
VDDIO_33_S_3 M18 M13 VSS VSS AG30

3.3V_S5 I/O
1 2 AA9 VDDIO_GBE_S_1 VDDIO_33_S_4 V12 1 1 1 M16 VSS VSS AG32
RH120 0_0402_5% AA10 V13 M21 AH5
2 2 +3VALW VDDIO_GBE_S_2 VDDIO_33_S_5 VSS VSS
VDDIO_33_S_6 Y12 M25 VSS VSS AH11
LH7 658mA 30mils Y13 N6 AH18
+VDDAN_33_USB VDDIO_33_S_7 2 2 2 VSS VSS
1 2 G7 VDDAN_33_USB_S_1 VDDIO_33_S_8 W11 N11 VSS VSS AH19
FBMA-L11-201209-221LMA30T_0805
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K
H8 VDDAN_33_USB_S_2 N13 VSS VSS AH21
+3VS +3VALW
CH67

CH68

CH69

CH70

CH71
220 ohm/3A J8 VDDAN_33_USB_S_3 N23 VSS VSS AH23
LH8 1 1 1 1 1 K8 10mils 5mA LH9 N24 AH25
+VDDPL_33_PCIE VDDAN_33_USB_S_4 +VDDXL_3.3V VSS VSS
1 2 K9 VDDAN_33_USB_S_5 VDDXL_33_S G24 1 2 P12 VSS VSS AH27
MBK1608221YZF_2P MBK1608221YZF_2P
2.2U_0603_6.3V4Z

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
M9 VDDAN_33_USB_S_6 P18 VSS VSS AJ18
CH72

CH73

CH74

CH75
220 ohm 2 2 2 2 2
M10 VDDAN_33_USB_S_7 P20 VSS VSS AJ28
1 1 N9 VDDAN_33_USB_S_8 1 1 P21 VSS VSS AJ29
N10 VDDAN_33_USB_S_9 P31 VSS VSS AK21
M12 VDDAN_33_USB_S_10 P33 VSS VSS AK25
2 2
N12 VDDAN_33_USB_S_11 2 2 Del L30 R4 VSS VSS AL18
M11 VDDAN_33_USB_S_12 R11 VSS VSS AM21
+1.1VALW R25 AM25
LH10 +1.1VALW VSS VSS
140mA 10mils R28 VSS VSS AN1

USB
1 2 +VDDAN_11_USB_S U12 10mils 187mA T11 AN18
MBK1608221YZF_2P VDDAN_11_USB_S_1 +VDDCR_1.1V VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

U13 VDDAN_11_USB_S_2 VDDCR_11_S_1 N20 1 2 T16 VSS VSS AN28

+3VS RH121 0_0603_5%
CH76

CH77

1U_0402_6.3V6K

1U_0402_6.3V6K
220 ohm VDDCR_11_S_2 M20 T18 VSS VSS AN33
LH11

CH78

CH79
1 1
3 +VDDPL_33_SATA 3
1 2 1 1 SYSON 29,32,39 N8 VSSAN_HWM VSSPL_DAC T21
MBK1608221YZF_2P
2.2U_0603_6.3V4Z

.1U_0402_16V7K

VSSAN_DAC L28
CH80

CH81

220 ohm 2 2
K25 VSSXL VSSANQ_DAC K33

2
@

G
1 1 VSSIO_DAC N28
2 2 QH10 H25 VSSPL_SYS
3 1 AO3416L_SOT23-3 EFUSE R6
+1.1VALW

D
2 2 LH12 +1.1VALW
197mA 10mils
1 2 +VDDCR_1.1V_USB T12 10mils 70mA LH13
MBK1608221YZF_2P VDDCR_11_USB_S_1 +VDDPL_1.1V HUDSON-M2_FCBGA656
10U_0603_6.3V6M

2.2U_0603_6.3V4Z

.1U_0402_16V7K

.1U_0402_16V7K

T13 VDDCR_11_USB_S_2 VDDPL_11_SYS_S J24 1 2

MBK1608221YZF_2P
CH100

CH82

CH83

CH84

2.2U_0603_6.3V4Z
220 ohm

.1U_0402_16V7K
+1.1VS

CH85

CH86
1 1 1 1 Connected to VSS through a dedicated via.
1 1 LH14
1 @ 2
MBK1608221YZF_2P
2 2 2 2
2 2
220 ohm

+3VALW
+FCH_VDD_11_SSUSB_S 12mA
20mils 10mils +VDDAN_33_HWM
282mA P16 VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S M8 1 2
+VDDAN_SSUSB RH122 0_0402_5%

2.2U_0603_6.3V4Z
1 2 M14 AMD reply:

.1U_0402_16V7K
RH123 0_0603_5% VDDAN_11_SSUSB_S_2
1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

CH87

CH88
N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
CH89

CH90

CH91

For FCH M2 - BOM option 40mils P13 1 1 it to +3.3V_S5 directly if HWM is not used.
VDDAN_11_SSUSB_S_4
+FCH_VDD_11_SSUSB_S

VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S 1 1 1 P14 VDDAN_11_SSUSB_S_5

Connected to VSS.
USB SS

2 2
Del M2 BOM option. 2 2 2 30mils
N16 VDDCR_11_SSUSB_S_1
N17 +3VS
VDDCR_11_SSUSB_S_2
P17 VDDCR_11_SSUSB_S_3 10mils 26mA
M17 AA4 +VDDIO_AZ 1 2
4 VDDCR_11_SSUSB_S_4 VDDIO_AZ_S RH124 0_0402_5% VDDIO_AZ_S should be tied to 4
POWER 1 2 +3.3/1.5V_S5 rail if Wake on Ring
424mA CH92 2.2U_0603_6.3V4Z is supported
+1.1VALW 2 1 1 2 +VDDCR_11_SSUSB HUDSON-M2_FCBGA656 1 2
LH15 RH125 0_0603_5% CH93 .1U_0402_16V7K
10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

FBMA-L11-201209-221LMA30T_0805
CH94

CH95

CH96

CH97

M3 @-->SMT
42 ohm/4A 1 1 1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2 2 Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Hudson-M2/M3-POWER/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 17 of 47

A B C D E
 5 4 3 2 1

+3VS

D APU_LVDS_CLK D
1 2
R456 4.7K_0402_5%
APU_LVDS_DAT 1 2 U4
R459 4.7K_0402_5%
+AVDD12 1 AVDD12
ANX3112
10 APU_TXOUT0- APU_TXOUT0- 19
LVDS_L0_N APU_TXOUT0+
+AVDD33 4 AVDD25 LVDS_L0_P 11 APU_TXOUT0+ 19
16 AVDD25
19 12 APU_TXOUT1- APU_TXOUT1- 19
AVDD25 LVDS_L1_N APU_TXOUT1+
35 AVDD25 LVDS_L1_P 13 APU_TXOUT1+ 19
+1.2VS +DVDD12 APU_TXOUT2-
20mil +DVDD12 5 DVDD12 LVDS_L2_N 14
APU_TXOUT2+
APU_TXOUT2- 19
25 DVDD12 LVDS_L2_P 15 APU_TXOUT2+ 19
L16 2 1 0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K
TEST_EN 6 10K_0402_5% 2 1 R391 1:test mode
FBMA-L11-201209-221LMA30T_0805 2 2 2 2 1 1 1 8
C286 C287 C291 C303 C341 C332 C337
+DVDD33
22
DVDD25 0:normal mode
DVDD25 APU_TXOUT_CLK-
LVDS_CLKL_N 17 APU_TXOUT_CLK- 19
18 APU_TXOUT_CLK+ APU_TXOUT_CLK+ 19
1 1 1 1 2 2 2 LVDS_CLKL_P
0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V6K DP0_TXP0_C 2
8 DP0_TXP0_C DPRX_LN0_P
DP0_TXN0_C 3 1 2
8 DP0_TXN0_C DPRX_LN0_N 12K_0402_1% R434
36 R_BIAS 2 1
C
TL_ENVDD R_BIAS 100P_0402_50V8J C224
C
19 TL_ENVDD 9 DIGON
+1.2VS +AVDD12 TL_BKOFF#
20mil BL_EN 21 TL_BKOFF# 19
13,21,23 APU_PCIE_RST# 7 RESET_L
L17 2 1 0.1U_0402_16V7K 0.01U_0402_16V7K 30 T22
FBMA-L11-201209-221LMA30T_0805 APU_LVDS_CLK CFG_SCL
2 2 1 1 1 19 APU_LVDS_CLK 28 DDC_CLK
C333 C340 C334 C335 C336 19 APU_LVDS_DAT APU_LVDS_DAT 29 31 T23
DDC_DATA CFG_SDA

1 1 2 2 2
10 LVDS_HPD 32 DPRX_HPD PROG_SCL 23 T24
0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V6K R388 1 2
100K_0402_5% 24 T25
DP0_AUXN_C PROG_SDA
8 DP0_AUXN_C 33 DPRX_AUX_N
20mil DP0_AUXP_C 34
+3VS +DVDD33 8 DP0_AUXP_C DPRX_AUX_P

19 TL_INVT_PWM R414 1 2 0_0402_5% 26 20

L18 2 VARY_BL AVSS
1 0.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_08052 1 R435 1 2 0_0402_5% 27
10 APU_INVT_PWM CPU_VARY_BL
C338 C339
Epad 37
1 2 ANX3112_QFN36_6X6
B B
2.2U_0603_6.3V6K

+3VS +AVDD33
20mil

L19 2 1 0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K

FBMA-L11-201209-221LMA30T_0805 +3VS
2 2 2 1 1 1
C347 C342 C343 C344 C345 C346

DP0_AUXP_C 2 @ 1
1 1 1 2 2 2 R450 1M_0402_5%
0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V6K
DP0_AUXN_C 2 @ 1
R451 1M_0402_5%

Place via on each trace bus and let resistor very close the via
A A

Security Classification Compal Secret Data

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2136S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8731P
Date: Tuesday, December 27, 2011 Sheet 18 of 47
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+LCDVDD INVPWR_B+ L7 B+
W=60mils FBMA-L11-201209-221LMA30T_0805
+3VS Place closed to JLVDS1 2 1

1
+3VALW +LCDVDD
+3VS
R61
W=60mils
100_0603_5%

1
1 1 1 1 1 1

2
D R62 C55 C56 C57 C58 C59 C60 SM010014520 3000ma D
100K_0402_5% 680P_0402_50V7K 68P_0402_50V8J
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z
220ohm@100mhz
2 2 2 2 2 2 DCR 0.04

2
R63

3
200K_0402_5% S Q8
AO3413L_SOT23-3
Q6A
DMN66D0LDW-7_SOT363-6 1
2 2 1

1
2
G
D
LCD/LED PANEL Conn.

1
C61 +LCDVDD
0.047U_0402_16V7K
W=60mils W=60mils
W=60mils LCD_CLK
2
1 1 LCD_DATA

3
C63 1 1
0.1U_0402_16V4Z @ C64 @ C65
C62 10P_0402_50V8J 10P_0402_50V8J
TL_ENVDD 2 2
18 TL_ENVDD 5
4.7U_0603_6.3V6K 2 2
Q6B
4

DMN66D0LDW-7_SOT363-6
9/8 SI build BOT limit 0.8, C62
del: SE053475Z80
add: SE107475K80 Check pin definition.
+LCDVDD
C C

@
R156 1 2 0_0402_5%
WCM-2012-900T_4P
USB20_P5 4 3 USB20_P5_R
15 USB20_P5 4 3 JLVDS1
1 1
USB20_N5 1 2 USB20_N5_R 2
15 USB20_N5 1 2 2
18 APU_LVDS_CLK APU_LVDS_CLK R193 2 1 0_0402_5% LCD_CLK 3
L11 APU_LVDS_DAT R194 2 3
18 APU_LVDS_DAT 1 0_0402_5% LCD_DATA 4 4
5 5
1 R229 2 0_0402_5% 6 6
7 7
@ 8 8
9 9
8/19 change stuff L26 by EMI request 10 10
11 11
18 APU_TXOUT1- 12 12
@ 12/21 for AMD issue workaround 13
18 APU_TXOUT1+ 13
29 EC_INVT_PWM 1 R198 2 0_0402_5% INVTPWM 14 14
18 APU_TXOUT0- 15 15
18 APU_TXOUT0+ 16 16
18 TL_INVT_PWM 1 R202 2 0_0402_5% USB20_N5 17 17
18 APU_TXOUT2+ 18 18 For easier layout routing
1

@ 19
18 APU_TXOUT2- 19 change the pin order 12.08
1
B R72 20 B
R189 20
10K_0402_5% 18 APU_TXOUT_CLK+ 21 21
300_0402_5% 18 APU_TXOUT_CLK- 22 22
23 23
2

24 24
2

D8 Check 25 25
Check ? 1 10P_0402_50V8J INVTPWM 26 26
C285 D_MIC_CLK 2 DISPOFF# 27
2 27
1 1 28 28
D_MIC_DATA 3 INVPWR_B+ USB20_N5_R 29
2 3 USB20_P5_R 29
30 30
1 R204 2 0_0402_5% PESD5V0U2BT 31 31
ENBKL 10,29 32
@ +3VS 32
D_MIC_CLK 33
@1 R201 11.01 Add ESD solution (reserved) 25 D_MIC_CLK 33
18 TL_BKOFF# 2 0_0402_5% DISPOFF#
25 D_MIC_DATA
D_MIC_DATA 34 34
35 35
36 36 G1 41
29 BKOFF# 1 R203 2 0_0402_5% 37 37 G2 42
38 38 G3 43
39 39 G4 44
1

40 40 G5 45
R74
@ 10K_0402_5% STARC_111H40-100000-G4-R

@
2

A A

C66 1 220P_0402_50V7K INVTPWM

2 Security Classification Compal Secret Data Compal Electronics, Inc.
C67 2 1 220P_0402_50V7K DISPOFF#
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8731P
Date: Tuesday, December 27, 2011 Sheet 19 of 47
5 4 3 2 1
 5 4 3 2 1

PCH_DPB_P3_C 0.1U_0402_16V7K 1 2 C270 APU_HDMI_TXC+ 8

PCH_DPB_N3_C 0.1U_0402_16V7K 1 2 C271 APU_HDMI_TXC- 8
PCH_DPB_P2_C 0.1U_0402_16V7K 1 2 C272 APU_HDMI_TXD2+ 8 W=40mils
PCH_DPB_N2_C 0.1U_0402_16V7K 1 2 C273 APU_HDMI_TXD2- 8 +HDMI_5V_OUT
PCH_DPB_P1_C 0.1U_0402_16V7K 1 2 C274 APU_HDMI_TXD1+ 8 D57 F1
PCH_DPB_N1_C 0.1U_0402_16V7K 1 2 C275 APU_HDMI_TXD1- 8 +5VS 2 1 +HDMI_5V 1 2
1
PCH_DPB_P0_C 0.1U_0402_16V7K 1 2 C276 APU_HDMI_TXD0+ 8 CH491DPT_SOT23-3 1.1A_6V_SMD1812P110TF
PCH_DPB_N0_C 0.1U_0402_16V7K 1 2 C277 APU_HDMI_TXD0- 8 C279

0.1U_0402_16V4Z 2

1
R376715_0402_1%

R377715_0402_1%

R378715_0402_1%

R379715_0402_1%

R380715_0402_1%

R381715_0402_1%

R382715_0402_1%

R383715_0402_1%
Q27
D 2N7002K_SOT23-3 D
2

2
1 3

S
HDMI +3VS

G
R384
12/15 change to 715 ohm for AMD request

2
+HDMI_5V_OUT 1 2 Follow Intel 4.7K_0402_5%
R386
Feedback putting

1
0_0402_5% 1 2
R385
2.2K ohm
100K_0402_5%

5
Q147B

2
4 3 HDMI_SCLK
8 APU_HDMI_CLK
2N7002DWH_SOT363-6
SB00000AR10

+3VS +5VS +3VS

1 2
1

R387 R390
4.7K_0402_5%

2
1K_0402_5% R393
4.7K_0402_5% 1 6 HDMI_SDATA
8 APU_HDMI_DATA
3 2

2N7002DWH_SOT363-6
8 DP2_HPD 2
SB00000AR10 Q147A
Q47B
2N7002KDW_SOT363-6
5 5V PULL UP IN CONNECTER SIDE
6

C C
Q47A
4

2N7002KDW_SOT363-6
2 HP_DETECT
1

R389
100K_0402_5%
2

+HDMI_5V_OUT

2K_0402_1%
1

1
R395 R396 JHDMI1
2K_0402_1% HP_DETECT 19
10/13 change conn to 
HP_DET
18
+HDMI_5V_OUT
17
+5V DC232001000
DDC/CEC_GND

2
SM070001310 400ma 90ohm@100mhz DCR 0.3 HDMI_SDATA 16
HDMI_SCLK SDA
15 SCL
@ @ 14 Reserved

10P_0402_50V8J

10P_0402_50V8J
1 1 13 CEC
C280 C281 HDMI_R_CK- 12 20
CK- GND
11 CK_shield GND 21
@ HDMI_R_CK+ 10 22
PCH_DPB_P3_C R392 1 0_0402_5% HDMI_R_CK+ @1 2 2 HDMI_R_D0- CK+ GND
2 2 9 D0- GND 23
C509 33P_0402_50V8J 8
HDMI_R_D0+ D0_shield
4 4 3 3 7 D0+
HDMI_R_D1- 6
WCM-2012-900T_0805 D1-
5 D1_shield
L29 1 2 HDMI_R_D1+ 4
1 2 HDMI_R_D2- D1+
3 D2-
PCH_DPB_N3_C R394 1 2 0_0402_5% HDMI_R_CK- @1 2 2
@ C510 33P_0402_50V8J HDMI_R_D2+ D2_shield
1 D2+
@ HONGL_13-13201904CP
B B
PCH_DPB_P0_C R397 1 2 0_0402_5% HDMI_R_D0+ @1 2
C511 33P_0402_50V8J
1 1 2 2
L30
WCM-2012-900T_0805
4 4 3 3

PCH_DPB_N0_C R398 1 2 0_0402_5% HDMI_R_D0- @1 2

@ C512 33P_0402_50V8J

PCH_DPB_P1_C R399 1 @ 2 0_0402_5% HDMI_R_D1+ @1 2

C513 33P_0402_50V8J
4 4 3 3
WCM-2012-900T_0805
L31 1 2
1 2
PCH_DPB_N1_C R400 1 2 0_0402_5% HDMI_R_D1- @1 2
@ C514 33P_0402_50V8J

PCH_DPB_P2_C R401 1 @ 2 0_0402_5% HDMI_R_D2+ @1 2

C515 33P_0402_50V8J
4 4 3 3
WCM-2012-900T_0805
L32 1 2
1 2
PCH_DPB_N2_C R402 1 2 0_0402_5% HDMI_R_D2- @1 2
@ C516 33P_0402_50V8J

Follow EMI request add 33pF cap to GND.

11.02
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8731P
Date: Tuesday, December 27, 2011 Sheet 20 of 47
5 4 3 2 1
 5 4 3 2 1

+3V_AOAC

12.08 R73 pull high

1
R73 @ WLAN
10K_0402_5%
+3V_AOAC +1.5VS_WLAN
+3V_AOAC

2
D D
R84
0_0402_5% JMINI1 CONN@
15,23 FCH_PCIE_WAKE# 1 2 1 1 2 2
R93 3 4
BT_ON BT_ON_L 3 4
1 2 5 5 6 6
15 MINI1_CLKREQ# 0_0402_5% 7 8 LPC_FRAME#
7 8 LPC_FRAME# 13,29,31
9 10 LPC_AD3
9 10 LPC_AD3 13,29,31
11 12 LPC_AD2
D 13 CLK_PCIE_MINI1# 11 12 LPC_AD2 13,29,31
1 13 CLK_PCIE_MINI1 13 13 14 14 LPC_AD1
LPC_AD1 13,29,31
14 BT_ON# BT_ON# 2 15 16 LPC_AD0
15 16 LPC_AD0 13,29,31
G
Q26 S
3

2N7002_SOT23-3 APU_PCIE_RST# 17 18
LPC_CLK0_EC 17 18 WL_OFF#
13,16,29,31 LPC_CLK0_EC 19 19 20 20 WL_OFF# 14
21 22 APU_PCIE_RST# APU_PCIE_RST# 13,18,23
21 22 R85
6 PCIE_DTX_C_FRX_N1 23 23 24 24 1 2 0_0603_5% +3V_AOAC
6 PCIE_DTX_C_FRX_P1 25 25 26 26 12/21 for AMD issue workaround
27 27 28 28
29 29 30 30
6 PCIE_FTX_C_DRX_N1 31 31 32 32
33 34 USB20_N8
6 PCIE_FTX_C_DRX_P1 33 34
35 36 USB20_N8_R R88 1 2 0_0402_5% USB20_N8
35 36 USB20_N8 15
37 38 USB20_P8_R R89 1 2 0_0402_5% USB20_P8
37 38 USB20_P8 15

1
39 39 40 40
41 42 R187
41 42 MINI1_LED#
43 43 44 44 MINI1_LED# 29 300_0402_5%
R58 45 46
0_0402_5% 45 46
47 47 48 48

2
1
C E51TXD_P80DATA 1 2 E51TXD_P80DATA2_R 49 50 C
29 E51TXD_P80DATA 49 50
29 E51RXD_P80CLK 1 2 E51RXD_P80CLK_R 51 51 52 52 R92 1 10P_0402_50V8J
53 54 4.7K_0402_5% C284
0_0402_5% G1 G2
1

R57
(9~16mA) 2

2
BELLW_80003-2021
R70
+3V_AOAC
100K_0402_5%
2

BT_ON 2 1 E51RXD_P80CLK_R

For Wireless LAN

1K_0402_5%
R326

+3VS +3V_AOAC
R83
0_1206_5% +1.5V_PCIE +1.5VS_WLAN
60mil
2 1
R82 0_0603_5%
1 1 1 2
C86 C87 1 1 1
C82 C83 C84
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 4.7U_0603_6.3V6K
2 2 2
Mini Card Power Rating
Power Primary Power (mA) Auxiliary Power (mA)
B B
Peak Normal Normal
+3VS 1000 750
+3V 330 250 250 (wake enable)
+1.5VS 500 375 5 (Not wake enable)

11/23 Del AOAC

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MiniCard & WLan
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8731P
Date: Tuesday, December 27, 2011 Sheet 21 of 47

5 4 3 2 1
 5 4 3 2 1

mSATA Conn.

12/12 Del mSATA by customer

D D

+3VS 100mils
C C

SATA Redriver Layout note: Close to U50 +5VS +5VS_HDD1

0.1U_0402_16V7K

0.01U_0402_16V7K
1U_0603_10V6K
1 1 1 1 2
R2685 0_0805_5%

C656

C657

C658

10U_0805_10V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K
2 2 2 1 1 1 1

C616

C617

C618

C619
@

2 2 2 2

12/8 Co-lay Parade repeater SA00004WF00

+3VS +3VS

@ U50
R715 1 2 10K_0402_5% 7 6
EN VDD
VDD 16
14 SATA_STX_DRX_P0 SATA_STX_DRX_P0 0.01U_0402_16V7K 1 @2 C659 SATA_STX_DRX_P0_R 1
SATA_STX_DRX_N0 0.01U_0402_16V7K @2 C660 SATA_STX_DRX_N0_R A_INp @
14 SATA_STX_DRX_N0 1 2 A_INn NC 10
20 R727 1 2 4.99K_0402_1%
SATA_DTX_SRX_P0 0.01U_0402_16V7K @2 C661 SATA_DTX_SRX_P0_R REXT
14 SATA_DTX_SRX_P0 SATA_DTX_SRX_N0 0.01U_0402_16V7K
1
@2 C662 SATA_DTX_SRX_N0_R
5 B_OUTp A_PRE0
12/21 change net name to connector side
14 SATA_DTX_SRX_N0 1 4 B_OUTn A_PRE0 9
8 B_PRE0
B_PRE1 B_PRE0
17 B_PRE1
A_PRE1 19 15 SATA_PTX_C_DRX_P0_R R192 2 @ 1 0_0402_5% SATA_STX_C_DRX_P0
@ A_PRE1 A_OUTp SATA_PTX_C_DRX_N0_R R195 @ SATA_STX_C_DRX_N0
A_OUTn 14 2 1 0_0402_5%
+3VS R720 1 2 10K_0402_5% 18 TEST SATA_PRX_C_DTX_P0_R R196 @ SATA_DTX_C_SRX_P0
B
3 GND B_INp 11 2 1 0_0402_5% B
13 12 SATA_PRX_C_DTX_N0_R R197 2 @ 1 0_0402_5% SATA_DTX_C_SRX_N0
GND B_INn
21 EPAD
PS8520BTQFN20GTR2_TQFN20_4X4

+5VS_HDD1 JHDD1 CONN@

1 1
2 2
3 3
4 4
SATA_STX_DRX_P0 C612 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_P0 5
SATA_STX_DRX_N0 C613 1 SATA_STX_C_DRX_N0 5
Note: Add EQ pin for STA1102RQTR 2 0.01U_0402_16V7K 6 6
7 7
SATA_DTX_SRX_N0 C614 1 2 0.01U_0402_16V7K SATA_DTX_C_SRX_N0 8
+3VS SATA_DTX_SRX_P0 C611 1 SATA_DTX_C_SRX_P0 8
2 0.01U_0402_16V7K 9 9
10 10
11 GND
A_PRE0 1 @ 2 12
R709 4.7K_0402_5% GND
B_PRE0 1 @ 2
R711 4.7K_0402_5% ACES_50463-0104A-001
A_PRE1 1 @ 2
R713 4.7K_0402_5%
B_PRE1 1 @ 2
R716 4.7K_0402_5%
A
SATA connector A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
mSATA Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 22 of 47

5 4 3 2 1
 5 4 3 2 1

@
12/08 change to +5VALW
W=60mils R404 0_1206_5%
W=60mils +5VALW
+3VALW 1 2
+CR_VDD_3V3
Q148 +LAN_VDD_3V3 JP10 +3VS
1.5A
These caps close to U1: Pin 11,12,39,58,63,64 SD_D3_R
1 1 2 2
1 3 1 3 4

D
C294 AO3413L_SOT23-3 SD_CMD_R 3 4 SATA_LED#
5 6

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
SD_CLK_R 5 6 HDDHALT_LED# SATA_LED# 14

10U_0603_6.3V6M
1U_0402_6.3V6K 1 1 1 1 1 1 1 C301 7 8

G
SD_D0_R 7 8 PWR_LED# HDDHALT_LED# 13
9 9 10 10
PWR_LED# 29,30

2
2 C295 C296 C297 C298 C299 C300 SD_D1_R TP_ON_OFF_LED#
11 11 12 12 TP_ON_OFF_LED# 29
+VSB SD_D2_R 13 14
2 2 2 2 2 2 2 SD_WP 13 14
15 15 16 16
SD_CD# 17 18
17 18

2
19 19 20 20
R405 Note:
470K_0402_5% 1. C38: Close to Pin12(DVDD33) for avoiding voltage drop when inserting card. 21 22
2. The rise time of +LAN_VDD_3V3 must >1ms and <100ms for the internal LDO. GND GND
D
23 GND GND 24 D
25 GND GND 26

1
EN_WOL

1.5M_0402_5%
1 D

2
PANAS_AXK7L20213G
2 Q149 R406 1
29 WOL_EN
SSM3K7002FU_SC70-3 C302
Need to check connect EC or to PCH
G
S 0.1U_0603_25V7K
3

10/13 by Karl

1
2

R407 0_0402_5%
SD_D0 1 2 SD_D0_R
R409 0_0402_5%
+LAN_VDD_3V3 R408 1 @ 2 10K_0402_5% U70 SD_D1 1 2 SD_D1_R
Power Manahement/Isolation R411 0_0402_5%
29 EC_PME# R410 1 2 0_0402_5% ISOLATEB 38 SD_D2 1 2 SD_D2_R
LANWAKEB ISOLATEB R413 0_0402_5%
40 LANWAKEB
15,21 FCH_PCIE_WAKE# R412 1 2 0_0402_5% Card Reader 19 SD_D0 SD_D3 1 2 SD_D3_R
SD_D0/MS_D7/xD_D5 SD_D1
+LAN_VDD_3V3 1 R2887 2 @ SD_D1/MS_CLK/xD_D6 18 R415 0_0402_5%
10K_0402_5% PCI-Express 23 SD_D2 SD_CMD 1 2 SD_CMD_R
R417 CLK_PCIE_LAN SD_D2/xD_D7 SD_D3 R416 0_0402_5%
13 CLK_PCIE_LAN 27 REFCLK_P SD_D3/MS_D2/xD_D2 22
0_0402_5% CLK_PCIE_LAN# 28 17 SD_CLK 1 2 SD_CLK_R
13 CLK_PCIE_LAN# REFCLK_N SD_D4/xD_WE#
LAN_CLKREQ# 2 1 LAN_CLKREQ#_R 16

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C
15 LAN_CLKREQ# SD_D5/xD_CE#
13,18,21 APU_PCIE_RST# 37 PERSTB SD_D6/MS_INS#/xD_RE# 15 1 1 1 1 1 1
LAN_CLKREQ#_R

@ C503

@ C504

@ C505

@ C506

@ C507
36 CLKREQB SD_D7/xD_RDY 14
20 SD_CLK C305 @
C306 1 PCIE_DTX_FRX_P0 SD_CLK/MS_D3/xD_D4 SD_CMD
6 PCIE_DTX_C_FRX_P0 2 0.1U_0402_16V7K 30 HSOP SD_CMD/MS_D6/xD_D3 21 5P_0402_50V8C
C307 1 PCIE_DTX_FRX_N0 SD_WP 2 2 2 2 2 2
6 PCIE_DTX_C_FRX_N0 2 0.1U_0402_16V7K 31 HSON SD_WP/MS_D1/xD_WP# 35
PCIE_FTX_C_DRX_P0 25 54 SD_CD#
6 PCIE_FTX_C_DRX_P0 HSIP SD_CD#/MS_D5/xD_ALE
PCIE_FTX_C_DRX_N0 26 34
6 PCIE_FTX_C_DRX_N0 HSIN MS_BS/xD_CLE
MS_D4/xD_D0 55
R418 1.5K_0402_5% EEPROM(TWSI)
Strapping SDA MS_D0/xD_D1 56

ISOLATEB
+LAN_VDD_3V3 1 2 44 SDA XD_CD# 57
Reserved for LAN PHY Disable Application
EMI-ESD
C
+3VS 1 2 42 SCL/LED_CR
C
R420 1K_0402_5% LAN_ACTIVITY# C308 1 2 470P_0402_50V8J
PN : SA00005B400
Transceiver Interface
GPO Pin
GPO 50 GPO
GPO
R419 0_0402_5%
1 @ 2
2

LAN_MDIP0 1 12
R421 LAN_MDIN0 MDIP0 DVDD33 +LAN_VDD_3V3 LINK_100_1000# C309 1
2 MDIN0 DVDD33 39 2 470P_0402_50V8J
15K_0402_5% LAN_MDIP1 4
LAN_MDIN1 MDIP1
5 MDIN1 AVDD33 11
LAN_MDIP2 6 58 +LAN_VDD_3V3
MDIP2 AVDD33
1

LAN_MDIN2 7 63 D58
LAN_MDIP3 MDIN2 AVDD33 LAN_ACTIVITY#
9 MDIP3 AVDD33 64 2
LAN_MDIN3 10 1
MDIN3 +LAN_VDD_1V0 SD_CD# LINK_100_1000# 3
Delete 0 ohm DVDD10 41 2 1 R200
27P_0402_50V8J C310 52 100K_0402_5%
1 2 XTLI 11.05 XTLI 59
DVDD10 TVNST52302AB0_SOT523-3
XTLO CKXTAL1 Clock
60 CKXTAL2 AVDD10 3
2

AVDD10 8
Y9 61
Regulator and Reference AVDD10 +CR_VDD_3V3
25MHZ_12PF_X5H025000FC1H-H
+LAN_SROUT1.0V 48 29 +LAN_EVDD10
REGOUT EVDD10
1

XTLO ENSWREG

0.1U_0402_10V7K
C312
1 2 45 ENSWREG_H VDD33/18 for SD UHS Mode Power
Card_3V3 13 1
27P_0402_50V8J C311 +LAN_VDDREG 46 +VDD33/18
VDDREG +VDD33/18
47 VDDREG VDD33/18 33

0.1U_0402_10V7K
C315

0.1U_0402_10V7K
C314
R425 53 C313 C316
VDD33/18 2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 2 62 RSET 1 1 1 1
R426 0_0402_5% 24 JLAN1
ENSWREG 2.49K_0402_1% GND @
+LAN_VDD_3V3 2 1 GND 32
LAN_LED0 51 65 @ 12
R424 0_0402_5% LAN_LED1 LED0 LEDs GND9(Exposed Pad) 2 2 2 2 RJ45_TX3- GND
49 LED1 8 PR4-
2 1 43 LED3 GND 11
@ RJ45_TX3+ 7 PR4+
3.3V : Enable Switching Regulator Close to Pin33 Close to Pin53 RJ45_RX1- 6
RTL8411-CG_QFN64_9X9 PR2-
(Default,For Power Efficiency)
0V : Enable LDO Regulator RJ45_TX2- 5 PR3-
Switching Regulator Circuit +LAN_VDD_1V0 RJ45_TX2+ 4 PR3+
SHI0000AA00 +LAN_VDD_1V0 R427
+LAN_VDD_3V3 L33 W=60mils 1 2 +LAN_EVDD10 +LAN_VDD_1V0 RJ45_RX1+ 3
B
R428 +LAN_SROUT1.0V 1 PR2+ B
2
1U_0402_6.3V6K
0.1U_0402_16V7K

1 2 +LAN_VDDREG 2.2UH +-5% NLC252018T-2R2J-N 0_0603_5% RJ45_TX0- 2

DELTA_1008HC-472EJFS-A_2P PR1-
10
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1 2 1 1 GND
0_0603_5% 1 1 1 1 1 C326 1 1 RJ45_TX0+ 1
C319 C320 C321 C322 PR1+
GND 9
C317 C318 0.1U_0402_16V7K C323 C324 C325 C327
4.7U_0603_6.3V6K 2 1 2 2
2 2 2 2 2 2 2 SANTA_130460-1

Close to Pin46,47 4.7U_0603_6.3V6K Close to Pin29

@
Place each cap. to Pin 3, 8 , 41 , 52 ,61

TS1
LAN_MDIP0 1 24 RJ45_TX0+
TD1+ TX1+
+3VS
Amber LED10
LAN_MDIN0 2 TD1- TX1- 23 RJ45_TX0-

510_0402_5% R423 +V_DAC 3 22 R430 1 2 75_0402_5%

LAN_LED0 2 TDCT1 TXCT1
1 LAN_ACTIVITY# 1 2 R431 1 2 75_0402_5%
+V_DAC 4 21 R432 1 2 75_0402_5%
TDCT2 TXCT2 R433 75_0402_5%
1 2
HT-110UD_1204 LAN_MDIP1 5 20 RJ45_RX1+
TD2+ TX2+
3

C328 1 2 LAN_MDIN1 6 19 RJ45_RX1- 2

TD2- TX2- C329
0.01U_0402_16V7K LAN_MDIP2 7 18 RJ45_TX2+ SE167100J80
TD3+ TX3+ 10P_1808_3KV
+5VS 1
White @
C508
LAN_MDIN2 8 TD3- TX3- 17 RJ45_TX2-
1 1
LED9 2 1 +V_DAC 9 16 C330 C331
TDCT3 TXCT3
3

1
LAN_LED1 2 R429 1 LINK_100_1000# 1 2 +V_DAC 10 15 D59 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
510_0402_5% 0.1U_0402_16V7K TDCT4 TXCT4 L34 2 2
A LAN_MDIP3 11 14 RJ45_TX3+ TVNST52302AB0_SOT523-3 A
LTW-110DC5-C_WHITE TD4+ TX4+
3

LAN_MDIN3 12 13 RJ45_TX3-
TD4- TX4-
1

Add LAN LED White& Amber on M/B 100UH_SSC0301101MCF_0.18A_20%

2
10/12 350UH_NA0069RLF
Change P/N from SCA00000T00 to SCA00001L00
SP050006Y00 11.01

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/0/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN&CardReader Realtek RTL8411
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 23 of 47
5 4 3 2 1
 A B C D E

+3VS +3VS
Programmable output pre‐emphasis level setting for
USB3.0 need support 2.5A
USB3.0 change USB PWR SW SA00003TV00
channel A1&A2, B1&B2

1
R403 3.3V tolerant. Internally pulled down at ~150KΩ
+5VALW low active +USB_AS
W=80mils 4.7K_0402_5% UR1 [A_DE1, A_DE0] [B_DE1, B_DE0] == ==
W=80mils U3 LL: 3.5dB de‐emphasis

2
1000P_0402_50V7K
1 8 33 LH: No de‐emphasis

150U_B2_6.3VM_R45M

0.1U_0402_16V4Z
GND VOUT USB3_RX0_N 0.1U_0402_10V7K USB3_RX0_R_N EPAD A_EQ0
1 C98

1000P_0402_50V7K
2 VIN VOUT 7 15 USB3_RX0_N 2 1 A1_OUTn NC 32
3 6 1 15 USB3_RX0_P
USB3_RX0_P 0.1U_0402_10V7K 2 1 C97 USB3_RX0_R_P 2 31 A_EQ1 HL: 2.7dB de‐emphasis
VIN VOUT A1_OUTp NC R732 1
4 EN FLG 5 1 1 3 GND REXT 30 2 4.99K_0402_1% HH: 5.0dB de‐emphasis
+ USB3_TX0_N 0.1U_0402_10V7K 2 1 C115 USB3_TX0_R_N 4 29 A_DE0
1 1 15 USB3_TX0_N B1_INn NC
G547I2P81U_MSOP8 C90 C91 C92 USB3_TX0_P 0.1U_0402_10V7K 2 1 C99 USB3_TX0_R_P 5 28 A_DE1

0.1U_0402_16V4Z
15 USB3_TX0_P B1_INp NC
C88 C89 6 27 USB3_RX0_C_N
2 2 2 USB3_RX1_N 0.1U_0402_10V7K USB3_RX1_R_N I2C_EN A1_INn USB3_RX0_C_P
15 USB3_RX1_N 2 1 C125 7 A2_OUTn A1_INp 26
2 2 USB3_RX1_P 0.1U_0402_10V7K USB3_RX1_R_P
15 USB3_RX1_P 2 1 C118 8 A2_OUTp VDD 25
9 24 USB3_TX0_C_N
1
USB3_TX1_N 0.1U_0402_10V7K USB3_TX1_R_N VDD B1_OUTn USB3_TX0_C_P +3VS 1
R94 15 USB3_TX1_N 2 1 C127 10 B2_INn B1_OUTp 23
15 USB3_TX1_P USB3_TX1_P 0.1U_0402_10V7K 2 1 C126 USB3_TX1_R_P 11 22 USB_Test
USB_OC0# B2_INp TEST USB3_RX1_C_N
1 2 USB_OC0# 15 12 PD# A2_INn 21
B_EQ0 13 20 USB3_RX1_C_P
USB_ON# 0_0402_5% B_EQ1 SDA_CTL A2_INp
29 USB_ON# 14 SCL_CTL GND 19
@ B_DE0 15 18 USB3_TX1_C_N B_EQ0 R422 1 2 4.7K_0402_5%
B_DE1 I2C_ADDR0 B2_OUTn USB3_TX1_C_P B_EQ1 R436 @ 4.7K_0402_5%
16 I2C_ADDR1 B2_OUTp 17 1 2
SI# 8/8 change USB_OC0# to USB30_OC# B_DE0 R437 1 @ 2 4.7K_0402_5%
B_DE1 R439 1 @ 2 4.7K_0402_5%
A_EQ0 R440 1 2 4.7K_0402_5%
A_EQ1 R438 1 @ 2 4.7K_0402_5%
PS8720BTQFN32GTR-A0_TQFN32_3X6 A_DE0 R441 1 @ 2 4.7K_0402_5%
A_DE1 R442 1 @ 2 4.7K_0402_5%
USB_Test R443 1 @ 2 4.7K_0402_5%
Change conn to SANTA‐373070 +USB_AS
+USB_AS
10/18 Change P/N from SCA00000T00 to SCA00001L00
JUSB1 @ Change conn to SANTA‐373070
1 11.01
USB20_N10_C 2
VBUS 10/18
USB20_P10_C D- USB20_N10_C USB20_N11_C JUSB4 @
3 D+
4 USB20_P10_C USB20_P11_C 1
USB3RXDN0_C GND USB20_N11_C VBUS +3VS
5 SSRX- 2 D-
USB3RXDP0_C 6 10 USB20_P11_C 3
SSRX+ GND D+

3
7 GND GND 11 4 GND
USB3TXDN0_C 0.1U_0402_10V7K 2 1 C93 USB3TXDN0_C_R 8 12 D10 D11 USB3RXDN1_C 5

3
USB3TXDP0_C 0.1U_0402_10V7K 2 USB3TXDP0_C_R SSTX- GND USB3RXDP1_C SSRX-
1 C94 9 SSTX+ GND 13 6 SSRX+ GND 10
7 GND GND 11 1 1
USB3TXDN1_C USB3TXDN1_C_R

1
SANTA_373070-1 0.1U_0402_10V7K 2 1 C96 8 12
PESD5V0U2BT PESD5V0U2BT USB3TXDP1_C 0.1U_0402_10V7K USB3TXDP1_C_R SSTX- GND
2 1 C95 9 SSTX+ GND 13 C129 C128

1
0.01U_0402_16V7K 0.1U_0402_10V7K
SANTA_373070-1 2 2

2 R227 @ 0_0402_5% D9 R141 @ 0_0402_5% 2

USB3_TX0_C_N 1 2 USB3TXDN0_C USB3RXDN0_C 1 1 109 USB3RXDN0_C USB3_TX1_C_N 1 2 USB3TXDN1_C

WCM-2012-900T_4P USB3RXDP0_C 2 2 98 USB3RXDP0_C L24

4 4 3 3 1 1 2 2
USB3TXDN0_C_R 4 4 77 USB3TXDN0_C_R

1 2 USB3TXDP0_C_R 5 5 66 USB3TXDP0_C_R 4 3
1 2 4 3
L21 3 3 WCM-2012-900T_4P
USB3_TX0_C_P 1 2 USB3TXDP0_C USB3_TX1_C_P 1 2 USB3TXDP1_C
R228 @ 0_0402_5% 8 R142 @ 0_0402_5%
R231 @ 0_0402_5% @
USB3_RX0_C_N 1 2 USB3RXDN0_C IP4292CZ10-TB USB3_RX1_C_N R2231 2 0_0402_5% USB3RXDN1_C
6/27 Add ESD solution
WCM-2012-900T_4P Part Number = SC300002500 L25
4 4 3 3 1 1 2 2

1 1 2 2 4 4 3 3
D12
L22 USB3RXDN1_C 1 1 109 USB3RXDN1_C WCM-2012-900T_4P
USB3_RX0_C_P 1 2 USB3RXDP0_C USB3_RX1_C_P 1 2 USB3RXDP1_C
R232 @ 0_0402_5% USB3RXDP1_C 2 2 98 USB3RXDP1_C R224 @ 0_0402_5%

R233 @ 0_0402_5% USB3TXDN1_C_R 4 4 77 USB3TXDN1_C_R

USB20_N10 1 2 USB20_N10_C R236 @ 0_0402_5%
15 USB20_N10
USB3TXDP1_C_R 5 5 66 USB3TXDP1_C_R USB20_N11 1 2 USB20_N11_C
WCM-2012-900T_4P 15 USB20_N11
4 4 3 3 3 3 L26
1 1 2 2
8
1 1 2 2
IP4292CZ10-TB 4 3
L23 6/27 Add ESD solution 4 3
USB20_P10 1 2 USB20_P10_C Part Number = SC300002500 WCM-2012-900T_4P
15 USB20_P10
R234 @ 0_0402_5% USB20_P11 1 2 USB20_P11_C
15 USB20_P11
R235 @ 0_0402_5%
3 3

+3VS +3VS

12/21 for AMD issue workaround

2

2
R133 R135
USB2.0 & charger 10K_0402_5% 10K_0402_5%
@ USB20_N11 USB20_N10 U2D_DN0
2 1

2 1

1
USB charger footprint need change to TPS2543 USB_CTL1_R USB_CTL2_R
R179 R181 R199
TPS2543 : SA000059H00 pin 9 (Status); 2540 pin9 (NC) Pre MP:Add C923 C924 @ R139 R143 300_0402_5% 300_0402_5% 300_0402_5%
100K_0402_5% 100K_0402_5%
@

2
1

+5VALW +USB_VCCB
1 10P_0402_50V8J 1 10P_0402_50V8J 1 10P_0402_50V8J
JIO1 @ C282 C283 C288
@ 27 HP_R HP_R 1 1
150U_B2_6.3VM_R35M

2 2
HP_L 2 2 2
1000P_0402_50V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 27 HP_L 3 3
HP_DET#
0.1U_0402_16V4Z

1 1 1 1 25 HP_DET# 4 4
+ MIC1_L
C667

10U_0603_6.3V6M
C2543

C669

1 28 MIC1_L 5 5
MIC1_R
C2507

C927

C928

28 MIC1_R 6 6
MIC_SENSE 7
2 2 2 2 2 25 MIC_SENSE 7
8 8
2
9 9
+USB_VCCB 10

PVT:Update net USB_CHARGE_EN#-->USB_CHARGE_EN 1

U27
12 U2D_DN0_C
11
12
10
11 Check mode wtih customer?
@ IN OUT U2D_DP0_C 12
13 13
R994 1 2 0_0402_5% 13 9 14
15

<PCH>
USB_OC1#
USB20_N0 2
FAULT# NC
11 U2D_DN0 <CONN>
15
16
14
15 State S0 S3, S4, S5
15 USB20_N0 DM_OUT DM_IN 16
USB20_P0 U2D_DP0
15 USB20_P0
R2600 1 2 0_0402_5%
3

4
DP_OUT DP_IN 10

15 2 1 U2D_DN0
R238
1
@ 0_0402_5%
2 U2D_DN0_C
17
18
17
18 Mode CDP DCP
29 ILIM_SEL ILIM_SEL ILIM1
4 5 16 R2498 2 1 19.1K_0402_1% ACES_85201-1605 4
CTL1 CTL2 CTL3 ILIM_
29 USB_CHARGE_EN EN ILIM0 R2499 @ 19.1K_0402_1% WCM-2012-900T_4P ILIM_
USB_CTL1 R2602 0_0402_5% 1 USB_CTL1_R CTL1 CTL2 CTL3 SEL
2 6 4 3 SEL
29
29
USB_CTL1
USB_CTL2
USB_CTL2
USB_CTL3
R2603
R2601
0_0402_5% 1
0_0402_5% 1
2
2
USB_CTL2_R
USB_CTL3_R
7
8
CTL1
CTL2 GND 14
17
4 3
Control pin
29 USB_CTL3 CTL3
TPS2540RTER_QFN16_3X3
GPAD
1 1 2 2 1 1 1 1 0 0 1 1
L27
U2D_DP0 1 2 U2D_DP0_C
R237 @ 0_0402_5%

PVT:Remove R2664 R2499 R2500 R2501 for DFX issue Follow EMI request add choke
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
11.08
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Con & Daughter Con
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 24 of 47
A B C D E
 5 4 3 2 1

If Sense_A total length is greater than

PLACE CLOSE TO U1 PIN 13 6 inches, chagne C12 to 0.1uF
Notes: MIC_SENSE
RA8 1 2 10K_0402_1% MIC_SENSE 24
Keep PVDD supply and speaker traces routed on the DGND plane.
RA9 1 2 2.49K_0402_1% +AVDD_CODEC
DVDD_IO should match Keep away from AGND and other analog signals
RA7 1 2 20K_0402_1% HP_DET#
with HDA Bus level(optional for 3.3V signaling or 1.5V signaling) RA1 +VDDA_CODEC HP_DET# 24
DVDD_IO FBMA-L11-201209-221LMA30T_0805 SENSE_A CA1 1 2 1000P_0402_50V7K
+3VS
Place AVDD ,PVDD,and DVDD capacitor close to Codec 2 1

RA2 2 1 0_0805_5% +3VS_DVDD +3VS +5VS

D RA3 +AVDD_CODEC SENSE_B RA10 1 2 10K_0402_1% D
+AVDD_CODEC
BLM18BD601SN1D_0603 RA5 2 1 RA6 2 1
1 2 0_0805_5% 0_0805_5%
CA11 2 1000P_0402_50V7K If Sense_B is un-used, then pull high

0.1U_0402_25V6
@ 1
0.1U_0402_25V6

0.1U_0402_25V6
1U_0402_6.3V6K

1U_0402_6.3V6K
2 1 1 1
PVDD PLACE CLOSE TO U1 PIN 14 Sense_B to AVDD by 10Kohm resistor

CA4
1 1 @
CA2 CA5

CA3

CA6

CA7
10U_0603_6.3V UA5
1 2 2 2

10U_0603_6.3V6M
0.1U_0402_25V6

0.1U_0402_25V6
2 2
1 DVDD_CORE AVDD1 27 1 1 1

CA8

CA9
AVDD2 38

CA10
3 DVDD_IO PVDD1 45
2 2 2
PVDD2 39
Follow EMI request, reserve cap.
2 1 CA508 @ 9 13 SENSE_A
Correct CA508 circuitry. (DVDD trough CA508 to GND) 33P_0402_50V8J DVDD SENSE_A SENSE_B
14
12.08 SENSE_B
2 1 CA103 HP0_PORTA_L 28
33P_0402_50V8J 29
HP0_PORTA_R
VREFOUT_A 23
15 HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO 6 MUTE_LED 30
HDA_BITCLK HP_OUT_L
HP1_PORTB_L 31 HP_OUT_L 27
15 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 5 32 HP_OUT_R HP Jack
HDA_SDO HP1_PORTB_R HP_OUT_R 27

1
15 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 10 19 MIC_EXTL
HDA_SYNC PORTC_L MIC_EXTL 28
20 MIC_EXTR Ext MIC R368
PORTC_R MIC_EXTR 28
15 HDA_SDIN0 HDA_SDIN0 2 1 SDIN_CODEC 8 24 VREFOUT_EXT_MIC VREFOUT_EXT_MIC 270_0402_1%
33_0402_5% RA11 HDA_SDI VREFOUT_C/GPIO4
15 HDA_RST_AUDIO# HDA_RST_AUDIO# 11 15
HDA_RST# PORTE_L

2
C 16 C
EAPD EAPD_L PORTE_R
29 EAPD 1 2 2 1 EAPD_AMP 26

3
DH6 DH7 17
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2 PORTF_L
12/8 Add DH7 for sub-woofer EAPD PORTF_R 18
47 QA1B
(pop noise issue when codec into D3) 100_0402_5% RA13 LA19 FBMA-L10-160808-301LMT_2P EAPD SPKL+ MUTE_LED_L
SPK_PORTD_+L 40 SPKL+ 28 5
19 D_MIC_CLK D_MIC_CLK 2 1 D_MIC_CLK_L1 2 D_MIC_CLK_L_C 2 41 SPKL-
DMIC_CLK/GPIO1 SPK_PORTD_-L SPKL- 28
19 D_MIC_DATA D_MIC_DATA 1 2 D_MIC_DATA_C 4 Internal SPKR(front stereo speaker) 2N7002KDW_SOT363-6
DMIC0/GPIO2

4
LA20 FBMA-L10-160808-301LMT_2P 44 SPKR+
SPK_PORTD_+R SPKR+ 28

2
48 43 SPKR-
SPDIFOUT0/GPIO3 SPK_PORTD_-R SPKR- 28
MUTE_LED_L 46 DMIC1/GPIO0/SPDIFOUT1 10K_0402_5%
MONO_OUT 25 SUB_OUT 26 RA18
36 12 MONO_INR 2 1 MONO_IN
CAP+ PCBEEP

1
2 CA96 0.1U_0402_25V6

CA12 21
VREFFILT
4.7U_0603_6.3V6K CAP2 22
1
35 CAP- V- 34
+3VS_DVDD
+3VS_DVDD Place C208 close to Codec VREG(+2.5V) 37

10U_0603_6.3V6M
7

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
DVSS

0.1U_0402_25V6
2 2 1 1
42 PVSS AVSS1 26

CA13

CA14

CA15
AVSS2 30
1

CA16
49 PAD AVSS3 33
RA14 RA17 1 1 2 2
4.7K_0402_5% 10K_0402_5% 92HD91B2X5NLGXYAX8_QFN48_7X7
2

B
Place C209,C210,CA87,CA89 close to Codec B

HDA_RST_AUDIO# EAPD_L

1 1 9/27 LDO TPS793475DBVR for audio power

CA17 CA18 +VDDA_CODEC
0.01U_0402_16V7K 0.1U_0402_25V6
2 2 +5VS UA2
W=40Mil VOUT 5
1 VIN
+AVDD_CODEC 4
BYPASS

0.1U_0402_25V6
1 2 3 EN
RA16 1
1

CA20
10K_0402_5% GND 2 2
RA55
10K_0402_5% TPS793475DBVR_SOT23-5 CA19
Follow EMI request, reserve cap. Need confirmed.
1 2
1
10U_0805_10V6K
CA100
11.03 RA56
2

CA97 0.1U_0402_25V6
BEEP# MONO_IN 2
29 BEEP# 1 2 1 2

0.1U_0402_25V6 100K_0402_5%
CA102 @1 2 0.1U_0402_25V6

CA101 @1 2 0.1U_0402_25V6 D
1

A A
1
CA98 @1 2 0.1U_0402_25V6 15 FCH_SPKR FCH_SPKR 2 UA1 RA54
G 2N7002H_SOT23-3 CA99
CA93@1 2 0.1U_0402_25V6 10K_0402_5%
SB Beep S 0.01U_0402_16V7K
3

2
2

CA92@1 2 0.1U_0402_25V6

RA53 1 2 0_0805_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio IDT 92HD91
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
GND GNDA MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 25 of 47
5 4 3 2 1
 5 4 3 2 1

+5VS +5V_SUBAMP

RA12
BLM18BD601SN1D_0603
1 2
D D

UA3

CA29 1 2 2 1 A1 C3 LA1 1 2 FBM-11-160808-601-T_0603

IN+ OUT+ SUBWOOFER+ 28
0.033U_0603_16V7 RA139 47K_0402_5%

CA27 1 2 2 1 C1
25 SUB_OUT 0.033U_0603_16V7 RA138 47K_0402_5% IN- LA2
OUT- A3 1 2 FBM-11-160808-601-T_0603 SUBWOOFER- 28
B2 PVDD

PGND B3
B1 VDD

1
25 EAPD_AMP C2 EN GND A2 CA30 CA31
680P_0603_50V7K 680P_0603_50V7K

2
TPA2011D1YFFR_DSBGA9

C C
2011.10.28 Change Sub-woofer Amp to TPA2011D1

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Woofer Amplifier
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 26 of 47
5 4 3 2 1
 5 4 3 2 1

Headphone amplifier HP_5V

HP_5V

10K_0402_1%
+5VS
RA38
LA14 1 2
D D
FBM-11-160808-601-T_0603

CA57 1U_0402_6.3V6K UA6

HP_OUT_R1 2 1 2 5 12
25 HP_OUT_R RIGHTINM VDD_12
LA18 0_0603_5% 4 RIGHTINP RA40 30_0603_1%
CA64 1U_0402_6.3V6K 11 1 2 HP_R HP_R 24
HP_OUT_L1 HPRIGHT HP_L
25 HP_OUT_L 2 1 2 1 LEFTINM HPLEFT 14 1 2 HP_L 24
2 2 LA12 0_0603_5% 2 LEFTINP RA39 30_0603_1%
CA65 CA66 3
@ GND_3
1U_0402_6.3V6K 1U_0402_6.3V6K 6 SD# GND_9 9
1 1 EC_SMB_DA2
8,29 EC_SMB_DA2 1 RA19 2 PCH_SMB_DA1_AMP7
SDA GND_10 10
0_0402_5%
GND_13 13 #DB 0930 need apply 30_0603 ohm P/N
@ 19
EC_SMB_CK2 GND_19
8,29 EC_SMB_CK2 1 RA20 2 PCH_SMB_CK1_AMP8
SCL
0_0402_5% 20 15
VDD_20 CPVSS_15
CPVSS_16 16

18 CPP CPN 17

C 21 GND C

CA54

CA94

CA95
0.1U_0402_25V6

1U_0402_6.3V6K
HPA00929

1U_0402_6.3V6K

0.1U_0402_25V6
2.2U_0402_6.3V6M
1 1 1 2 1
CA90 CA80
2 2 2 1 2
CA79 1U_0402_6.3V6K
1 2

Add level shift 11.06

+3VS HP_5V

B B
2

RH126
2.2K_0402_5% RH127
2N7002DWH_SOT363-6 2.2K_0402_5%
2

EC_SMB_CK2 1 6 PCH_SMB_CK1_AMP

QH8A
5

EC_SMB_DA2 4 3 PCH_SMB_DA1_AMP

2N7002DWH_SOT363-6
QH8B
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio SPK/HP Amplifier
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 27 of 47
5 4 3 2 1
 A B C D E

Front Speaker Connector 1

JSPKR1
25
25
SPKR+
SPKR-
SPKR+
SPKR-
1
2
1 Ext. Mic 4.7K_0402_5%
SPKL+ 2
25 SPKL+ 3 3 1 2 VREFOUT_EXT_MIC
1 SPKL- 4 CA55 RA57
25 SPKL- 4 1
1U_0603_25V6 2 1 MIC1_L
25 MIC_EXTL MIC1_L 24
5 GND1 1U_0603_25V6 MIC1_R

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
6 GND2 25 MIC_EXTR 2 1 MIC1_R 24
1 1 1 1 RA58
E&T_3806-F04N-02R CA56 1 2 VREFOUT_EXT_MIC
CONN@ 4.7K_0402_5%

CA44

CA45

CA46

CA47
2 2 2 2 2
<BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure> CA58
1U_0402_6.3V4Z

2
1

1
@ DA1 DA2 @

3.3_0402_5%

3.3_0402_5%

3.3_0402_5%

3.3_0402_5%
RA37

RA41

RA42

RA43
PJDLC05_SOT23-3 PJDLC05_SOT23-3

1
2 2

Need place rear Audio Codec (UA5)

JSW1 CONN@
26 SUBWOOFER+ 1 1
26 SUBWOOFER- 2 2

3 G1
4 G2
E&T_3806K-F02N-03R

Change 4pins to 2 pins

12.13

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/04/07 Deciphered Date 2012/10/21 Title
Audio SPK Conn/Jack/MIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 28 of 47

A B C D E
 5 4 3 2 1

+3VALW_EC +3VALW_EC
+3VALW_EC +3VALW_EC
R98 L9
2

2
+3VALW 0_0805_5% FBMA-L11-160808-800LMT_0603 TP_CLK R102 1 2 4.7K_0402_5%
R154 R125 1 2 +3VALW_EC 1 2 +EC_VCCA
100K_0402_5% 100K_0402_5% 1 1 1 1 2 2 1 TP_DATA R107 1 2 4.7K_0402_5%

0.1U_0402_16V4Z
C100

0.1U_0402_16V4Z
C101

0.1U_0402_16V4Z
C102

0.1U_0402_16V4Z
C103

1000P_0402_50V7K
C104

1000P_0402_50V7K
C105
R99 C106 +3VS
1

ECAGND
0.1U_0402_16V4Z
AD_BID0 AD_PID0 2 2 2 2 1 1 2

0_0402_5%
BKOFF# R109 1 2 10K_0402_5%
1

2
@

1
R155 1 R137 1
0_0402_5% C1365 200K_0402_5% C1364 +3VALW_EC
D @ @ D
0.1U_0402_16V4Z 0.1U_0402_16V4Z R112
2 2
2

1
100K_0402_5%
2 1

111
125
CH751H-40PT_SOD323-2

22
33
96

67
U5

9
EC_ACIN 2 1 ACIN 32,38
D5

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
DB SI PV MV C109 2 1 100P_0402_50V8J
Board ID EC_GA20 1 21 AC_LED#
0 ohm 8.2K ohm 18K ohm 33K ohm 15 EC_GA20 GATEA20/GPIO00 PWM0/GPIO0F AC_LED# 35
R155 15 EC_KBRST#
EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM1/GPIO10 23 BEEP#
BEEP# 25
13,31 SERIRQ SERIRQ 3 PWM Output 26
Project ID 200k ohm 200k ohm 200k ohm 200k ohm LPC_FRAME# 4
SERIRQ# FANPWM0/GPIO12
27 T28
13,21,31 LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13
R137 13,21,31 LPC_AD3
LPC_AD3 5 LPC_AD3/LAD3
LPC_AD2 7 C108 2 1 100P_0402_50V8J ECAGND
13,21,31 LPC_AD2 LPC_AD2/LAD2
LPC_AD1 8 63 BATT_TEMPA BATT_TEMPA 36
13,21,31 LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38
LPC_AD0 10 64
13,21,31 LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39
LPC & MISC ADP_I/AD2/GPI3A 65 ADP_I
ADP_I 36,38
LPC_CLK0_EC 12 66 AD_BID0 USB_ON# R721 1 2 10K_0402_5% +5VALW
13,16,21,31 LPC_CLK0_EC CLK_PCI_EC/PCICLK AD3/GPI3B
10,13,31 PLT_RST# PLT_RST# 13 PCIRST#/GPIO05 AD Input AD4/GPI42 75 AD_PID0
R106 2 1 47K_0402_5% EC_RST# EC_RST# 37 76 R123 1 2 10K_0402_5% +3VALW
+3VALW_EC EC_SCI# EC_RST#/ECRST# AD5/GPI43 @
15 EC_SCI# 20 EC_SCI#/GPIO0E
C107 2 1 0.1U_0402_16V4Z NMI_DBG# 38 ENBKL 100K_0402_5% 2 1 R205
CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPO3C 68
70 EN_DFAN1
EN_DFAN1/DA1/GPO3D EN_DFAN1 30
30 KSI[0..7] DA Output IREF/DA2/GPO3E 71 R191 2 1 0_0402_5% KBL_OFF# KBL_OFF# 30
KSI0 55 72
KSI0/GPIO30 DA3/GPO3F
KSI1
KSI2
56
57
KSI1/GPIO31 Reserve ILIM_SEL 11.03
KSI3 KSI2/GPIO32 TP_ON_OFF_LED#
58 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 83 TP_ON_OFF_LED# 23
C KSI4 USB_ON# C
59 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 84 USB_ON# 24
+3VALW_EC KSI5 60 85 ILIM_SEL
KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C ILIM_SEL 24 +3VALW_EC
10/1 ENE Recommand
KSI6 61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 EAPD EAPD 25
KSI7 TP_CLK
R104 1 2 47K_0402_5% KSO1 30 KSO[0..15]
KSO0
KSO1
62
39
40
KSI7/GPIO37
KSO0/GPIO20
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
87
88 TP_DATA
TP_CLK 30
TP_DATA 30
R144
1 2
0_0402_5%
SPI ROM 256KB
R105 1 2 47K_0402_5% KSO2 KSO2 KSO1/GPIO21 U6
41 KSO2/GPIO22
KSO3 42 97 VGATE 20mils 8 4
R111 1 2 2.2K_0402_5% EC_SMB_DA1 KSO3/GPIO23 SDICS#/GPXIOA00 VGATE 42 VCC VSS
KSO4 43 98 WOL_EN 1
KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 WOL_EN 23
KSO5/GPIO25 Int. K/B
KSO5 44 99 VLDT_EN VLDT_EN 32,41 C110 SPIPIN3 3
R113 1 2 2.2K_0402_5% EC_SMB_CK1 KSO6 ME_EN/SDIMOSI/GPXIOA02 W
45 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 109
KSO7 46 KSO7/GPIO27 SPI Device I/F 2
0.1U_0402_16V4Z 7 HOLD
KSO8 47
KSO9 KSO8/GPIO28 EC_SI_SPI_SO R114 0_0402_5% EC_SI_SPI_SO_R EC_SPICS#/FSEL#_R 1
48 KSO9/GPIO29 SPIDI/MISO 119 1 2 S
KSO10 49 120 EC_SO_SPI_SI 1 R115 2 33_0402_5% EC_SO_SPI_SI_R
KSO11 KSO10/GPIO2A SPIDO/MOSI EC_SPICLK_L EC_SPICLK_L_R EC_SPICLK_L_R
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 1 R116 2 33_0402_5% 6 C
KSO12 51 128 EC_SPICS#/FSEL# 1 R117 2 33_0402_5% EC_SPICS#/FSEL#_R
KSO13 KSO12/GPIO2C SPICS# EC_SO_SPI_SI_R EC_SI_SPI_SO_R
52 KSO13/GPIO2D Delete PX_MODE bcuz PX5.0 is ready. 5 D Q 2
KSO14 53
73 10.20
KSO15 KSO14/GPIO2E R134 1 0_0402_5% ENBKL MX25L2006EM1I-12G SOP 8P
R1100 C221 54 2 ENBKL 10,19
KSO15/GPIO2F GPIO40 @
LPC_CLK0_EC 1 81 KSO16/GPIO48 H_PECI/GPIO41 74
2 1 2 82 KSO17/GPIO49 GPIO FSTCHG/GPIO50 89 SA00002C100 (S IC FL 1MB MX25L1005AMC-12G SOP
90 2 R217 1 0_0402_5%
BATT_CHG_LED#/GPIO52 CAP_LOCK#
BAT_CHG_LED 35 8P 3.3V)
33_0402_5% 22P_0402_50V8J CAPS_LED#/GPIO53 91 CAP_LOCK# 30
EC_SMB_CK1 77 92 KB_BKL_LED# KB_BKL_LED# 30
6/27 add 33 ohm and 22p by EMI request 31,36,38 EC_SMB_CK1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54
31,36,38 EC_SMB_DA1
EC_SMB_DA1 78 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55 93 PWR_LED#
PWR_LED# 23,30
6/27 add 33 ohm and 22p by EMI request
EC_SMB_CK2 79 95 SYSON
8,27 EC_SMB_CK2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 SYSON 17,32,39
EC_SMB_DA2 80 121 VR_ON
8,27 EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 42
127 C114 22P_0402_50V8J
AC_IN/GPIO59
SM Bus EC_SPICLK_L_R 1 2
12/16 remove PU R120 for AMD request 6 SLP_S3# 100 EC_RSMRST# C119 @ 22P_0402_50V8J
B
15 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 15 B
15 SLP_S5# 14 SLP_S5# 101 EC_SPICLK_L_R 1 2 1 2
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 15
15 EC_SMI# 15 EC_SMI# 102 @ R129 33_0402_5%
USB_CTL1 EC_SMI#/GPIO08 EC_ON/GPXIOA05 EC_THERM#
24 USB_CTL1 16 GPIO0A EC_SWI#/GPXIOA06 103 EC_THERM# 8,13,36,42
17 MINI1_LED# 104 0_0402_5% 1 R67 2
+3VALW_EC 21 MINI1_LED# GPIO0B ICH_PWROK/GPXIOA07 FCH_PWRGD 15
24 USB_CTL2 18 USB_CTL2
GPIO0C GPIO BKOFF#/GPXIOA08 105 BKOFF# BKOFF# 19
24 USB_CTL3 19 USB_CTL3
SUS_PWR_DN_ACK/GPIO0D GPO RF_OFF#/GPXIOA09 106 PBTN_OUT# PBTN_OUT# 15
19 EC_INVT_PWM 25 107 USB_CHARGE_EN
INVT_PWM/PWM2/GPIO11 GPXIOA10 USB_CHARGE_EN 24
1

R714 FAN_SPEED1 28 108

10K_0402_5% 30 FAN_SPEED1 EC_PME# FAN_SPEED1/FANFB0/GPIO14 GPXIOA11
23 EC_PME# 29 FANFB1/GPIO15
For PCI SERR 21 E51TXD_P80DATA
E51TXD_P80DATA
E51RXD_P80CLK
30 EC_TX/GPIO16 EC_ACIN R136
21 E51RXD_P80CLK 31 EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 110
D14 32 112 EC_ON 2 1
EC_ON 30 +3VALW_EC
2

NMI_DBG# 1 2 GPIO0 WLAN_OFF_LED ON_OFF/GPIO18 ENBKL/GPXIOD02 ON/OFF# 47K_0402_5%

GPIO0 13 30 WLAN_OFF_LED# 34 SUSP_LED#/GPIO19 EAPD/GPXIOD03 114 ON/OFF# 30
0_0402_5%1 2 R218 36 GPI EC_THERM#/GPXIOD04 115 LID_SW# LID_SW# 30
CH751H-40PT_SOD323-2 30 WLAN_ON_LED# NUM_LED#/GPIO1A
116 SUSP#
SUSP#/GPXIOD05 SUSP# 32
PBTN_OUT#/GPXIOD06 117
EC_PME#/GPXIOD07 118
R124 EC_XCLK1 122
X1 EC_XCLK0 XCLK1 +V18R
13,16 RTC_CLK 1 2 123 XCLK0 V18R 124
EC_XCLK11 2EC_XCLK0 0_0402_5% 1 12/14 PU to +3VALW for EC request
AGND

1 C113
GND
GND
GND
GND
GND
1

32.768KHZ_12.5PF_Q13FC1350000
1 1
@ C111 @ C112 @ C71 R66 4.7U_0603_6.3V6K @
22P_0402_50V8J KB930QF-A1_LQFP128_14X14 2
100K_0402_5% 2 1 +3VALW
2
11
24
35
94
113

69

15P_0402_50V8J 15P_0402_50V8J @ 20mil 2.2K_0402_5% R728

2 2 L10 EC_SMB_CK2 2 1 +3VS
2

ECAGND 2 1 2.2K_0402_5% R729

FBMA-L11-160808-800LMT_0603 EC_SMB_DA2 2 1
2.2K_0402_5% R730
2 @ 1 +3VALW
2.2K_0402_5% R731

A JFW1 A
KSO2 1
KSO3 1
2 2
KSI5 3
KSI4 3 R126 100K_0402_5%
4 4
KSI6 5 1 2 PLT_RST#
KSI7 5
6 6
E51TXD_P80DATA 7
8
7
8
R130 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 VR_ON Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
9
10
GND
GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB930 & 9012
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
ACES_50521-00841-001 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
@ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8041P
Date: Tuesday, December 27, 2011 Sheet 29 of 47
5 4 3 2 1
 +5VS
PV# 9/13 change power rail form +3VALW->+3VALW_EC 29 KSI[0..7]
KSI7
C167 10U_0603_6.3V6M KSO15 C226 100P_0402_50V8J KSI6 ACES_51503-03241-001
+3VLP +3VALW_EC FAN1 Conn 1 2 KSO14
KSO13
C227
C229
1
1
2
2 100P_0402_50V8J
100P_0402_50V8J
KSI5
KSI2
KSI4 KSI1
1 2 32 32
KSO12 C228 1 2 100P_0402_50V8J KSI3 KSI7 31
U11 KSO11 C231 100P_0402_50V8J KSI6 31
1 2 30 30

2
1 8 KSO10 C230 1 2 100P_0402_50V8J KSI1 KSO9 29
EN GND 29

2
@ R131 2 7 KSO9 C233 1 2 100P_0402_50V8J KSI0 KSI4 28 34
R170 100K_0402_5% +VCC_FAN1 VIN GND KSO8 C232 100P_0402_50V8J KSI5 28 GND
3 VOUT GND 6 1 2 29 KSO[0..15] 27 27 GND 33
2 1 4 5 KSO7 C235 1 2 100P_0402_50V8J KSO0 26
29 EN_DFAN1 VSET GND 26
10K_0402_5% R172 300_0402_5% KSO6 C234 1 2 100P_0402_50V8J KSO15 KSI2 25 25

1
1 APL5607KI-TRG_SO8 KSO5 C237 1 2 100P_0402_50V8J KSO14 KSI3 24 24

1
2 ON/OFF# 29 KSO4 C236 1 2 100P_0402_50V8J KSO13 KSO5 23
C168 C169 KSO3 C240 100P_0402_50V8J KSO12 KSO1 23
1 2 22 22
ON/OFFBTN# 1 0.1U_0402_16V4Z 10U_0603_6.3V6M KSO2 C238 1 2 100P_0402_50V8J KSO11 KSI0 21
+3VS 2 KSO1 C241 100P_0402_50V8J KSO10 KSO2 21
1 2 1 2 20 20
2 3 51ON# 51ON# 35 KSO0 C239 1 2 100P_0402_50V8J KSO9 KSO4 19
C170 KSO8 KSO7 19
18 18
C269 D6 1000P_0402_50V7K KSI7 C243 1 2 100P_0402_50V8J KSO7 KSO8 17
CHN202UPT_SC70-3 KSI6 C242 100P_0402_50V8J KSO6 KSO6 17
0.1U_0402_16V7K 1 2 1 2 16 16
1

1
KSI5 C245 1 2 100P_0402_50V8J KSO5 KSO3 15

2N7002KDW_SOT363-6
15

6
R173 KSI4 C244 1 2 100P_0402_50V8J KSO4 KSO12 14
10K_0402_5% KSI3 C248 100P_0402_50V8J KSO3 KSO13 14
1 2 13 13

Q42A
40mil KSI2 C246 1 2 100P_0402_50V8J KSO2 KSO14 12
EC_ON JFAN1 KSI1 C249 100P_0402_50V8J KSO1 KSO11 12
29 EC_ON 2 1 2 11 11

2
+VCC_FAN1 1 KSI0 C250 1 2 100P_0402_50V8J KSO0 KSO10 10
1 10

2
SI# 8/16 Reserve C269 0.1uF by ESD request 29 FAN_SPEED1 2 4 KSO15 9
2 G1 9

1
R132 3 5 WL_WHIT 8
3 G2 WLAN_AMBER 8
1 7 7
10K_0402_5% C171 ACES_85204-03001 6/27 add 33 ohm and 22p by EMI request 25 MUTE_LED 6 6
1000P_0402_50V7K SP02000CU00 +3VS 5 5

1
CONN@ R372 1 2 360_0402_5% 4
2 29 CAP_LOCK# 4
+5VS 3 3
R374 1 2 360_0402_5% 2
+3VALW +5VALW 29 KB_BKL_LED# 2
1 1

11.01 change K/B symbol JKB1 @

R514 U28

37 KBC_HANGUP_RESET# 1 2 N_3_5V_001_R 1 6
RST1# TEST

1
0_0402_5% 2 GND DSR 5
R520
Amber White Keyboard backlight Conn
ON/OFF# 1 2 3 4 1 2 +3VS R367 R371
D60 CH751H-40PT_SOD323-2 SR0# VCC 360_0402_5% 360_0402_5%
0_0402_5% +5VS +5VALW

2
FT7521_MO_252 1 WLAN_AMBER WL_WHIT

2N7002KDW_SOT363-6

2N7002KDW_SOT363-6
6

1
C502
0.1U_0402_16V4Z R80
2

Q48A

Q48B
Q9 100K_0402_5%
2 5 +5VS_KBL
29 WLAN_OFF_LED# WLAN_ON_LED# 29 R369

3
S

2
2 2 1

4
G

3
Add 4S shut-down circuit 10.24 CONN@ JP14 D 1K_0402_5%

1
1

2N7002KDW_SOT363-6
1

0.047U_0402_16V7K

Q42B
2 AO3413L_SOT23-3
2
5 G1 3 3 1 5
6 4 KBL_OFF# 29
G2 4

C68

4
ACES_50504-0040N-001
2

12/8 update JPWR1 symbol

+3VALW_EC +5VALW

1 1 TP/B TO M/B
C47 C48

0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2

JPWR1 @
+5VALW 1
+3VALW_EC 1
2 2

1
29 LID_SW# LID_SW# 3
ON/OFFBTN# 3 D7
4

1
PWR_LED# 4
23,29 PWR_LED# 5 5 G1 7 PESD5V0U2BT
6 6 G2 8 @ 12/8 update JTP1 symbol

3
E-T_6916K-Q06N-00L JTP1CONN@

3
6/27 Add ESD solution 8 G2
7 G1
+3VALW_EC 6 6
TP_CLK 5
29 TP_CLK 5
TP_DATA 4
29 TP_DATA 4
FCH_SCLK1_R 3
FCH_SDATA1_R 3
1 2 2
1 1 1

C116
ACES_50578-0060N-001
2

C117
2
100P_0402_50V8J

100P_0402_50V8J
H11 H13 H18 H19 H24 9/23 change conn to SP010012G00
H_3P3 H_2P8 H_3P3 H_3P3 H_4P4 SI# 7/29 remove the TP colay circuit R214, R215
HOLEA HOLEA HOLEA HOLEA HOLEA 15 FCH_SCLK1 R190 2 1 0_0402_5% FCH_SCLK1_R
15 FCH_SDATA1 R210 2 1 0_0402_5% FCH_SDATA1_R

@ @ @ @ @
1

1
H22 H27 H26 H25 H29 H30
H_3P1X2P8 H_2P8 H_3P1X2P8 H_3P3 H_3P3 H_3P3

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

@ @ @ @ @ @
PCB
1

1
ZZZ1

H32 H31 H33

H_3P3 H_3P3 H_3P3 H34 H35
H_2P1N H_2P8
HOLEA HOLEA HOLEA
HOLEA HOLEA LA-8731P
@ @ @ DA60000TF00
1

@ @
1

FD1 FD2 FD3 FD4

@ @ @ @

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWRBTN/KB/TP/LED/FAN/Screw
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 30 of 47

 ACCELEROMETER Address: 0x50/0x52
+3VALW_EC
+3VALW_EC

2
R171
U25 10K_0402_5%
1 9 +3VALW_EC
Vdd_IO INT2

1
INT1 11 ACCEL_INT# 13
EC_SMB_CK1 4 14
29,36,38 EC_SMB_CK1 SCL/SPC VDD
EC_SMB_DA1 6
29,36,38 EC_SMB_DA1 SDA/SDI/SDO
7 SDO/SA0 GND 5
+3VALW_EC 2 1 8 CS GND 12
R166 10K_0402_5% 10
RES
RES 13 1 1
1

2 15 C218
R167 NC RES C219
3 NC RES 16
0_0402_5% 0.1U_0402_16V7K 10U_0603_6.3V6M
2 2
HP3DC2
2
1

R168
0_0402_5%
@
2

TPM1.2
+3VS +3VALW
+3VS

1
R509 R510
R508 9656@ 0_0402_5% 0_0402_5%

1
0_0402_5% 9656@ 9635@
0.1U_0402_16V4Z

2
1 1 1
C1053 C1054 C1055
1

2
0.1U_0402_16V4Z C124 +3VS
2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z

24
19
10
2

1
U69
R503

VSB
VDD
VDD
VDD
4.7K_0402_5%
9635@
LPC_AD0 26 28 LPC_PD#_TPM
13,21,29 LPC_AD0 LAD0 LPCPD#

2
LPC_AD1 23 9 BADD
13,21,29 LPC_AD1 LAD1 TESTB1/BADD
LPC_AD2 20 8
13,21,29 LPC_AD2 LAD2 TEST1

1
LPC_AD3 17 R504
13,21,29 LPC_AD3 LAD3
14 TPM_XTALO
XTALO

1
13 TPM_XTALI R502 @
TPM XTALI 4.7K_0402_5%
LPC_CLK0_EC 21 SLB 9635 TT 1.1 9635@
13,16,21,29 LPC_CLK0_EC LCLK

2
LPC_FRAME# 22 2 T44 4.7K_0402_5%
13,21,29 LPC_FRAME# LFRAME# GPIO2
PLT_RST# 16 6 T45
10,13,29 PLT_RST# LRESET# GPIO

2
SERIRQ 27
13,29 SERIRQ SERIRQ
PM_CLKRUN# 15
13 PM_CLKRUN# CLKRUN#
+3VS 1 2 7 PP NC 1
1
R1380 3
R507 @ 4.7K_0402_5% NC
12

GND
GND
GND
GND
NC

1
0_0402_5%
9635@ R1409
SLB9635TT_TSSOP28
2

4
11
18
25
0_0402_5%

2
+3VS
9635@ 18P_0402_50V8J
TPM_XTALI C1057 1 2
1

Y8

1
R506 9635@
4.7K_0402_5% R1381 4 3
9635@ 9635@ OSC NC
10M_0402_5% 1 2
OSC NC
2

2
LPC_PD#_TPM R505 2 1 0_0402_5% SUS_STAT#
SUS_STAT# 15 32.768K 12.5PF Q13MC1462001700
TPM_XTALO C1056 1 2
9635@ 18P_0402_50V8J
9656@
PLT_RST# R511 2 1 0_0402_5% BADD

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TPM/Gsensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
LA-8731P 0.1

Date: Tuesday, December 27, 2011 Sheet 31 of 47

 A B C D E

+5VALW TO +5VS +1.1VALW TO +1.1VS (1.1A)

+5VALW
7/12 SI Change to PAK type
SI7326DN-T1-E3_PAK1212-8 +5VS
U12
1 +1.1VALW +1.1VS
U39

10U_0603_6.3V6M
2

2
10U_0603_6.3V6M AO4430L_SO8

10U_0603_6.3V6M
5 3 1 1
R176

C172

1U_0603_25V6
C173
1 1 8 1
470_0603_5%
C174

C175

10U_0603_6.3V6M
C1447

1U_0402_6.3V6K
C1449
7 2

2
10U_0603_6.3V6M
C1448
6 3 1 1
2 2

1
1 @ 1
1 5
2 2

1
R1102 R1101
1K_0402_5% 470_0603_5%
2 2

4
6
2

3 1
2
20mil 10mil 5VS_GATE SUSP
+VSB 2 1 2
R180
20K_0402_5% 1 Q14A 5 VLDT_EN#

1
3

C179 DMN66D0LDW-7_SOT363-6 20mil +VSB 1 2 1.1VS_GATE

0.1U_0603_25V7K R1105 Q54B

4
6
47K_0402_5% DMN66D0LDW-7_SOT363-6
SUSP 2

300K_0402_5%
R1106
5 1

1
Q14B VLDT_EN# 2 C1451
4

DMN66D0LDW-7_SOT363-6 Q54A .1U_0603_25V7K

DMN66D0LDW-7_SOT363-6 2

2
D

1
29,38 ACIN ACIN 2 U15
G 2N7002H_SOT23-3
S

3
+3VALW TO +3VS
+3VALW +3VS
2 SI7326DN-T1-E3_PAK1212-8 2
U18
1
2 +1.5VTO +1.5V_PCIE
2
10U_0603_6.3V6M
C181

10U_0603_6.3V6M
C182

1 1 5 3 1 1
R186
10U_0603_6.3V6M
C183

1U_0603_25V6
C184

470_0603_5%
2 2 2 2
4

+1.5V_PCIE

R188 10mil +3VALW +1.5V

1
20mil 47K_0402_5%
6

+VSB 2 1 3VS_GATE W=60mils

R64
1 100_0603_5%
3

1
C191 2 SUSP 1

2
0.1U_0603_25V7K R68 C72
Q20A 100K_0402_5%
2
1

SUSP 5 DMN66D0LDW-7_SOT363-6 4.7U_0603_6.3V6K

2

2
Q20B R65
4

3
DMN66D0LDW-7_SOT363-6 200K_0402_5%
2 2 1 2
G SI2305CDS-T1-GE3_SOT23-3
Q11A
DMN66D0LDW-7_SOT363-6 1

1
C69
0.047U_0402_16V7K Q12 D +1.5V_PCIE

1
2
W=60mils

3
3
6/24 Q20 and Q21 to Q20 change to Dule mos package 1 1
3
C70
SUSP 5 0.1U_0402_16V4Z
4.7U_0603_6.3V6K C73
Q11B 2 2

4
DMN66D0LDW-7_SOT363-6

+0.75VS
+2.5VS +1.2VS +1.5V
+5VALW +5VALW +5VALW

2
R182
2

2
22_0603_5% R183 R184 R185
R1097 R174 R175 470_0603_5% 470_0603_5% 470_0603_5%
100K_0402_5% 100K_0402_5% 100K_0402_5%

3 1

6 1

3 1
1

6 1

6
VLDT_EN# SYSON# SUSP
39 SUSP
D
1

29,41 VLDT_EN 2 U16 2 SUSP 5 SUSP 2 SUSP 5 SYSON#

G 2N7002H_SOT23-3 SYSON 2 DMN66D0LDW-7_SOT363-6
17,29,39 SYSON
1

S Q15A Q15B Q17A Q17B

3

4
1

Q19A 5 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6

29 SUSP#
1

R1103 R177
1

10K_0402_5% 100K_0402_5% Q19B

4

R178
2

10K_0402_5%
2

4 4
2

C267 @
SYSON 1 2
100P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8041P
Date: Tuesday, December 27, 2011 Sheet 32 of 47
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Strap pin table
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8731P
Date: Tuesday, December 27, 2011 Sheet 33 of 47
5 4 3 2 1
 5 4 3 2 1

Boot Enter S3 S3 Resume Shut Down

ACIN

AC Plug
+5VALW

+3VALW

SPOK
(+3VALW/+5VALW PWRGD) SPOK enable +1.1VALW
D D

+1.1VALW

EC_RSMRST#
(FCH to EC)

ON/OFF

PBTN_OUT#
(EC to FCH)

SLP_S5#

SLP_S3#
(FCH to EC)
125.6mS 165mS
SYSON
620uS
+1.5V
52.6mS 116.8mS 50.43mS 52.57mS
SUSP#
3.79mS
+5VS
5.95mS
+3VS LDO to +2.5VS

5.07mS
C
+2.5VS C

4.88mS
+1.5V_PCIE
(+1.5VS)

+0.75VS
83.4mS 84.2mS 85mS 84mS
VR_ON
8.62mS
+CPU_CORE

+CPU_CORE_NB

VGATE
31mS
VLDT_EN 31.6mS
1.08mS
+1.2VS

+1.1VS

FCH_PWRGD 62.83mS 94.17mS 63.63mS 94.37mS

(EC to FCH)

APU_PWRGD 108.4mS 22.43mS 98.77mS 22.3mS

(FCH to APU)

PLT_RST# 3.4mS 2.6mS

(FCH to devices)
B B

APU_PCIE_RST#
(FCH to PCIe device)

APU_RST# 2.2mS 1.8mS

(FCH to APU)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/08 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-8731P 0.2

Date: Tuesday, December 27, 2011 Sheet 34 of 56

5 4 3 2 1
 5 4 3 2 1

D D

ADPIN PL1 VIN

HCB2012KF-121T50_0805
1 2

PJP1 @ 1 2

100P_0402_50V8J

1000P_0402_50V7K
100P_0402_50V8J
1 1 2 2 PL2

1
HCB2012KF-121T50_0805

1
Charge_LED 3 4 ACIN_LED PR1 @

PC1

PC3
3 4

PC4
PC2 1K_0402_5%
ADPIN 5 6 ADPIN 1000P_0402_50V7K
5 6

2
ACES_59012-06001-002
3

3
PD1
C PD4 PJSOT24CW_SOT323 C
1

PJSOT24CW_SOT323

1
ESD diode : SCA00001G00 +3VALW

3
+3VLP +3VALW

2
29 AC_LED#

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
1

1
VIN 37.1
TP0610K-T1-GE3 1P SOT23-3

PR26

PR27

PR28

PR29
PQ5
2
PD2 @

2
LL4148_LL34-2 @ @
1

5
PR25
2K_0402_5% 1 AC_LED#

P
ACIN_LED 1 B
2 4 O
1

1 A 2 BAT_CHG_LED

G
B PR2 @ PR3 @ B
68_1206_5% 68_1206_5% VS PU2
PQ1

3
74LVC1G02GW_SOT353-5
PD3 TP0610K-T1-GE3 1P SOT23-3
2

LL4148_LL34-2
BATT+ 2 1 3 1
0.22U_0603_25V7K
100K_0402_5%
1

PC6@
PR4

PC5

5
0.1U_0603_25V7K
2 AC_LED#

P
A
2

PR5 Charge_LED 4 Y
2

22K_0402_1% 1
B BAT_CHG_LED 29

G
30 51ON# 1 2
PU3

3
74LVC1G86GW_SOT353-5

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/03 Deciphered Date 2014/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8712P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 35 of 46
5 4 3 2 1
 5 4 3 2 1

D
For KB930 ‐‐> Keep PU1 circuit D

(Vth = 0.825V)

Part Number = SP02000I400 BATT++ BATT+

PH1 under CPU botten side :
ACES_88107-12001-H01-CP
PJPB1 @ GND 14
PL3 CPU thermal protection at 90 +‐3 degree C
SMB3025500YA_2P
GND 13 BATT++ BATT+ Recovery at 56 +‐3 degree C
2 1

12 12

1
11 PC7 PC8
11
10 10 1000P_0402_50V7K 0.01U_0402_25V7K Rset = 3 * Rtmh
9 9
Rhyst = (Rset* Rtml) / (3*Rtml ‐ Rset)

2
8 8
7 7
6
6
5 5 Rtmh at 90C = 7.8K, Rtml at 56C = 26.1K
4
C 4
3 3 Rset = 3 * 7.8K = 23.4K  ==> 23.7K C
2 PR8
2
1 1 100_0402_5% Rhyst = (23.4K * 26.1K) / (3 * 26.1K ‐ 23.4K) = 11.12K ==> 11.3K
1 2 EC_SMB_DA1 29,31,38
PR9
100_0402_5%
1 2 EC_SMB_CK1 29,31,38 +3VLP

1
PR10
6.49K_0402_1%
PR12

1
1 2 +3VALW
PC10 23.7K_0402_1%
Place clsoe to EC pin .1U_0402_16V7K

2
PR11
1K_0402_5%

2
1 2
BATT_TEMPA 29
PR13
11.3K_0402_1%

1
PU1
1 VCC TMSNS1 8

1
PH1
2 7 100K_0402_1%_NCP15WF104F03RC
GND RHYST1

2
MAINPWON 3 6
8,37 MAINPWON OT1 TMSNS2
+3VS 4 5 2 1 2 1
OT2 RHYST2 ADP_I 29,38
G718TM1U_SOT23-8 PR14 PR15
6.34K_0402_1% 1.8K_0402_1%

2
1
PR16 PR17
B 100K_0402_1% 10K_0402_1% B

1
PQ2 8 H_PROCHOT#

2
TP0610K-T1-GE3 1P SOT23-3
D

1
B+ 3 1 +VSB 2 1 2 EC_THERM# 8,13,29,42
G
PR18 @
0.22U_1206_25V7K
100K_0402_1%

S SSM3K7002FU_SC70-3 0_0402_5%
Active point = 71.52W

3
1

@ PQ3
1

1
PR19

PC11

+5VALW PC12 @
0.1U_0603_25V7K
Recovery point = 62.62W
2

2
2

PR21
2

PR20 22K_0402_1%
100K_0402_1% 1 2

PR22
D
1

0_0402_5%
1 2 2 PQ4
37,40 SPOK
G SSM3K7002FU_SC70-3
S
3
1

PC13 @
.1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/03 Deciphered Date 2014/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA8712P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 36 of 46
5 4 3 2 1
 A B C D E

2VREF_8205

1U_0603_16V6K
1

PC302
2
1 1

VL

PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
20K_0402_1% 20K_0402_1% B++
1 2 1 2
B+ B++ For RF request
For RF request
PL301 +3VLP

ENTRIP2

ENTRIP1
PR306

2200P_0402_50V7K
HCB2012KF-121T50_0805 PR305

10U_0805_25V6K

10U_0805_25V6K

68P_0402_50V8J
FB_3V

FB_5V

0.1U_0402_25V6
1 2 113K_0402_1% 57.6K_0402_1%

1
PC303

PC304

PC322
1 2 1 2
2200P_0402_50V7K

10U_0805_25V6K

68P_0402_50V8J

PC305

PC306
0.1U_0402_25V6

10U_0805_6.3V6M

2
1

1
PU301
PC301

PC307

PC321

5
PC308

PC309

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
5
PQ302
2

PQ301 25 AON7408L_DFN8-5
P PAD

2
AON7408L_DFN8-5
36,40 SPOK
7 VO2 VO1 24 4
4
2 PC311 2
8 VREG3 PGOOD 23
PC310 PR307 PR308 0.22U_0603_16V7K
1 2BST1_3V 1 2BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2BST1_5V1 2

3
2
1
0_0402_5% 0_0402_5%
1
2
PL302 3 0.22U_0603_16V7K UG_3V 10 UGATE2 UGATE1 21 UG_5V PL352
4.7UH_ETQP3W4R7WFN_5.5A_20% 1UH_VMPI0703AR-1R0M-Z01_11A_20%

+3VALWP 2 1 LX_3V 11 PHASE2 PHASE1 20 LX_5V 2 1

+5VALWP
1

5
4.7_1206_5%

LG_3V 12 19 LG_5V
LGATE2 LGATE1
5

4.7_1206_5%
PQ304
PR309

SKIPSEL
PQ303 PD302 PR311 TPCA8057-H_PPAK56-8-5

150U_UD_6.3VM_R15M
PR310
1

VREG5
RLZ5.1B_LL34 499K_0402_1% 1
B+

GND
+ PC312 RT8205LZQW(2) WQFN 24P PWM

VIN
1 2 1 2

NC
EN
2
1SNUB_3V

150U_B2_6.3VM_R35M +

PC313
4

1SNUB_5V 2
4 PR312 @
Ipeak=5A 2

13

14

15

16

17

18
680P_0603_50V7K

0_0402_5%
MAINPWON 2
1 2

680P_0603_50V7K
Imax=3.5A
PC314

3
2
1
MDV2658BURH_POWERDFN33-8-5

1U_0603_10V6K
200K_0402_1%
1
2
3

1
F=500K

PC316
2

PC315
B++ VL

PR313

0.1U_0603_25V7K
Rtrip=113K, OCP=6.92A

2
2

PC318
Total Capacitor 150uF,

1
PC317
4.7U_0805_10V6K

2
Ipeak=10A
ENTRIP1

ENTRIP2

2VREF_8205 Imax=7.5A
3 3
F=400K
6

PJP303
2 1
PQ305A PQ305B 2 1 Rtrip=57.6K, OCP=16.39A
SSM6N7002FU-2N_SOT363-6 2 N_3_5V_001 5 SSM6N7002FU-2N_SOT363-6 @ JUMP_43X118

PJP304
Total Capacitor 150uF,
1

+5VALWP 2 2 1 1
+5VALW ( UMA 10A,400mils ,Via NO.= 20 )
@ JUMP_43X118

1 2
VL
PR315 PR314
0_0402_5% 100K_0402_5%
1 2
30 KBC_HANGUP_RESET#
PJP301
2 1
PR316
0_0402_5%
+3VALWP 2 1
@ JUMP_43X118
+3VALW ( 5A,200mils ,Via NO.= 10 )
MAINPWON 1 2
8,36 MAINPWON
1

PD301 PR317
LL4148_LL34-2 1M_0402_1% PQ306
2 1 1 2 2 LTC015EUBFS8TL NPN UMT3F
VIN
4.7U_0603_6.3V6K
402K_0402_1%
1

4 4
PC319
PR318

PR319
100K_0402_1%
2

2 1 @
VS
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/10/03 Deciphered Date 2014/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA8712 0.1
For KB930 ‐‐> Keep PD301, PR317, PR319 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 37 of 46
A B C D E
 A B C D

for reverse input protection

PQ101 D

1
2
G
2N7002KW_SOT323-3
S

3
1 1

1 2 1 2
@ PJ101
PR101 PR102
1M_0402_5% 3M_0402_5% 2 2 1 1
B+ JUMP_43X79
VIN P1 PQ103
P2
PR103 PL101
PQ102 AON7702L_DFN8-5 PQ104
0.01_1206_1%
AO4474L_SO8 1.2UH +-30% 1231AS-H-1R2N=P3 2.9A AON7702L_DFN8-5
8 1 1 1 4 1 2 1
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K

68P_0402_50V8J
7 2 2 2

2200P_0402_50V7K
10U_0805_25V6K

0.1U_0402_25V6
10U_0805_25V6K
6 3 3 5 2 3 5 3
@

0.1U_0402_25V6

1
VIN

PC105

PC218
5

PC108
PC106
@

0.01U_0402_50V7K
1

1
@
0_0402_5%

PC107
1

1
PC103

PC104
PC102

0_0402_5%
4

4
1

PR104
PC101

PC110
2

PR105
2 PC109
0.1U_0402_25V6
2

1 2 @

2
3

2
PD101
BQ24725_BATDRV 1

0.1U_0603_25V7K

0.1U_0603_25V7K
BAS40CW_SOT323-3 2

1
PC111

PC112
PR106
4.12K_0603_1%
PC113 0.047U_0402_25V7K

1
4.12K_0603_1%

4.12K_0603_1%

2
1

1 2
PR108
PR107

5
10_1206_1%
1
PQ105

PR109

2
AON7408L_DFN8-5
2

2
PR110 2

BQ24725_ACP
0_0603_5%

BQ24725_ACN
PR111

1
DH_CHG 1 2 4

BQ24725_BST
PD102 BATT+

BQ24725_LX
0_0402_5%

1
1 2 RB751V-40_SOD323-2

DH_CHG
PL102
2011/03/18 PC114 PC115 4.7UH_ETQP3W4R7WFN_5.5A_20% PR112

3
2
1
1U_0603_25V6K 1 2 0.01_1206_1%
delete VIN voltage BQ24725_LX 1 2 CHG 1 4
1U_0603_25V6K
detecting circuit

4.7_1206_5%
5

1
2 3

20

19

18

17

16
PU101 PQ106

PR113

1 CSOP1

1 CSON1
BTST
VCC

PHASE

HIDRV

REGN

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.01U_0402_50V7K

68P_0402_50V8J
21

AON7408L_DFN8-5

0.1U_0402_25V6
PAD

0.1U_0402_25V6

PC118

PC119
2

1
PC121
DL_CHG

PC116

PC117

PC127
PC122
1 ACN LODRV 15 4

680P_0603_50V7K

2
PC120
2 ACP GND 14
PR114

3
2
1

2
BQ24738ARGRR QFN 20P CHARGER 0_0603_5%
BQ24725_CMSRC 3 13 SRP 1 2 CSOP1
CMSRC SRP

1
BQ24725_ACDRV 4 12 SRN 1 2 CSON1
ACDRV SRN

2
@PR116
@ PR116 PR115
10K_0402_1% 0_0603_5% PC123
BQ24725_BATDRV 0.1U_0603_25V7K
1 2 5 11
+3VALW PR117 ACOK ACDET BATDRV
10K_0402_1%
IOUT

SDA

ILIM
SCL
1 2
3
+3VLP +3VALW 3
6

10
29,32 ACIN 1 2
PR118
0_0402_5% 1 2
PR119
0_0402_5%

0.01U_0402_25V7K
280K_0402_1%

100K_0402_1%
1

1
PR120

PC124
0_0402_5%
2

VIN
2
330K_0402_1%

2
PR123
1
PR124

1
PR122
2

0_0402_5%
2
0.047U_0402_16V

53.6K_0402_1%

EC_SMB_CK1 29,31,36
1

1
PC125

PR126
2

1
PR125

EC_SMB_DA1 29,31,36
2

PC126
2 1 ADP_I 29,36
Vin Dectector 100P_0402_50V8J
4

Min. Typ Max. 4

H-->L 17.33V
L-->H 16.98V

ILIM and external DPM Security Classification Compal Secret Data Compal Electronics, Inc.
4.36A Issued Date 2011/10/03 Deciphered Date 2014/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- CHARGER
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8712P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 38 of 46
A B C D
 5 4 3 2 1

2
D PC403 D
680P_0603_50V7K

1
PR403

2
PC402 4.7_0805_5%
22U_0805_6.3V6M SY8809DFC_DFN8_2X2
4 5 PL402
GND GND

2
PL401 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
3 6 LX_1.5VP 1 2
LX LX
+1.5VP

1
HCB1608KF-121T30_0603
1 2 IN_1.5VP 2 7
+5VALW IN PG

22U_0805_6.3V6M

22U_0805_6.3V6M
EN_1.5VP 1 FB_1.5VP

22U_0805_6.3V6M
EN FB 8

1
PC404

PC405

PC406
PU401

2
@
PR401
1 2
17,29,32 SYSON

1
0_0402_5%

0.1U_0402_10V7K
47K_0402_5%

PC401
1
PR402
@

2
C @ C

22P_0402_50V8J
150K_0402_1%
2

1
PR405

PC407

2
1 2
PR406
100K_0402_1%

1
+1.5V APL5336 HF
SA00002XR10
PU402 PJP402 PJP401
B
1 VIN VCNTL 6
+3VALW +0.75VSP 2 2 1 1
+0.75VS +1.5VP 2 2 1 1
+1.5V B

2 5 @ JUMP_43X39 @ JUMP_43X118
GND NC
1

PC422
1

4.7U_0805_6.3V6K 3 VREF NC 7

1
PR422
2

4 8 PC423
1K_0402_1% VOUT NC 1U_0603_10V6K +1.5V
2

TP 9
+0.75VSP Ipeak=8A
2

APL5336KAI-TRL SOP
VREF_APL5336 TDC=1.4A Imax=6A
PC424 Peak Current=2A Total Capacitor 1050uF,
SSM3K7002FU_SC70-3

+0.75VSP ESR 4.43mohm
1

.1U_0402_16V7K

PR421
D
1

0_0402_5%
PR423
PQ402

2 1 0.75VS_N_002 2
32 SUSP 1K_0402_1%
G PC425 HW side:
2
1

PC421 @ S 10U_0805_6.3V6M
C106 330uF 17m
3

0.1U_0402_10V7K
C218 390uF 10m
2

VGA@ CV122 390uF  10m
@ C189 330uF 15m

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/10/03 Deciphered Date 2014/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 1.5VP/0.75VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-8551P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 39 of 46
5 4 3 2 1
 5 4 3 2 1

D D

1.1valwp
Peak Current 4A
PC802
SY8809DFC_DFN8_2X2
current limited 6A

1
22U_0805_6.3V6M 4 5 PL802
GND GND 1UH_PCMB042T-1R0MS_4.5A_20%
PL801

2
3 6 LX_+1.1V 1 2
+5VALW HCB1608KF-121T30_0603 LX LX +1.1VALWP
1 2 1.1V_IN 2 7
IN PG

4.7_0805_5%
1 8 FB_+1.1V
EN FB

PR802
PU801

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
PC803

PC804

PC805
PR801

2
1 2EN_1.1V

SNUB_+1.1V
36,37 SPOK
@

1
0_0402_5%

0.1U_0402_10V7K
C C

47K_0402_5%

PC807
PR804

1
PR803

2 1
@
2

@ 2 8.45K_0402_1%

680P_0603_50V7K
PC809
PC808

2
1
2 1

PR805
22P_0402_50V8J

+1.1VALWP
10K_0402_1%

2
@ PJP801
+1.1VALWP 2 2 1 1 +1.1VALW
JUMP_43X39 (4A,240mils ,Via NO.= 8)

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/29 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8712P 0.01
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 40 of 46
5 4 3 2 1
 5 4 3 2 1

PL701
HCB1608KF-121T30_0603
+1.2VSP_B+ 2 1
B+

2200P_0402_50V7K

68P_0402_50V8J
10U_0805_25V6K
0.1U_0402_25V6
1

1
PC703

PC705
PC702

PC704
2

2
5
D PQ701 D

PR702
PC706
2.2_0603_5% 4
1 2 1 2
PU701 0.1U_0603_25V7K
1 10 BST_+1.2VSP PR711 SIS412DN-T1-GE3_POWERPAK8-5
PGOOD BOOT

3
2
1
PR703 0_0402_5%
1 2 TRIP_+1.2VSP 2 CS UGATE 9 UG_+1.2VSP 1 2 PL702
88.7K_0402_1% 1UH_VMPI0703AR-1R0M-Z01_11A_20%
PR701 EN_+1.2VSP 3 8 SW_+1.2VSP 1 2
29,32 VLDT_EN
0_0402_5% EN PHASE
+1.2VSP
1 2 FB_+1.2VSP 4 7 +1.2VSP_5V
FB VCC
+5VALW
2

RF_+1.2VSP LG_+1.2VSP
47K_0402_1%

0.1U_0402_16V7K

5 RF LGATE 6
1

1
PQ702
PR710

1
11
@ PC701

330U_D2_2.5VY_R15M
TP PC707 PR704 +

PC708
FDMC7692S_MLP8-5
2

1
RT8237EZQW(2)_WDFN10_3X3 1U_0603_6.3V6M 4.7_1206_5%
1

2
2

2
@ PR705 4
470K_0402_1% Ipeak=8.5A

1
PC709
Imax=5.95A
2

1000P_0603_50V7K

3
2
1

2
F=290K
C @ @ C
PC710 PR706
2 1 2 1
PJP701 +1.2VS
PR707 1000P_0402_50V7K 1.2K_0402_1% +1.2VSP 2 2 1 1
7.15K_0402_1% @ JUMP_43X118
2 1
(8.5A,340mils ,Via NO.=17)

+1.2VSP
Iocp=13A
2

PR708
10K_0402_1%
1

B B

PU702
APL5508-25DC-TRL_SOT89-3
+3VS PJP702
2 IN OUT 3 +2.5VSP
+2.5VSP 2 1 +2.5VS
2 1
GND

1
@ JUMP_43X39

4.7U_0805_6.3V6K
1

1
@ PR709 (0.75A,40mils ,Via NO.=22)

PC712
PC711 1 10K_1206_5%
1U_0603_10V6K
2

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/29 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.2VSP/+2.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8712P 0.01
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 41 of 46
5 4 3 2 1
 5 4 3 2 1

PC2011 PR2001
330P_0402_50V7K 2K_0402_1%
2 1 2 1
8 APU_VDDNB_SEN PC2012
PR2002 PR2003 @ PR2004
2.8K_0402_1% 137K_0402_1%390P_0402_50V7K 32.4K_0402_1%
2 1 2 1 2 1 2 1
PL2002
CPU_B+
PR2005 PR2006 PC2013 PR2007 PC2014 HCB2012KF-121T50_0805
10_0402_5% 0_0402_5% 1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J 1 2 B+
D D

2200P_0402_50V7K
PL2005

10U_0805_25V6K

10U_0805_25V6K
+APU_CORE_NB 2 1 2 1 2 1 2 1 2 1
HCB2012KF-121T50_0805

68P_0402_50V8J
33U_D_25VM_R60M

33U_D_25VM_R60M
1 1

0.1U_0402_25V6
5
PC2019 1 2

1
VSUMP_NB 1000P_0402_50V7K + +

PC2018
PC2017

PC2020

PC2057

PC2058

PC2015
1
2.61K_0402_1%

PC2016
10K_0402_5%_ERTJ0ER103J
1

2 1

2
2 2

2
PQ2001
PR2008

2
@ UGATE_NB1 AON7518 1N DFN
0.047U_0402_16V7-K

0.1U_0402_25V6
4
2

11K_0402_1%

2
PR2009
12
PH2001

PC2021

PC2022

PL2001
1

3
2
1
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1

PR2010
634_0402_1% PHASE_NB1 1 4
+APU_CORE_NB
2

VSUMN_NB 2 1 FCCM_NB

1
PC2025 2 3
1

1
@ PC2024

0_0603_5%
@ PR2012 PR20130.22U_0603_25V7K

@ PR2011
PC2023 100_0402_1% 220P_0402_50V7K BOOT_NB1 2 1 2 1 PQ2002 PR2014 PR2015
0.1U_0603_50V7K 2 1 2 1 LGATE_NB1 4.7_1206_5% 3.65K_0402_1%
2

PR2061 0_0603_5% VSUMP_NB 2 1

2
2 1 PHASE_NB1

1 2
10K_0402_1% LGATE_NB1 4 PR2018
UGATE_NB1
After rev1.1 must change to 133k
PC2026
680P_0603_50V7K
1_0402_1%
VSUMN_NB 2 1
APU_CORE_NB
TDC 25A

2
48

47

46

45

44

43

42

41

40

39

38

37
MDU1511RH_POWERDFN56-8-5
Peak Current 33A

3
2
1
2

PU2000
2

PR2016
OCP current 40A

ISUMP_NB

PHASEX

UGATEX
ISEN1_NB

ISUMN_NB

VSEN_NB

FB_NB

PGOOD_NB
COMP_NB

FCCM_NB

PWM2_NB

LGATEX
133K_0402_1% PC2027 PR2019
1000P_0402_25V6K 10_0402_5% CPU_B+
Load line -4mV/A
1

+5VS 2 1 1 36 BOOT_NB1
ISEN2_NB BOOTX
1

PR2017 27.4K_0402_1%
2 1 2 35 2
PR2020
1
FSW=300kHz
NTC_NB VIN
PH2000 BOOT2 0_0603_5%
DCR 1.1mohm +/-5%
3 34
IMON_NB BOOT2
TYP MAX

1
470K_0402_5%_TSM0B474J4702RE PR20000_0402_5%
C 2 1 2 1 SVC 4 33 UGATE2 PC2028 C
8,13,29,36 EC_THERM# 8 APU_SVC
PR20210_0402_5% SVC UGATE2
0.22U_0603_25V7K CPU_B+ H/S Rds(on) :11.7mohm , 14.5mohm

2
PHASE2
2 1 5 VR_HOT_L PHASE2 32
L/S Rds(on) :2.6mohm , 3.2mohm
1

PR20230_0402_5%
+5VS

2200P_0402_50V7K
PR2022 SVD LGATE2

10U_0805_25V6K

10U_0805_25V6K

0.01U_0402_25V7K
8 APU_SVD 2 1 6 SVD LGATE2 31
10.5K_0402_1% PR20240_0402_5% ISL6277HRTZ-T_TQFN48_6X6
+1.5VP 2 1 VDDIO 7 30
PR20250_0402_5% VDDIO VDDP PR2026
2

1
1 SVT

PC2029

PC2031

PC2030

PC2032
8 APU_SVT 2 8 SVT VDD 29 2 1

5
PR20280_0402_5% 1_0603_5%

1U_0603_16V6K
29 VR_ON 2 1 ENABLE 9 ENABLE PWM_Y 28

2
1

1
After rev1.1 must change to 133k PR20270_0402_5%

1U_0603_16V6K
PR2029 1 PWROK 10 LGATE1

PC2034
8,13 APU_PWRGD 2 PWROK LGATE1 27
133K_0402_1% PQ2003

PC2033
2

2
1 2 11 26 PHASE1 UGATE1 4 AON7518 1N DFN
IMON PHASE1
PC2035 12 25 UGATE1
1000P_0402_25V6K NTC UGATE1

PGOOD

BOOT1
ISUMN
ISUMP

COMP +3VS
ISEN3

ISEN2

ISEN1

PL2003
VSEN

1 2
RTN

3
2
1
+5VS
FB2

FB

TP
PHASE1 1 4
PR203027.4K_0402_1% PR2032 0.36UH_FDUM0640J-H-R36M-P3_22A_20% +APU_CORE
13

14

15

16

17

18

19

20

21

22

23

24

49

1
2 1 0_0402_5% PC2036 ISEN1 2 PR2031 1 2 3 1 2 ISEN2

5
2 1 ISEN3 PR2035 0.22U_0603_25V7K 10K_0402_1%

1
PH2002 PR2033 BOOT1 2 1 2 1 PR2037 PR2034
470K_0402_5%_TSM0B474J4702RE 2 1 ISEN2 BOOT1 100K_0402_5% 4.7_1206_5% PR2038 10K_0402_1%
2 1 PR2036 0_0603_5% 3.65K_0402_1%

2
10_0402_5% ISEN1 VSUM+ 2 1
1

LGATE1
0.22U_0402_10V6K

0.22U_0402_10V6K

@ 4

1 2
1

PR2062 VGATE 29 PC2039

1

PR2039 10K_0402_1% PQ2004 680P_0603_50V7K PR2040

10.5K_0402_1%
@
PC2040
10P_0402_25V8K
TPCA8057-H_PPAK56-8-5
VSUM-
1_0402_1%
2 1
APU_core
2

3
2
1

2
TDC 36A
PC2037

PC2038

2 1
2

VSUM-
CPU_B+ Peak Current 50A
B
VSUM+ OCP current 60A B

2200P_0402_50V7K
PC2041 PR2042 PC2042 PR2043

10U_0805_25V6K

10U_0805_25V6K
2.61K_0402_1%

0.01U_0402_25V7K
Load line -2.1mV/A
10K_0402_5%_ERTJ0ER103J
1

1000P_0402_50V7K301_0402_1% 100P_0402_50V8J 32.4K_0402_1%

5
FSW=300kHz
330P_0402_50V7K
PR2041

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 1 2 1 2 1 2@ 1

DCR 1.1mohm +/-5%

2

1
PC2046

PC2047

PC2048

PC2049
2

2
11K_0402_1%

PR2045 PR2046 PC2050

TYP MAX
12

2.26K_0402_1% 137K_0402_1% 390P_0402_50V7K PQ2005

PR2044

PC2043

PC2044

PC2045
PH2003

2
2 1 2 1 2 1 UGATE2 4 AON7518 1N DFN
H/S Rds(on) :11.7mohm , 14.5mohm
1

1
1

PR2048
750_0402_1% PR2047 PC2051 L/S Rds(on) :2.6mohm , 3.2mohm
VSUM- 2K_0402_1% 680P_0402_50V7K
2

2 1

3
2
1
2 1 2 1 PL2004
PC2052
1

PR2050 820P_0402_50V7K PHASE2 1 4

PC2054 100_0402_1% PR2049 0.36UH_FDUM0640J-H-R36M-P3_22A_20% +APU_CORE
0.1U_0603_50V7K 2 1 2 1 10_0402_5% PC2053 ISEN2 2 PR2051 1 2 3 1 2 ISEN1
2

1
2 1 +APU_CORE PR20530.22U_0603_25V7K 10K_0402_1%
@ @ PR2055 BOOT2 2 1 2 1 PR2054 PR2052
0_0402_5% 4.7_1206_5% PR2056 10K_0402_1%
2 1 APU_VDD_SEN 8 0_0603_5% 3.65K_0402_1%
VSUM+ 2 1

1 2
LGATE2 4
PR2057 PC2055
0_0402_5% PQ2006 680P_0603_50V7K PR2058
TPCA8057-H_PPAK56-8-5 1_0402_1%
0.01U_0402_25V7K

2 1

2
PR2059 VSUM- 2 1

3
2
1
10_0402_5% APU_VDD_RUN_FB_L 8
2

2 1
PC2056
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 42 of 46
5 4 3 2 1
 5 4 3 2 1

D
+APU_CORE D

+APU_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC247

PC248

PC249

PC250

PC251
2

2
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC257

PC258

PC261

PC262

PC259
2

2
+APU_CORE_NB

22U_0805_6.3V6M
+APU_CORE_NB

1
22U_0805_6.3VAM
+APU_CORE_NB

PC265
C C

Local

PC264

330U_D2_2V_Y

330U_D2_2V_Y
1 1

2
@
@ + +

PC266

PC267
2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
10U_0805_6.3V6K
1

1
PC252

PC254

PC255

PC256

PC260
2

2
@

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J
0.22U_0402_16V7K

0.22U_0402_16V7K

0.01U_0402_50V7K

0.01U_0402_50V7K

0.01U_0402_50V7K
1

1
PC273

PC274

PC277

PC278

PC279

PC280

PC285

PC281
2

2
capacitors under processor on bottom side of board

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J
0.22U_0402_16V7K

0.22U_0402_16V7K
1

1
PC275

PC276

PC282

PC283

PC284
2

2
+APU_CORE
Local
B B
330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

1 1 1 1
+ + + +
PC268

PC269

PC270

PC271

2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/29 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR DECOUPLING
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 LA-8712P 0.01
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 27, 2011 Sheet 43 of 46
5 4 3 2 1