M.E / M.Tech.

PRACTICAL END SEMESTER EXAMINATIONS, APRIL/MAY 2022

Second Semester

VL4211 - VERIFICATION USING UVM LABORATORY

(Regulations 2021)

Time : 3 Hours Answer any one Question Max. Marks 100

Aim/Principle/Apparatu Tabulation/Circui Calculation Viva-Voce Recor Total

s required/Procedure t/Program/Drawin & Results d
g
20 30 30 10 10 100

1. Verify 3 general functions of UVM by a simple UVM testbench and DUT

2. Examine the UVM testbench to override a default component DUT.

3. Design and simulate sequence items and sequence of parent sequence and
invoking another sequence.

4. Design and simulate UVM driver and sequencer to serve as an arbiter for
controlling transaction flow from multiple stimulus sequences.

5. Design and simulate UVM monitor and agent

6. Design, simulate and examine the coverage of UVM with suitable experiment

7. Design and simulate an experiment to verify the performance of a certain DUT by

using UVM score board and environment

8. Design and simulate a test that runs multiple sequence in UVM environment

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9. All the verification components need to be encapsulated by targeting the DUT
Justify this by designing and simulating a configurable UVM test environment

10. When verifying a DUT that handles packets flowing back and forth, or processes
instructions, or performs other types of functionalities, you must create a
verification environment that supports the appropriate abstraction level. Perform an
experiment to do transaction-level verification environment in UVM

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