IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 32, NO.

6, JUNE 2022 535

Design and Analysis of High-Gain and Compact

Single-Input Differential-Output Low Noise
Amplifier for 5G Applications
Hao-Hsuan Chen , Wei-Chung Cheng, Cheng-Hung Hsieh, Member, IEEE,
and Zuo-Min Tsai , Senior Member, IEEE
Abstract— This letter describes the design, analysis, and
testing of a 28-GHz single-input differential-output (SIDO)
low-noise amplifier (LNA) with a noise figure of 2.5 dB, compact
size (0.25 mm2 ), and high gain (22.3 dB). The proposed LNA
was fabricated using the Taiwan Semiconductor Manufacturing
Company (TSMC) 65-nm CMOS process. This amplifier
contains a two-stage common-source (CS) buffer amplifier for a
low-noise design and combines CS and common-gate transistors
for converting single-ended signal into differential signal.
A novel method of common-mode rejection ratio optimization is Fig. 1. Circuit topologies of (a) general SIDO LNA and (b) proposed method
used to determine the optimal phase compensation transmission of CMRR optimization to minimize gain and phase imbalances.
line and transistor size to reduce gain and phase imbalances
simultaneously. The gain and phase imbalances were 0.042 dB
and 2.6◦ at 28 GHz, respectively. Compared with published
LNAs, this SIDO LNA achieved the high figure of merits (FoMs)
of 7.17 and 2.27, respectively. Therefore, this LNA can be used
for 5G NR band of n257 (26.5–29.5 GHz), n258 (24.25–27.5 GHz),
and n261 (27.5–28.35 GHz).
Index Terms— CMOS, common-mode rejection ratio (CMRR),
low-noise amplifier (LNA), monolithic microwave integrated
circuit (MMIC), single-input differential-output (SIDO).

I. I NTRODUCTION Fig. 2. Schematic of proposed SIDO LNA.

I N A millimeter-wave 5G communication system, phased

array systems are employed to increase power budgets
and overcome path loss. Phased array systems require beam-
former integrated circuits (ICs) for multiple RF channels [1].
Because the consumer electronics industry is influenced by
trends toward reduced size and cost, designers must minimize
component size and integrate as many RF channels as possible
in a single beamformer IC [2]. Because of link budget consid-
erations, a low-noise amplifier (LNA) is crucial in a receiver.
Manuscript received October 18, 2021; revised December 28, 2021;
accepted January 31, 2022. Date of publication February 18, 2022; date of
current version June 7, 2022. This work was supported in part by the Center
for mmWave Smart Radar Systems and Technologies of Taiwan through
the Featured Areas Research Center Program within the framework of the
Higher Education Sprout Project by the Ministry of Education of Taiwan;
in part by the Ministry of Science and Technology (MOST), Taiwan, under
Grant 110-2622-E-A49-008, Grant 107-3017-F-009-001, and Grant 109-2221-
E-009-124-MY3; in part by Industrial Technology Research Institute (ITRI),
Taiwan; and in part by Taiwan Semiconductor Research Institute (TSRI),
Taiwan. (Corresponding author: Zuo-Min Tsai.)
Hao-Hsuan Chen is with the Advanced Institute of Manufacturing With
High-Tech Innovations, National Chung Cheng University, Chiayi 621301,
Taiwan.
Wei-Chung Cheng is with the Department of Electrical Engineering,
National Chung Cheng University, Chiayi 621301, Taiwan.
Cheng-Hung Hsieh and Zuo-Min Tsai are with the Center of mmWave
Smart Radar Systems and Technologies, and the College of Electri-
cal and Computer Engineering, Institute of Communications Engineering,
National Yang Ming Chiao Tung University, Hsinchu 30050, Taiwan (e-mail:
zuomintsai@gmail.com).
Color versions of one or more figures in this letter are available at
https://doi.org/10.1109/LMWC.2022.3149033.
Digital Object Identifier 10.1109/LMWC.2022.3149033
1531-1309 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
If a high-gain (typically above 20 dB) LNA is employed in
the first stage of the receiver, the noise figure (NF) of the
entire receiver is dominated by the LNA noise [3]. Therefore,
a compact and high-gain LNA is important for a receiver in a
millimeter-wave beamformer IC.
In a beamformer IC, the input–output (I/O) of antenna
ports are single-ended because of the unbalanced structure of
antennas [4]. Recently, differential circuits have been adopted
for millimeter-wave components such as phase shifters [5], [6]
and variable-gain amplifiers [7], [8] because of the benefits
of their high noise rejection capability for power supplies
and substrates, simple design enabling 180◦ phase switching,
and compact size achieved through the use of transformers.
Therefore, a single-input differential-output (SIDO) LNA pro-
vides a solution for connecting single-ended antenna ports and
differential receiver components while achieving a low NF
[9]–[19]. SIDO LNAs can be implemented using multiple
methods. The straightforward method involves integrating
LNAs with passive baluns [9], [10]. Passive baluns have wide
bandwidth and low phase/gain imbalances. The costs using
passive baluns are additional loss and chip area. Another
method combines common-source (CS) and common-gate
(CG) transistors to implement the balun and LNA in a single
circuit [4], [11]–[15]. This method provides high gain with
a small area. The phase imbalance cannot be optimized in a
wide frequency range because of the leakage current from the
CS and CG transistors. In [15], a transmission line was applied
to compensate for the phase imbalance. The gain imbalance
of the SIDO LNA, which uses CS and CG transistors with

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 536
Fig. 3. Contour maps showing the ratio between common- and differential-mode G max on the plane of W M4 / W M3 and L 1 at frequencies of (a) 20, (b) 30,
and (c) 40 GHz.
a wide bandwidth, still requires optimization. In summary,
the challenge of designing of SIDO LNA is to consider
gain and phase imbalances, simultaneously. However, gain
and phase imbalances depend on the device topology (CS
or CG), transistor size, and impedance matching condition.
Therefore, a comprehensive factor covering the gain and phase
imbalances is required for device optimization. In this letter,
a design method is proposed that involves using the common-
mode rejection ratio (CMRR) to optimize signal balance in a
SIDO LNA. When the CMRR is applied for size selections
of device and phase compensation line, the performance can
be optimized to overcome the gain and phase imbalances for
a wide bandwidth. The output matching network then can be
designed for high gain. To verify feasibility of the proposed
design method, a wideband, high-gain LNA with low gain and
phase imbalances was created. It is the first letter to apply
CMRR analytical method to achieve SIDO structure using
the Taiwan Semiconductor Manufacturing Company (TSMC)
65-nm CMOS process for LNA, and has detailed design
principles and measurement results. This LNA achieves an
NF of less than 4 dB, differential gain exceeding 20 dB, gain
imbalance lower than 0.5 dB, and phase imbalance of 4◦ in
the frequency range of 21–33 GHz.
II. A NALYSIS
The circuit topology of a general SIDO LNA is shown
in Fig. 1(a). A SIDO device has one input matching and
two output matching networks. The input matching network
matches the source impedance to the optimal impedance for
noise reduction. Because changing the matching condition
leads to both phase and gain imbalances, in this topology,
the two output-matching networks are simplified as two loads
with the same impedance (Z L ). To balance differential output
signal, a comprehensive design method is required to opti-
mize gain and phase imbalances simultaneously. Instead of
optimizing gain and phase imbalances separately, the proposed
method involves optimizing the CMRR of this SIDO amplifier.
Fig. 1(b) presents the analysis method for evaluating the
common-mode and differential-mode gains of this SIDO LNA.
An ideal balun is applied to the outputs of the SIDO device.
Because both devices have identical load impedance Z L , the
differential port of the balun is connected to the load with
impedance of 2Z L , and the common port of the balun is
connected to the load with impedance of Z L /2. Under this
configuration, the differential amplifier can be equivalent to
two amplifiers that operate in single-to-differential and single-
to-common mode, as shown in Fig. 1(b). In Fig. 1(b), CMRR
is the ratio between the output voltages in differential and
common mode. CMRR can be expressed as the (VO+ − VO− )/
(VO+ + VO− ). While the output signal has perfect magnitude
and phase balance, (VO+ + VO− ) is equal to zero. Therefore,
CMRR, which has (VO+ + VO− ) of the denominator can be
used as a factor to estimate both the gain and phase imbal-
ances of the device. Therefore, the difference in maximum
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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 32, NO. 6, JUNE 2022
Fig. 4. Gain and phase imbalances of different CMRR.
Fig. 5. (a) Gain imbalance and (b) phase imbalance with and without
compensation.
transducer gain (G max ) between the single-to-differential mode
and single-to-common mode determines the CMRR of this
SIDO amplifier. When the G max is optimized, the CMRR
can be optimized, and the gain and phase imbalance can be
minimized.
III. D ESIGN
The proposed LNA is presented in Fig. 2; it contains two-
stage CS buffer amplifier with devices M1 and M2 , and
amplifiers for Path 1 and Path 2 [CG amplifier device (M3 ) for
Path 1, phase compensation line, and a CS amplifier device
(M4 ) for Path 2]. Path 1 and Path 2 are assigned to RFout+ and
RFout−, respectively. The size of M1 is 2×16 µm for minimal
NF, and the size of M2 is 2 ×12 µm for maximal gain. At low
frequency, the CG and CS devices have gains with equal
magnitudes and opposite signs, and they can output differential
signals. However, at high frequency, the reactance of the
devices influences both the gain magnitude and phase. In this
design, a delay line L 1 is used to compensate for the phase
imbalance, and the ratio between the device sizes W M4 /W M3
is designed to compensate for the gain imbalance. Fig. 3
presents a contour map of the ratio between the common- and
differential-mode G max on the plane of W M4 /W M3 and L 1 at
frequencies of 20, 30, and 40 GHz, and Fig. 4 shows the sta-
tistical contour plot of CMRR versus phase/gain imbalance of
this design while changing the design parameters (W M4 /W M3
and L 1 ). The maximal CMRR has the best phase/gain imbal-
ance performance. The red crosses in Fig. 3 represent the
selected sizes (W M4 /W M3 = 1.17 and L 1 = 105 µm) at
which the CMRRs are optimized at those frequencies. The M4
transistor is (2 × 12 µm) × 1.17 = 2 × 14 µm and the lengh of
the phase compensation line L 1 is 105 µm. Therefore, a wide-
band single-to-differential frequency response can be achieved.
Demonstrating that optimizing the CMRR can achieve low
gain and phase imbalances, Fig. 5 presents the gain difference
 CHEN et al.: DESIGN AND ANALYSIS OF HIGH-GAIN AND COMPACT SIDO LNA FOR 5G APPLICATIONS
TABLE I
P ERFORMANCE C OMPARISON W ITH S TATE - OF - THE -A RT LNA S
Fig. 6. Photograph of the fabricated LNA.
Fig. 7. (a) Measured and simulated results related to the S-parameter of
single-ended input to single-ended output and (b) SIDO.
Fig. 8. (a) Measured and simulated results for single-ended input to single-
ended output NF and (b) measured single-ended input to single-ended output
input IP3 (IIP3 ) for the LNA.
in a wide frequency range with and without compensation.
Such compensation can reduce the gain imbalance from 1.2 dB
to 0.4 at 28 GHz, and phase imbalance is below 4◦ in the
frequency range of 20–40 GHz. The phase imbalance can
be improved by 7◦ with compensation at 28 GHz. Therefore,
CMRR can minimize the gain and phase imbalances of this
SIDO amplifier.
IV. M EASUREMENT
A photograph of the SIDO LNA chip is presented in
Fig. 6. The core area has a size of 0.87 mm × 0.29 mm.
The measured and simulated S-parameters are presented
in Fig. 7. The maximal |S21 |/|S31 | was 19.3 dB/19.26 dB,
and the relevant figure was 22.3 dB for the single-
to-differential mode, the return loss was less than 10 dB at
operating frequencies, and the 3-dB bandwidth was 12 GHz
from 21 to 33 GHz. The NF measured from 20 to 32 GHz was
lower than 3 dB, the IP1 dB,21 /IP1 dB,31 was −14.7/−16.7 dBm,
and the IIP3,21 /IIP3,31 was −5/−7 dBm, as shown in Fig. 8.
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537
Fig. 9. Measured and simulated results for (a) gain imbalance and (b) phase
imbalance.
The measurements were in good agreement with the simulated
results. The gain imbalance was 0.042 dB, and the phase
imbalance was lower than 2.6◦ , as presented in Fig. 9. The
discrepancy of the phase imbalance is mainly attributed to
the process variation, and the compensation t-line is not
a wideband structure. Therefore, the measured results of
out-band frequencies are easier to deviate from the out-band
electromagnetic (EM) simulations. The results of comparisons
of SIDO LNAs from other published works and with this
study are revealed in Table I. Of all the aforementioned LNAs,
the proposed LNA has the high gain, small size, and high
figure of merits (FoMs). The FoM equations are as follows:
Gain [lin.] × BW [GHz]
FoM1 = (1)
(NF [lin.] − 1) × Pdc [mW]
Gain [lin.] × BW [GHz] × IIP3 [mW]
FoM2 = . (2)
(NF [lin.] − 1) × Pdc [mW]
V. C ONCLUSION
The proposed SIDO LNA is designed for K - and K a-band
5G communication systems using the TSMC 65-nm CMOS
process. With the proposed design method, the CMRR can
be optimized to simultaneously minimize the gain and phase
imbalances. Measurement results indicate performance com-
parable to that of others LNAs, with 22.3-dB differential
gain, 2.5-dB NF, 0.042-dB gain imbalance, 2.6◦ phase imbal-
ance, and 0.25-mm2 chip size. The FoM1/FoM2 achieved
was 7.17/2.27, demonstrating that the proposed LNA can
be used for 5G NR band of n257 (26.5–29.5 GHz), n258
(24.25–27.5 GHz), and n261 (27.5–28.35 GHz).
ACKNOWLEDGMENT
The authors would like to thank Dr. T.-C. Chen for his
assistance. This letter has been revised by Wallace Academic
Editing.
 538 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 32, NO. 6, JUNE 2022
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