Co Complete Notes

COMPUTER ORGANIZATION UNIT-1
• Unit - I Logic Gates:
1. AND Gate: Definition, symbol, truth table and timing diagram

2. OR Gate: Definition, symbol, truth table and timing diagram.
3. NOT Gate: Definition symbol, truth table and timing diagram.
4. NAND Gate: Definition, symbol, truth table and timing diagram.
5. NOR Gate: Definition, symbol, truth table and timing diagram.
6. Exclusive OR Gate: Definition, symbol, truth table and timing diagram.
AND GATE DEFINITION: The AND gate is an electronic circuit that gives a high output
(1) only if all its inputs are high.
• An AND gate accepts two input signals and gives only one output
• A dot (.) is used to show the AND operation i.e. A.B.
TIMING DIAGRAM(AND)
• OR GATE DEFINITION: The OR gate is an electronic circuit that gives

a high output (1) if one or more of its inputs are high.
• An OR gate accepts two input signals and gives only one output
• A plus (+) is used to show the OR operation.
UNIT 1 NOTES COMPUTER ORGANIZATION - BY Dr. DEEPA, Ms. SHEETAL & Ms.
SOWMYA, DCA, PRESIDNCY COLLEGE Page 1
TIMING DIAGRAM(OR)
• NOT GATE DEFINITION

• The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter
• A NOT gate accepts one input value and produces one output value
TIMING DIAGRAM(NOT)
• NAND GATE Definition: The outputs of all NAND gates are high if any of the inputs are low.
• The NAND gate is the complement of AND gate
• It has two inputs and only one output
• The symbol is an AND gate with a small circle on the output. The small circle represents
inversion.
TIMING DIAGRAM(NAND)
• NOR GATE Definition: The output of NOR gate is high if both of the inputs are low.
• The symbol is an OR gate with a small circle on the output. The small circle
represents inversion.
• The NOR gate is the complement of OR gate
• It has two inputs and only one output
TIMING DIAGRAM(NOR)
• XOR GATE Definition: The 'Exclusive-OR' gate is a circuit which will give a high output ,When
both the inputs are different. An encircled plus sign (+ ) is used to show the XOR operation.
– An XOR gate produces
– 0 or LOW if its two inputs are the same
– 1 or HIGH if its inputs are different
TIMING DIAGRAM(XOR)
An XNOR gate produces

1 or HIGH if its two inputs are the same
0 or LOW if its inputs are different
TIMING DIAGRAM OF XNOR
UNIVERSAL GATES-NOTES
• NAND and NOR are called universal gates
• As other basic gates and circuits are constructed using NAND and NOR.
EXPLAIN NAND AS UNIVERSAL
1. Construction of NOT gate using NAND:
 A NAND gate can be used as NOT gate with a single input by connecting two
inputs of the NAND gates together.
2. Construction of AND gate using NAND
• Two NAND gates are used for Constructing AND gate.
• First NAND gate output is connected as an input to second NOT (NOT using
NAND) gate to construct AND gate.
3. Construction of OR gate using NAND
• Three NAND gates are used to construct OR gate.
• The output of two NOT(NOT using NAND) gates are connected as a inputs to NAND gate
to construct OR gate
COMBINATIONAL CIRCUITS NOTES - Dr. DEEPA & Ms. SHEETAL, DCA, PRESIDNCY COLLEGE
Page 9
EXPLAIN NOR AS UNIVERSAL

1. Construct NOT gate using NOR
• A NOR gate can be used as NOT gate with a single input by connecting two inputs of the NOR
gates together.
2. Construct OR gate using NOR
 Two NOR gates are used for Constructing OR gate.
• First NOR gate output is connected as an input to second NOT (NOT using NOR) gate to
construct OR gate
3. Construct AND using NOR Gate

Page 10
• Three NOR gates are used to construct AND gate.
• The output of two NOT(NOT using NOR) gates are connected as a inputs to NOR gate to
construct AND gate
Page 11
Combinational Circuits: Half Adder and Full Adder
Introduction to Combinational logic circuits:
Page 12
• Combinational circuit is a circuit in which we combine the different logic

gates in the circuit.
• Combinational Logic circuit is implemented using Boolean circuits, where

the output of logic circuit is a pure function of the present inputs only.
• Example: half- adder, full-adder, encoder, decoder.
characteristics of combinational circuits
• The combinational circuit does not use any memory.
• The output of combinational logic circuit depends only on the current

inputs
• A combinational circuit can have n number of inputs and m number of

outputs.
• HALF ADDER (DEFINITION):
• Half adder is a combinational logic circuit with two inputs and two outputs.
It is used to add two binary bits.
• A circuit that computes the addition of two bits

and produces the Sum and Carry bit is called a half adder
• This circuit has two inputs A & B and two outputs namely SUM and CARRY.
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• HALF ADDER (BLOCK DIAGRAM)
HALF ADDER (TRUTH TABLE)
HALF ADDER (LOGIC CIRCUIT)
• HALF ADDER (Expressions):
SUM = A  B
CARRY = AB
Page 14
FULL Adders (Definition & Block Diagram)
• FULL Adders Definition: A full - adder is a combinational circuit that

performs the addition of three binary bits. It consists of three inputs A, B, C
& two outputs SUM and CARRY.
• FULL Adders BLOCK DIAGRAM
FULL ADDER (TRUTH TABLE)
FULL ADDER (LOGIC CIRCUIT)
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FULL ADDER(EXPRESSION)
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
For the CARRY-OUT (Cout) bit:
Cout = Cin(A XOR B) OR A AND B = Cin(A ⊕ B) + A.B
Page 16
Sequential Circuits: SR FLIPFLOP
Introduction to SEQUENTIAL circuits:

• The output of circuit depends on the previous output and the present inputs.
• This type of circuit uses previous output, present input, clock and memory
element.
• sequential circuit consist of combinational logic circuit and memory element
Memory element
• A memory element is used to store 1 bit data.
• A one bit memory is called as bi-stable or flip-flop.
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Clock: Importance of clock signal in sequential circuits
• A clock is a signal, which oscillates between logic level 0 and logic level 1,
repeatedly. Square wave with constant frequency is the most common form of
clock signal.
• A clock signal has “edges”. These are the instants at which the clock changes
from 0 to 1 (a positive edge) or from 1 to 0 (a negative edge).
• Clock signals control the outputs of the sequential circuit.
• A digital clock signal is basically a square wave voltage and it is used in
synchronous device.
• Triggering: It is a process of applying clock signal ( input) to a Flip-Flop
• Types of Triggering
1. Level triggering: High level and low level
2. Edge triggering : Positive edge triggering [Rising Edge]
Negative edge triggering [Falling Edge]
• High Level Triggering: When a flip flop is required to respond at its HIGH
state, a HIGH level triggering method is used
• Low Level Triggering: When a flip flop is required to respond at its LOW state, a
LOW level triggering method is used.
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• Positive Edge Triggering: If flip-flop changes its state from ‘0’ OFF to ‘1’ ON
state.
• Negative Edge Triggering: If flip-flop changes its state from ‘1’ ON to ‘0’ OFF
state.
Definition of FLIPFLOP:
• It is the basic memory element in a digital computer.
• It is used to store one bit of information with a ‘0’ or ‘1’ . It has only two
states ‘0’ OFF & ’1’ ON.
• TYPES OF FLIPFLOPS
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• SR flip-flop
• D flip-flop
• JK flip-flop
• T flip-flop
• SR FLIPFLOP or SET/RESET FLIP FLOP (DEFINITION):

• The SR Flip Flop has 3 inputs, SET (S),RESET (R) and CLK.
• The SR Flip Flop has two outputs, Q and Q¯
• The Q output is considered the normal output and is the one most used.
• The other output Q¯ is simply the compliment of output Q.
• SR FLIPFLOP (BLOCK DIAGRAM)
SR FLIPFLOP (TRUTH TABLE)
SR FLIPFLOP (LOGIC CIRCUIT)
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• WORKING OF SR FLIPFLOP:
• Case 1:With the inputs the S=0 and R=0, then the output remains in
previous state i.e. it holds the previous data.(No change/ Hold state)
• Case 2:With the inputs set to S=0and R=1, when the clock pulse is applied,
the active high signal on R resets the filp flop to 0 ,then the flip flop said to
be in the RESET state.
• Case 3:With the inputs set to S=1and R=0, when the clock pulse is applied,
the active high signal on S sets the flip flop to 1 ,then the flip flop said to be
in the SET state.
• Case 4: When both the S=1 and R=1, then the flip flop will be in undefined
state(INVALID/PROHIBITED).
TIMING DIAGRAM OF SR FLIPFLOP
Page 21
• D FLIPFLOP or DELAY/DATA FLIP FLOP (DEFINITION):

• It is a flip-flop with single input data D and a clock
• It is called as data flip flop and also Delay Flip flop
• The data at D input is delayed by one clock pulse before it gets to output.
• D FLIPFLOP (BLOCK DIAGRAM)
D FLIPFLOP (TRUTH TABLE)

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D FLIPFLOP (LOGIC CIRCUIT)
• WORKING OF D FLIPFLOP:
• Case 1 :With the inputs set to D=0, when the clock pulse is applied, the
active high signal resets the flip flop to Q= 0 ,then the flip flop said to be in
the RESET state.
• Case 2:With the inputs set to D=1, when the clock pulse is applied, the
active high signal SETS the flip flop to Q=1 ,then the flip flop said to be in
the SET state.
TIMING DIAGRAM OF D FLIPFLOP
Page 23
• JK FLIPFLOP or JACK/KILBY FLIP FLOP (DEFINITION):

• A JK flip-flop has two inputs similar to that of RS flip-flop. We can say JK flip-flop is
a refinement of RS flip-flop.
• JK means Jack Kilby, a Texas instrument engineer who invented IC.
• The three inputs of JK Flip-flop is J (set) , K (reset) ,clk and two outputs Q and Q’
• JK FLIPFLOP (BLOCK DIAGRAM)
Page 24
JK FLIPFLOP (TRUTH TABLE)
JK FLIPFLOP (LOGIC CIRCUIT)
• WORKING OF SR
JK FLIPFLOP:
• Case 1:With the inputs the J=0 and K=0, then the output remains in
previous state i.e. it holds the previous data.(No change)
Page 25
• Case 2:With the inputs set to J=0and K=1, when the clock pulse is applied,
the active high signal on R resets the flip flop to 0 ,then the flip flop said to
be in the RESET state.
• Case 3:With the inputs set to J=1and K=0, when the clock pulse is applied,
the active high signal on S sets the flip flop to 1 ,then the flip flop said to be
in the SET state.
• Case 4: When both the J=1 and K=1, then the flip flop will be in TOGGLE
state(TOGGLE).
TIMING DIAGRAM OF SR
JK FLIPFLOP
• T FLIPFLOP or TOGGLE FLIP FLOP (DEFINITION):
• T FLIPFLOP (BLOCK DIAGRAM)
Page 26
T FLIPFLOP (TRUTH TABLE)
T FLIPFLOP (LOGIC CIRCUIT)
• WORKING OF T FLIPFLOP:
• CASE1: When T=0 and clock=1 then Q and Q’ Holds Previous States. So no
change in outputs. This state is referred as HOLD STATE
Page 27
• CASE 2: When T=1 and clock=1 then Q and Q’ will change their outputs
from 0 to 1 and 1 to 0 for every clock period, so toggling of outputs. This
state is referred as TOGGLE STATE
TIMING DIAGRAM OF T FLIPFLOP
Boolean algebra
• Mathematician George Boole invented the Boolean Algebra. Boolean
algebra is a division of mathematics which deals with operations on
logical values and incorporates binary variables. Boolean Algebra is used
to analyze and simplify the digital (logic) circuits.
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Description of the Laws of Boolean Algebra
Annulment Law – A term ANDéd with a “0” equals 0 or ORéd with a “1” will
equal 1.
A . 0 = 0 A variable AND’ed with 0 is always equal to 0.

A + 1 = 1 A variable OR’ed with 1 is always equal to 1.
Identity Law – A term ORéd with a “0” or ANDéd with a “1” will always
equal that term.
A + 0 = A A variable OR’ed with 0 is always equal to the variable.

A . 1 = A A variable AND’ed with 1 is always equal to the variable.
Idempotent Law – An input that is ANDéd or ORéd with itself is equal to that
input.
A + A = A A variable OR’ed with itself is always equal to the variable.

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A . A = A A variable AND’ed with itself is always equal to the variable.
Complement Law – A term ANDéd with its complement equals “0” and a
term ORéd with its complement equals “1”.
A’ . A = 0 A variable AND’ed with its complement is always equal to 0.

A’ + A = 1 A variable OR’ed with its complement is always equal to 1.
Commutative Law – The order of application of two separate terms is not

important.
A . B = B . A The order in which two variables are AND’ed makes no

difference.
A + B = B + A The order in which two variables are OR’ed makes no
difference.
Double Negation Law – A term that is inverted twice is equal to the original
term.
(A’)’ = A A double complement of a variable is always equal to the variable.
de Morgan´s Theorem – There are two “de Morgan´s” rules or theorems,
(1) Two separate terms NORéd together is the same as the two terms inverted
(Complement) and ANDéd for example, (A+B)’ = A’. B’.
(2) Two separate terms NANDéd together is the same as the two terms inverted
(Complement) and ORéd for example, (A.B)’ = A’ +B’.
De Morgan´s Theorem(5 MARKS)***
1. (A + B)' = A'B’ (OR LAW)equ 1
2. (AB)' = A' + B‘ (AND LAW)equ2
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1. Statement 1 (A + B)' = A'B’

This theorem states that the complement of the sum of Boolean
expression is equal to product of the complement of the individual
expression
Proof using truth table
2. Statement 2: (AB)' = A' + B‘

This theorem states that the complement of product of Boolean
expression is equal to the sum of the complement of the individual
expression.
Proof using truth table
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Duality Theorem
Duality is one of the characteristics of Boolean Algebra. Each expression in

Boolean algebra has its dual. The duality theorem is without any proof and states
that :
Starting with a Boolean expression, one can get another expression by following
the below given steps:
Change each OR sign to AND sign
ge each AND sign to OR sign
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COMPUTER ORGANIZATION UNIT -2
Unit-II
Computer Organization: Instruction format, Types of basic computer
instruction format, Instruction cycle, Design of basic computer flowchart,
Interrupt and its types, Interrupt cycle
Registers
1. The data register (DR) holds the operand read from memory.
2. The accumulator (AC) register is a general purpose processing register.
3. The instruction read from memory is placed in the instruction register (IR).
4. The temporary register (TR) is used for holding temporary data during the
5. The memory address register (AR) has 12 bits to hold address.

6. The program counter (PC) also has 12 bits and it holds the address of the next
instruction to be read from memory after the current instruction is executed.
7. Two registers are used for input and output. The input register (INPR) receives
an 8-bit character from an input device.
8. The output register (OUTR) holds an 8-bit character for an output device.
Types of basic computer Instructions:
 Memory - reference instruction.

 Register - reference instruction.
 Input-Output instruction
UNIT 2 NOTES COMPUTER ORGANIZATION - BY Dr. DEEPA, Ms. SHEETAL & Ms. SOWMYA, DCA,
PRESIDNCY COLLEGE
Memory Reference – These instructions refer to memory address as an operand. The

other operand is always accumulator.
 Specifies 12-bit address,
 3-bit opcode (other than 111) and 1-bit addressing mode for direct and indirect
addressing.
MRI
AND Performs logical AND operation with AC content
LDA Load Memory Word to AC
ADD ADD memory word to AC
STA Store the content of AC to memory
BUN Branched Unconditionally
BSA Branch and save return address
ISZ Increment and skip if zero
1. AND to AC
This is an instruction that performs the AND logic operation on pairs of bits in AC
and the memory word specified by the effective address. The result of the operation
is transferred to AC.
2. ADD to AC
This instruction adds the content of the memory word specified by the effective
address to the value of AC. The sum is transferred into AC and the output carry Cout
is transferred to the E (extended accumulator) flip-flop.
3. LDA: Load to AC
This instruction transfers the memory word specified by the effective address to AC.
STA: Store AC
This instruction stores the content of AC into the memory word specified by the
effective address.
4. BUN: Branch Unconditionally

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This instruction transfers the program to instruction specified by the effective

address.
The BUN instruction allows the programmer to specify an instruction out of
sequence and the program branches (or jumps) unconditionally.
5. BSA: Branch and Save Return Address

This instruction is useful for branching to a portion of the program called a
subroutine or procedure. When executed, the BSA instruction stores the address of
the next instruction in sequence (which is available in PC) into a memory location
specified by the effective address.
Register Reference – These instructions perform operations on registers rather than

memory addresses.
 The IR(14 – 12) is 111 (differentiates it from memory reference) and
 IR(15) is 0 (differentiates it from input/output instructions).
 The rest 12 bits specify register operation.
 The first seven register-reference instructions perform clear, complement,

circular shift, and increment micro operations on the AC or E registers.
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 The next four instructions cause a skip of the next instruction in sequence
when
 If condition is satisfied. The skipping of the instruction is achieved by
incrementing PC.
 The AC is positive when the sign bit in AC(15) = 0; it is negative when
AC(15) = 1. The content of AC is zero (AC = 0) if all the flip-flops of the
register are zero.
 The HLT instruction stops the sequence counter.
Input/ Output Reference – These instructions are for communication between

computer and outside environment (IO devices).
 The IR(14 – 12) is 111 (differentiates it from memory reference) and
 IR(15) is 1 (differentiates it from register reference instructions).
 The rest 12 bits specify I/O operation.
INPUTOUTPUT INSTRUCTION
IO reference
instructions
INP Input character to AC
OUT Output character from AC
SKI Skip on input flag
SKO Skip on output flag
ION Interrupt on
IOF Interrupt off
 The INP instruction transfers the input information from INPR into the eight
bits of AC and also clears the input flag to 0.
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 The OUT instruction transfers the eight least significant bits of AC into the
output register OUTR and clears the output flag to 0.
 The next two instructions, check the status of the flags and cause a skip of
the next instruction if the flag is 1.
 The instruction that is skipped will normally be a branch instruction to return
and check the flag again.
 The branch instruction is not skipped if the flag is 0. If the flag is 1, the branch
instruction is skipped and an input or output instruction is executed.
 The last two instructions set and clear an interrupt enable flip-flop IEN. The
purpose of IEN is explained in conjunction with the interrupt operation
Instruction Cycle: Processing required for complete execution of an instruction is

called instruction cycle.
In Basic Computer, a machine instruction is executed in the following cycle:

1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction
Upon the completion of step 4, control goes back to step 1 to fetch, decode and
execute the next instruction.
This process is continued indefinitely until HALT instruction is encountered.
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Fetch and Decode

Sequence of steps required for fetching instruction from memory to CPU internal
register is known as fetch cycle.
For fetching and decoding, the steps are:

i) Initially, PC holds the address of first instruction to fetch. With timing signal T0,
address pointed by PC is transferred to the AR.
ii) The processor fetches instruction to IR from memory location referenced by AR
and increment PC for next instruction. This happens with timing signal T1.
iii) Processor interprets instruction and performs required action i.e. decoding during
time period T2.
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Type of instruction during instruction cycle can be determined by a special bit called
D7 and the Mode value I are specify using following Notations
D’7 I T3: AR <- M [AR]
D’7 I’ T3: Nothing
D7 I’ T3: Execute a register-reference instruction
D7 I T3: Execute an input-output instruction
Then, among decoded, D7 determines which type of instruction.

i) If D7 = 1, it will be either register-reference or input-output instruction.
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a) If I = 1, input-output instruction is executed during T3.

b) If I = 0, register-reference instruction is executed during T3.
ii) If D7 = 0, it will be memory-reference instruction.
a) If I = 1, indirect addressing mode instruction during T3.
b) If I = 0, direct addressing mode instruction during T3.
The SC is reset after executing each instruction.
Interrupt Cycle
The process of altering the flow of execution of a program is called interrupt.
An Interrupt flip flop R is included in computer system, When R = 0, it specifies
Instruction cycle and R = 1 specifies the Interrupt cycle.
This is a hardware implementation of a branch and save return address operation.
Fig: flowchart of interrupt cycle
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Steps of the Interrupt Cycle are:-
1. Processor checks for interrupt, by indicating interrupt signals(R = 1 interrupt cycle,

R=0 Instruction cycle).
2. During Execution phase of instruction cycle checks the IEN ,If IEN =0,If there is
no interrupt, fetch next instruction
3. If IEN = 1, there is an interrupt, it checks FGI =1 or FGO =1

4. Set R =1 and Suspend the execution of the current program and start with Interrupt
cycle
 In interrupt cycle Saves its context(return address) (M[0]<-PC)
 Set program counter (PC) to interrupt service routine (pc<-1)
 Process the interrupt
 Restore the context of the original program and continue its
execution (IEN =0,R = 0)
Design of basic Computer:
Computer is an electronic Machine which is used to perform arithmetic and logical
operations and it stores data for future use.
• The basic computer consists of the following hardware components:
1. Memory unit.
2. Nine registers: AC, PC, DR, AR, IR, TR, OUTR, INPR and SC.
3. Seven flip flops: I, SR, E, R, IEN, FGI and FGO.
4. Two decoders: 3X8 o decoder and 4X16 timing decoder.
5. A 16-bit common bus.
6. Control logic gates.
7. Adder and logic circuit connected to the input of AC.
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1. Memory unit
• RAM stands for random access memory. It is also called direct access memory
Random access means that each individual byte in entire memory can be
accessed directly. RAM is used to store data and instructions temporarily.
• ROM stands for Read Only Memory. The instructions in ROM prepare the
computer for use. These instructions can only be read but cannot be changed or
deleted. It is not possible to write new information or instructions into the
ROM.
2. Registers
3. Seven flip flops: I, S, E, R, IEN, FGI and FGO.
FLIP USAGE
FLOP
I TO SET MODE VALUES OF
COMPUTER INSTRUCTIONS
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SR SET AND REST FLIPFLOP

R INTERRUPT flip flop
IEN Interrupt Enable flip flop
FGI Flag Input flip flop
FGO Flag output flip flop
E Extended bit of Accumulator Flipflop
4. Decoder -3X8 for Register input/output, 4X16 decoder used for Timing control.
5. Common bus: It is 16 bit bus system which is used to carry information to one
location to another location
6. Control Logic gates: It is used to realize basic gate operation and control the flow
of information
8. Adder Logic circuit: It is used to perform arithmetic logic operations.
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Basic design of computer Flowchart

This is the final flowchart of the instruction cycle including interrupt cycle for the
basic computer.
Instruction cycle
Sequence of steps required for fetch and decode
Execute
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Type of instruction during instruction cycle can be determined by a special bit called
D7 and the Mode value I are specify using following Notations
D’7 I T3: AR <- M [AR]
D’7 I’ T3: Nothing
D7 I’ T3: Execute a register-reference instruction
D7 I T3: Execute an input-output instruction
Interrupt cycle
• If R =1 and Suspend the execution of the current instruction execution and
start with Interrupt cycle
• In interrupt cycle Saves its context(return address) (AR<-0,TR<-PC)
• Set program counter (PC) to interrupt service routine (pc<-0 )
• Process the interrupt(PC<-PC +1)
• Restore the context of the original program and continue its execution (IEN
=0,R = 0, SC=0)
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Interrupt:-
The process of altering the flow of execution of a program is called interrupt.

Program interrupt refers to the transfer of program control from a currently running
program to another service program as a result of an external or internal generated
request. Control returns to the original program after the service program is executed.
Types of interrupts
 Internal Interrupts
 Software Interrupts
 External Interrupts
Internal Interrupts
• Internal interrupts arise from illegal or erroneous use of an instruction or data.
• They are also called trap.
• Examples of interrupts caused by internal error conditions are register
overflow, attempt to divide by zero, stack overflow, etc.
External Interrupts
• They come from I/O Devices, or from circuit monitoring or from any other
external source.
• Examples for causing external interrupts are I/O device requesting transfer of
data, I/O device finished transfer of data, elapsed time of an event.
Software Interrupts
• Software interrupt is a special call instruction that behaves like an interrupt
rather than a subroutine call. It can be used by the programmer to initiate an
interrupt procedure at any desired point in the program.
• Example:
• Windows to linux/linux to windows
• User mode to admin mode/admin mode to user mode.
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COMPUTER ORGANIZATION UNIT-1

• Unit - I Logic Gates:

1. AND Gate: Definition, symbol, truth table and timing diagram

• OR GATE DEFINITION: The OR gate is an electronic circuit that gives

• NOT GATE DEFINITION

An XNOR gate produces

TIMING DIAGRAM OF XNOR

EXPLAIN NAND AS UNIVERSAL

1. Construction of NOT gate using NAND:

2. Construction of AND gate using NAND

• Two NAND gates are used for Constructing AND gate.

3. Construction of OR gate using NAND

• Three NAND gates are used to construct OR gate.

EXPLAIN NOR AS UNIVERSAL

2. Construct OR gate using NOR

 Two NOR gates are used for Constructing OR gate.

3. Construct AND using NOR Gate

• Three NOR gates are used to construct AND gate.

Combinational Circuits: Half Adder and Full Adder

Introduction to Combinational logic circuits:

• Combinational circuit is a circuit in which we combine the different logic

• Combinational Logic circuit is implemented using Boolean circuits, where

• Example: half- adder, full-adder, encoder, decoder.

characteristics of combinational circuits

• The combinational circuit does not use any memory.

• The output of combinational logic circuit depends only on the current

• A combinational circuit can have n number of inputs and m number of

• HALF ADDER (DEFINITION):

• A circuit that computes the addition of two bits

• HALF ADDER (BLOCK DIAGRAM)

HALF ADDER (TRUTH TABLE)

HALF ADDER (LOGIC CIRCUIT)

• HALF ADDER (Expressions):

FULL Adders (Definition & Block Diagram)

• FULL Adders Definition: A full - adder is a combinational circuit that

• FULL Adders BLOCK DIAGRAM

FULL ADDER (TRUTH TABLE)

FULL ADDER (LOGIC CIRCUIT)

SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin

For the CARRY-OUT (Cout) bit:

Cout = Cin(A XOR B) OR A AND B = Cin(A ⊕ B) + A.B

Sequential Circuits: SR FLIPFLOP

Introduction to SEQUENTIAL circuits:

Clock: Importance of clock signal in sequential circuits

• Triggering: It is a process of applying clock signal ( input) to a Flip-Flop

• It is the basic memory element in a digital computer.

• SR FLIPFLOP or SET/RESET FLIP FLOP (DEFINITION):

• SR FLIPFLOP (BLOCK DIAGRAM)

SR FLIPFLOP (TRUTH TABLE)

SR FLIPFLOP (LOGIC CIRCUIT)

TIMING DIAGRAM OF SR FLIPFLOP

• D FLIPFLOP or DELAY/DATA FLIP FLOP (DEFINITION):

• D FLIPFLOP (BLOCK DIAGRAM)

D FLIPFLOP (TRUTH TABLE)

D FLIPFLOP (LOGIC CIRCUIT)

TIMING DIAGRAM OF D FLIPFLOP

• JK FLIPFLOP or JACK/KILBY FLIP FLOP (DEFINITION):

• JK FLIPFLOP (BLOCK DIAGRAM)

JK FLIPFLOP (TRUTH TABLE)

JK FLIPFLOP (LOGIC CIRCUIT)

• T FLIPFLOP or TOGGLE FLIP FLOP (DEFINITION):

• T FLIPFLOP (BLOCK DIAGRAM)

T FLIPFLOP (TRUTH TABLE)