A 10 mW Inductorless, Broadband CMOS Low Noise Amplifier
for 900 MHz Wireless Communications
Johan Janssens, Jan Crols and Michiel Steyaert
K.U.Leuven, ESAT-MICAS,
Kardinaal Mercierlaan 94, B-3001 Heverlee, Belgium
Abstract
A low-power, broadband LNA has been integrated in a
standard 0.5 p m CMOS process. The presented CMOS LNA
offers a noise figure better than 3.3 dB up to 970 MHz while
drawing only 3.4 mA from a 3.0 Volt supply. The circuit
employs a topology without on-chip inductors and does not
require any tuning or trimming to achieve the performance.
The amplifier provides a gain of 14.8 dB in a 700 MHz
wide band and has a gain of 9 dB at 900 MHz. The input IP3
is -4.7 dBm. The reverse isolation is higher than 41 dB,
making it fit for insertion in a CMOS low-IF receiver.
Introduction
Present wireless communication systems extensively use
digital signal processing to create high-quality links. Whereas
today’s CMOS technologies allow for a low-cost integration
of these complex digital functions on a single die, the RF
front-end is typically still being implemented in bipolar or
BiCMOS technologies for low-power reasons. Nowadays, the
viability of full-CMOS implementations is being explored
[ 1,2,3], ultimately aiming at single-technology or even single-
chip integration. As the LNA is a critical part of the receiver
channel regarding both noise figure and overload
performance (IP3), it poses a challenge to meet this
performance also in CMOS while combining it with a low
power dissipation.
In this work a low-noise amplifier for 900 MHz CMOS
wireless receivers is presented which can compete with
existing bipolar realizations [6,7] and which has a
significantly lower power consumption than previously
published CMOS low-noise amplifiers for this frequency
range [ 1,2,3,8,9,10,11]. The low power consumption is
achieved by exploiting a current-reuse technique in an all-
nMOS, open-loop configuration. Before discussing the
proposed LNA topology and the measurement results, some
considerations on the integration of wireless receiver front-
ends in CMOS are given.
High Integration CMOS Receivers
When the classical heterodyne receiver architectures are
directly mapped onto a CMOS implementation, they tend to
be more power hungry than their bipolar equivalent. The
excess power dissipation originates - apart from CMOS
frequency limitations - from the intrinsically lower driving
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efficiency of MOS transistors ( g d Z ) when compared to
bipolar transistors. These receiver architectures require a lot
of external filters which need to be driven at a low impedance
level. The high-Q filters are necessary siince they perform the
image rejection (mirror signal suppression) and the channel
selection in this topology. The integration of these filters is
however difficult. Consequently, the large number of off-chip
components makes this architecture not well-suited for
building highly integrated receivers.
By using new receiver architectures, like the low-IF [ 5 ] or
wideband-IF receiver, the number of external nodes to be
driven can be kept to a minimum, resulting in a significant
reduction of the power consumption. The degree of
integration can also be much higher in these topologies, as
there is in principle no need for external filters; The image
rejection is performed using a quadrature demodulation
scheme while the channel selection is done by a simple low-
pass filter.
In a real circuit implementation, of course, some filtering
is needed because of the linearity constraints and the limited
output swing of practical building blocks. In practice, an HF
filter suppresses the out-of-band blocking signals to relax the
dynamic range requirements. The use of a bandpass filter
between the LNA and the downconversion mixer is however
not necessary when a sufficiently linear LNA and a non-
switching mixer are used; A bandpass filter suppresses the
second and third order harmonics of the R F signal which are
generated within the LNA due to a limited linearity. A
switching mixer would mix these harmonics down to the
wanted signal frequency.
In contrast with bipolar technology, a CMOS technology
has the advantage that it allows for the realization of highly
linear mixers [4] based on transistors in the linear region. To
complete the reception path, a power-efficient CMOS low-
noise amplifier with a good linearity and sufficient reverse
isolation is required.
LNA Topology
In low-power LNA designs typically inductors are utilized
to form a relatively high-Q LC-load, tuned to the working
frequency. The performance of integrated inductors in CMOS
technologies however heavily depends on the substrate
doping level: the higher the resistivity of the substrate, the
better the quality of the inductor. Yet, as typically a low-
ohmic, highly doped substrate is used - mainly for its
75
IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE
resistance to latch-up in digital CMOS circuits - eddy
currents in the substrate significantly degrade the
performance of the inductor. In this paper the possibilities of
inductorless, broadband designs are explored, i.e., without
using accurately tuned, high-Q LC tanks defining the
amplification. In other words, the circuit does not exploit
‘overdrive’ capabilities provided by on-chip inductors.
Figure 1 shows the schematic of the low noise amplifier.
The amplifier consists of a cascade of three, all-nMOS gain
stages, formed by M l x , M2x and M3x.
A multi-stage topology is employed to ensure the critical
reverse isolation when the circuit is used in a low-IF or zero-
IF receiver. In these receiver topologies, the local oscillator
frequency and the wanted signal frequency are very close to
each other or even the same. At all cost, leakage to the
antenna of the large-amplitude LO signal that is driving the
succeeding mixer stages needs to be prevented, because this
results in corruption of the wanted signal. As precisely these
topologies are most suited to build highly integrated
receivers, ensuring a sufficiently large reverse isolation has
been an important design goal.
A current-reuse technique is applied to reduce the LNA
power consumption; Gain stages M I X and M2x consist of
three, respectively two, nMOS gain blocks that are stacked
on top of each other in the same current branch. In this way
current is saved when generating transconductance, while the
available voltage headroom is used more effectively. In the
case of the input-stage this results in an almost 3 times higher
effective gm for the same current. Large on-chip decoupling
capacitors provide stable intermediate nodes between the
stacked gain blocks and isolate them from each other at high
frequencies. Consequently, the gain blocks are activated
above gm/2r~C,generating a -3dB point near 50 MHz in the
forward characteristic.
Each gain block is loaded with polysilicon resistors Rx
such that the gain is inherently broadband and locally well-
defined. The output nodes of each gain block are combined
Figure 1: LNA circuit diagram.
5.4.2
76
with capacitors Cc2 to form one effective signal node at radio
frequencies. Because a fixed fraction of the capacitance
(-1/10)acts as a parasitic to the substrate, a trade-off is
necessary between signal transfer and loading of the
preceding stage. In practice, Cc2 is limited to about 1 or
2 pF.
To ensure sufficient linearity, the last two stages are
degenerated by polysilicon strips Rdx, lowering the effective
voltage excursion at the gates. It is important to notice that
due to the intrinsically better linearity of a CMOS device
compared to bipolar transistors, an open-loop structure can
be used for the input stage. In this way, the extra noise
generated by the feedback system is avoided. Each stage is
designed to give an equal contribution to IP3.
The output buffer is a degenerated cascode amplifier.
Cascode transistor M4 shields the LNA output from the drain
parasitics of M31, at the same time providing a low
impedance to these capacitances and ensuring extra reverse
isolation. To optimize the total bandwidth, the size of M4 is
about half the size of M3 1.
Each stage’s biasing current is determined by current
mirror M5. Part of the transistors in the signal path are DC-
biased by means of high-ohmic polysilicon resistors
connected to their gates. The transistor sizes, element values
and biasing information are summarized in table 1.
Table 1: Operating point information
 The LNA input is capacitively coupled internally, Source-Load Amplification (VouWin) and IReverse Gain (512)
simplifying matching [3] if considered necessary. The
performance of the LNA reported here is achieved without
adding these external, tuned impedance transforming
networks. If impedance matching is done at the input, a larger
bandwidth and a higher gain can be achieved at the cost of a
higher frequency selectivity [3].
In this topology, combining low-noise operation with a
low power consumption requires the use of a low Vgs-VT-
value (-0.2 Volt), allowing a high gm at low current levels.
Yet, as low Vgs-VT-values mean wide transistors, the input
bandwidth tends to decrease, eventually degrading the high-
frequency noise figure. In order to counteract the noise figure
increase caused by input bandwidth limitations, the series
inductance of the bondwire can be employed to generate a
low-Q second-order boosting section at the amplifier’s input.
The low quality-factor is ensured by the 50 ohm source

,
impedance, making it robust with respect to variations in total 1 o8 1 ti”
package inductance. Even though the net quality-factor is Frequency [Hz]
low, the second-order section can change an input loss of Figure 2: Gain and reverse gain.
3 dB in a gain of 1 dB, extending the frequency band of low-
noise operation. 5, , , \NANoi? Figurf , ,
The LNA is designed to drive the capacitive input
impedance of two (I&Q) ultra-linear downconversion mixers 45
(similar to [ 4 ] )in a low-IF receiver topology. Because this
mixer can handle the blocking levels and because the image
rejection is performed by the quadrature demodulation, no
3.51 A
intermediate filtering is required between the LNA and the
downconverters. Hence it is not necessary to lower the output
impedance to 50 ohm because the mixers can be on-chip,
having their gates directly connected to the LNA. In order to
correctly evaluate the LNA performance, a bonding pad with
an identical parasitic capacitance (350fF) is used.

Realization and Experimental Results 0‘ , - 4

700 750 800 850 900 950 1000 1050 1100

A bare LNA die is mounted on a ceramic thin-film Frequency [MHz]

substrate and wire bonded from the pads to 50 ohm striplines.
The full S-parameter set with respect to the reference planes
is measured from 100 MHz to 3 GHz and converted to the
forward voltage gain VoutNin. Figure2 shows both the
forward and the reverse gain of the LNA. The amplifier
provides a forward gain of 14.8 dB in a 31d order intermodulation products for i i two-tone test around
-3dB band ranging from below 100 MHz (near 50 MHz) up
to 700 MHz. At 900 MHz, the gain is 9 dB. The reverse
isolation is better than 41 dB over the full measuring range,
making the amplifier well suited for low-IF applications.
The noise density is measured by connecting a commercial
low noise amplifier to the LNA output. Noise figure data is
extracted continuously from 700 MHz up to 1.1 GHz by
referring the measured spectrum to the input, using the S -
parameters of the full noise-measurement setup. The resulting
noise figure plot is shown in figure 3. The LNA noise figure
remains between 2.3 dB and 3.3 dB up to a frequency of
970 MHz.
Figure 3: Noise figure.
The input-referred IP3 is extracted by applying two
closely spaced tones at the LNA input and sweeping their
power levels. Figure.4 shows the fundamental tones and the
700MHz. The two curves extrapolate to an IIP3 of
-4.7 Vc!Bm (VdBm being defined as the voltage that
corresponds with a power level of 0 dBm in 50 ohm).
A microphotograph of the 0.5 p m IC is shown in figure 5.
The total die area is 1.0 x 1.2 mm2, the largest part of it being
occupied by the decoupling capacitors. The active core only
occupies an area of 0 . 4 x 0 . 3 mm2. The total power
consumption is only 10 mW for a power supply of 3.0 Volt.
The measured performance of the LNA is summarized in
table 2.

5.4.3
77
 Input-Referred 3rd Order Intercept Point
Conclusion 101 /I

A low-power CMOS LNA for 900MHz wireless

0
applications has been presented. The noise figure is lower
than 3.3 dB up to 970 MHz while consuming only 10 mW. -1 0
Yet, the circuit employs a broadband topology that does not
rely on accurately tuned LC-tanks using integrated inductors. -20
The low power consumption has been achieved by
exploiting a current-reuse technique in an open-loop all-
nMOS configuration. As a result, the presented CMOS low-
noise amplifier can compete with existing bipolar realizations
[6,7] and has a significantly lower power consumption than
previously published CMOS low-noise amplifiers for this
frequency range [1,2,3,8,9,10,11].

References
[I] S. Sheng et al., “A Low-Power CMOS Chipset for Spread-Spectrum
Communications,” Proc. ISSCC, pp. 346-347, San Francisco, Feb. 1996.
[2] B. Razavi, “A 900-MHz CMOS Direct Conversion Receiver,” Digest of
Technical Papers, 1997 Symposium on VLSI circuits, pp. 113-1 14, Kyoto,
June 1997. -3”
-35 -30 -25 -20 -15 -10 -5 (
[3] A. N. Karanicolas, “A 2.7V 900MHz CMOS LNA and Mixer,’’ Proc. Vin [VdBm]
ISSCC, pp.50-51, San Francisco, Feb. 1996.
[4] J. Crols and M. Steyaert, “A 1.5 GHz highly linear CMOS Figure 4: 3rdorder intermodulation performance.
downconversion mixer,” in IEEE J. Solid-state Circuits, vo1.30, 110.7,
pp.736-742, July 1995.
[SI J. Crols and M. Steyaert, “Low-IF Topologies for High Performance
Analog Front-Ends of Fully Integrated Receivers,” accepted for
publication in IEEE Trans. on Circuits and Systems 11, 1997.
[6] K. Irie et al., “A 2.7 V GSM Transceiver IC,” Proc. ISSCC, pp. 302-303,
San Francisco, Feb. 1997.
[7] R.G. Meyer and W.D. Mack, “A lGHz BiCMOS RF Front-End IC,”
IEEE J. Solid-state Circuits, ~01.29,No. 3, pp.350-355, Mar. 1994.
[8] A. Rofougaran et al., “A 1 GHz CMOS RF Front-End IC with Wide
Dynamic Range,” Proc. ESSCIRC, Lille, pp.250-253, Sept. 1995.
[9] D. Shaeffer and T. Lee, “A 1.5 V, 1.5 GHz CMOS Low Noise
Amplifier,” Proc. V U 1 Circuits Symposium, Honolulu, pp.32-33, June
1996.
[lo] Y.J. Shin and K. Bult ,“An Inductorless 900 MHz RF Low-Noise
Amplifier in 0.9um CMOS,” Proc. CICC, $anta Clara, pp.513-516, May
1997.
[ l l ] J. Janssens, M. Steyaert and H. Miyakawa, “A 2.7 Volt CMOS
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Symposium on VLSI circuits,” pp.87-88, Kyoto, June 1997.

Table 2: LNA performance summary.

Parameter I Value
supply ”ohage 1 3.0 Volt
Figure 5: LNA microphotograph.
Power dissioation I 10 mW
-3dB band 50 - 700 MHz
Noise figure 2.3 - 3.3 dB
In-band gain 14.8 dB

Input IP3 I -4.7 VdBm

Die area 1 1.0x1.2mm*
Technology 0.5 l m CMOS
low-ohmic substrate

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