1

Scalable Model for the Intrinsic Inductance of

Octagonal Inductors in RFCMOS
José Valdés-Rayón, Student Member, IEEE, Reydezel Torres-Torres, Senior Member, IEEE, Roberto
S. Murphy-Arteaga, Senior Member, IEEE
Abstract—The intrinsic inductance of on-silicon inductors is
accurately represented using a model that considers the size of the
device as well as its distance from the ground shield. The model
accounts for the current path along the turns forming the device
and that associated with the return path. Improvement of more
than 10% in the accuracy of the predicted intrinsic inductance is
achieved when comparing the results with those obtained using
previously reported approaches.

Index Terms—inductor, S-parameters, ground shield.

I. INTRODUCTION
When working with inductors, the intrinsic inductance is the
main figure of merit specified for device and circuit designers
since it provides insight about its geometry and the requirement
Fig. 1. Micrograph showing the fabricated octagonal inductors with different
for space. Thus, several approaches have been proposed to
apothem; the dummy structures for pad de-embedding are also shown.
estimate this parameter. However, the effect of the ground
shield that isolates the device from the substrate and allows to
define a scalable model [1] is commonly ignored. In this regard,
the importance of a scalable circuit model for inductors relies
on the fact that the assessment of the Q-factor and the overall
inductor performance considering different geometrical
parameters (e.g., number of turns, size, track width and spacing)
is needed before prototyping [2]. For the case of spiral
inductors, the intrinsic inductance is assumed to be the one
associated with the area enclosed by the turns (Ltop) [3],[4],
neglecting the side inductance (Lside) corresponding to the loop
Fig. 2. Sketch detailing the dimensions used for the fabricated inductors.
formed by the turns and ground plane. This may yield a
significant error when modeling small inductors in advanced Fig. 2. The devices are made of copper and present a
technologies presenting multiple metal levels. Here, for the first symmetrical octagonal design with three turns n = 3, width and
time the contribution of Lside is taken into account in the thickness of the metal trace w = 7.7 μm and t = 3 μm,
characterization and modeling of spiral inductors, showing its respectively, and the spacing between adjacent turns is s = 3.5
equivalency to the inductance of a microstrip line [5]. The μm. The apothem of the outer turn for the three implemented
scalability of the resulting model is verified by achieving inductors is respectively a = 100, 150, and 200 μm. Notice also
excellent correlation with experimentally obtained data from in Fig. 1 that the inductors include coplanar pads formed with
octagonal inductors presenting different apothem for the outer aluminum, which are designed to measure S-parameters using
turn (a). Furthermore, the device parasitics are also considered, ground-signal-ground coplanar probes with a 100 μm pitch. For
allowing for the accurate simulation of the S-parameters and the this propose, a vector network analyzer setup was calibrated up
Q-factor up to several gigahertz beyond the frequency of to the probe tips by applying an off-wafer line-reflect-match
resonance for the considered inductor sizes. algorithm and an impedance standard substrate. In addition to
the inductors, the ‘open’ and ‘short’ dummy structures shown
II. PROTOTYPES AND MEASUREMENTS in Fig. 1 were included in the test chip to correct the
In order to show the development and verification of the measurements from the pad parasitics using a two step de-
proposal, a test chip was fabricated in an RFCMOS process. A embedding procedure [7]. Using the measured S-parameters, it
micrograph of the inductors fabricated in this test chip is show is possible to systematically obtain the model parameters for the
in Fig 1, whereas the corresponding dimensions are detailed in inductor as explained afterwards.

Manuscript received July 15, 2015. This work was supported by CONACyT- The authors are with the Instituto Nacional de Astrofísica, Óptica y Electrónica
Mexico through Scholarship #426221. (INAOE), Department of Electronics, Tonantzintla, Puebla 72840, Mexico.
(email: jose.valdes@inaoep.mx).
 2

Fig. 3. π-model for an inductor on RFCMOS: a) using generic admittance

blocks, and b) representing the admittances using equivalent circuits.
Fig. 4. Sketch detailing the current loops associated with Ltop and Lside.

  2.26  
TABLE I

Ltop  0.535 n 2 Davg  ln    0.19  2 

VALUES FOR THE MODEL ELEMENTS FOR THE FABRICATED INDUCTORS

   
(4)

a Rs Ls Rp Cp Csi Rsi Cci
(μm) (Ω) (nH) (Ω) (fF) (pF) (Ω) (fF)
100 2.58 2.69 14.5 32.90 0.25 1343.7 26.10
where μ is the relative magnetic permeability, n is the number
150 3.42 4.98 22.5 54.28 0.38 938.6 36.59
of turns, Davg = 2a − (n w + (n − 1) s) is the device’s average
200 4.70 7.56 25.5 77.00 0.49 740.9 47.04
diameter, and ρ is the fill ratio that accounts for the effective
cross section from which the current is flowing. In [3], ρ is
III. EQUIVALENT CIRCUIT MODELING calculated using a formula that neglects the finite thickness of
At frequencies up to some tens of gigahertz, the wavelength the metal traces forming the turns. This assumption may yield
of signals propagating on semiconductor chips is much larger overestimation of Ltop since in practice, the distribution of the
than the dimensions of the inductors typically used in current in the whole section of the trace is equivalent to
RFCMOS. Thus, the appropriate modeling of these devices can considering several continuous paths in parallel, which reduces
be achieved using lumped models. Fig. 3a shows a π-model for the effective inductance. Thus, based on Grover’s formulation
[4], an alternative expression for ρ is proposed here; this is
  n w  t   n  1s  t  Davg
an inductor to allow its representation as a two-port device
using generic admittances, whereas Fig. 3b illustrates the model
(5)
when representing these admittances using equivalent circuits.
In this model, Yf includes the effect of the intrinsic inductance which allows to apply (4) for an octagonal inductor from the
(Ls) in series with the device’s parasitic resistance (Rs), and dimensions defined in Fig. 2 considering the thickness t.
considers the undesirable coupling of the input and output Now a second contribution to Ls is from the inductance
terminals using Cp and Rp. On the other hand, Yi and Yo account originated by the current loop formed between the metal trace
for the coupling to ground of the input and output terminals, defining the turns and the ground shield (i.e., Lside). As can be
respectively. Since the fabricated inductors are intended to seen in Fig. 4, Lside is equivalent to the inductance presented by
present input/output symmetry, it is common to assume Yi ≈ Yo. this metal trace when analyzed as a straight microstrip line with
Nonetheless, some differences in these admittances are possible length equal to the total length of the inductor. Thus, Lside can
due to tolerances in the fabrication process. Thus, even though be calculated using the formula for microstrip [5]:
 2 h 
Yi and Yo are modeled using the same circuit topology, different
Lside  Ptotal k ms ln  
wt 
values can be obtained for the corresponding capacitances and (6)
resistances in each case.
Once S-parameters corresponding to the different inductors
are available, these data are transformed to Y-parameters so that where kms = 200 nH/m is an empirical constant, h is the distance
Yi = Y11 + Y12, Yo = Y22 + Y12, and Yf = –Y12 are determined. from the metal trace to the ground shield, and Ptotal is the length
of the of the spiral inductor, which is obtained from:

Afterwards, the analytical parameter extraction described in [6]
was used to obtain the parameters in the model shown in Fig. 3.
The corresponding results are listed in Table I, where only
values for the elements in Yi are shown since those associated
with Yo present close values.
At this point, the intrinsic inductance as a function of the
apothem is known for the fabricated inductors. This allows the
verification of the model for Ls described afterwards.
IV. SCALABLE MODEL FOR THE INTRINSIC INDUCTANCE
It is a common design practice to assume that Ls in the model
of Fig. 3 can be directly calculated considering only the
equivalent area surrounded by the inductor turns (i.e., Ls ≈ Ltop).
In this case, for an octogonal spiral inductor the following
expression is used [3]:
Ptotal  k p  2a  i w  (i  1) s 
n
(7)
i 1
In (7), kp = η tan(π/η); hence, since η is the number of sides for
a regular polygon geometry, kp = 3.3137 for the octagonal
inductors considered here. Finally, Ls can be calculated from:
Ls  Ltop  Lside
(8)
which allows the accurate determination of the inductor’s
intrinsic inductance from geometry and material properties.
V. RESULTS AND DISCUSSION
Fig. 5 shows the intrinsic inductance obtained experimentally
as described in Section III for the three considered inductors. In
 3

8 18
experimentally determined Ls 20 Experiment
7 17
model: Ls = Ltop + Lside 10 Model
Inductance (nH)

0 am
6 16
5 15

% Lside
-10 fr =17 GHz
4 14
3 Ltop 13 20

Q-Factor
2 12 10
0 am
Lside
1 11
0 10 -10 fr = 9.7 GHz

a (m)
100 150 200
20
10

am
Fig. 5. Comparison between experimental data and calculations using the
0
proposed equations for the intrinsic inductance. The dashed curve shows the fr = 6.6 GHz
contribution of Lside to the total intrinsic inductance. -10
0.0 0.5 1.0 1.5
0
/
f fr
S11
-30 Measured data Fig. 8. Model-experiment correlation for the Quality factor.
Model S12
-60
a m fr = 17 GHz
inductor. Thus, when using this equation in conjunction with
-90
the improved formula proposed here to calculate the inductance
|S11|, |S12| (dB)

0
associated with the inductor turns, excellent model-experiment
-30 S11
correlation is achieved for devices presenting different
-60 S12
geometries and beyond the corresponding self-resonance
-90 a m fr = 9.7 GHz
frequency.
0
-30 S11
ACKNOWLEDGMENT
-60 S12

a m
-90
0.0 0.5
f fr/
Fig. 6. Model-experiment correlation for the S-parameters of the inductors.
this figure, the proposed model considering Ltop and Lside
accurately represents the experimental data. Notice that the
effect of Lside becomes more significant as the inductor is scaled
down, which is due to the fact that as the device shrinks, the
effective area enclosed by the turns decreases in a more
accentuated way than the side area associated with the metal
trace when analyzed as a microstrip. In fact, when reducing the
size of an inductor formed at a certain metal level, Lside would
eventually surpass Ltop. For the studied devices, Fig. 5 shows
that the contribution of Lside increases from about 12% to 17%
when the apothem is reduced from 200 μm to 100 μm.
Fig. 6 shows the excellent agreement between the model and
the measured S-parameters. In this case, the intrinsic inductance
was calculated using (8) and the proposed equations for Ltop and
Lside. This model shows accuracy several gigahertz beyond the
self-resonance frequency (fr) corresponding to each inductor,
demonstrating its applicability within the useful band of
operation for these devices. Furthermore, when calculating the
quality factor (Q) as in [2] from simulations using the proposed
model, excellent correlation is observed when comparing the
corresponding curves with those associated with experimental
data.
fr = 6.6 GHz The authors thank IMEC for supplying the test structures.
1.0 1.5
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VI. CONCLUSIONS
The significant geometry-dependent contribution of the side-
inductance of on-chip inductors to the total intrinsic inductance
is demonstrated. The corresponding effect is accurately
considered by using a simple and analytical equation that
involves the total length of the metal trace that forms the