Logic Circuit Design

Assoc. Prof. Dr. Ahmet Turan Ozdemir

Erciyes University
Faculty of Engineering
Department of Electronic Engineering

Logic Circuit Design

Erciyes University
 These slides were developed with the aid of examples found in:
– “Logic and Computer Design Fundamentals” - M. Morris Mano and
Charles R. Kime
– “Digital Design: Principles and Practices” - John Wakerly

PowerPoint files can be found at

www.aturan.com

Logic Circuit Design

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 Outline

♦ Registers
– Shift Registers
– Applications

♦ Designing with Registers

– ASM Charts

♦ Programmable Logic Devices

– VLSI Design
– PLDs
– ROM

♦ Random Access Memory

– SRAM
– DRAM
– Organization and Timing

Logic Circuit Design

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 Introduction

♦ Practical synchronous sequential circuits are too complex to design at the flip-
flop level.
• For example, strictly speaking, a PC with only 16 Mbytes of main
memory is a sequential circuit with well over 2128,000,000 states.
K (kilo) 210 1024
M (mega) 220 1048576
G (giga) 230 1.07 x 109
T (tera) 240 1.10 x 1012

♦ Practical sequential designs, like combinational designs, require a

hierarchical approach
– Common function blocks: registers and counters
– These devices are commonly available as MSI modules

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 Decomposing a Design: Control and Data

♦ Control Signals - signals that activate data-processing functions.

– To activate a sequence of such operations, the control unit sends the proper
sequence of control signals to the datapath.

♦ Status Signals - signals that describe aspects of the state of the datapath.
– The control unit uses these signals in determining the specific sequence of
operations to be performed.

♦ Other Signals - allow the control unit and datapath to interact with other
parts of the system, such as memory and input-output logic.
Logic Circuit Design
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 MSI Quad/Hex Registers

All four flip -flops use the same clock!

Logic Circuit Design
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Octal Register with Parallel Load Enable

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 Shift Registers
Multi-bit register that moves data “sideways” left/right ( 1 bit/clock )
– Shift Left (or Shift Down) is towards MSB

– Shift Right (or Shift Up) is towards LSB

Logic Circuit Design

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Serial In, Serial Out (SISO) Shift Register

Logic Circuit Design

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Serial In, Parallel Out (SIPO) Shift register

Logic Circuit Design

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Parallel In, Serial Out (PISO) Shift Register

Logic Circuit Design

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Parallel In, Parallel Out (PIPO) Shift Register

Logic Circuit Design

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Bi - directional Universal Shift Registers

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Universal SR Schematic

Logic Circuit Design

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 Shift Register Applications
♦ State Registers
– Shift registers are often used as the state register in a sequential device.
Usually, the next state is determined by shifting right and inserting
a primary input or output into the next position (i.e. a finite memory machine)
– Very effective for sequence detectors

♦ Serial Interconnection of Systems

– keep interconnection cost low with serial interconnect
♦ Bit Serial Operations
– Bit serial operations can be performed quickly through device iteration
– Iteration (a purely combinational approach) is expensive (in terms of # of
transistors, chip area, power, etc).
– A sequential approach allows the reuse of combinational functional units
throughout the multi-cycle operation

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Shift Register Applications

Logic Circuit Design

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Shift Register Applications
Serial Binary Adder

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Octal Tri-state Register/Latch

Logic Circuit Design

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Programmable Logic Devices
– VLSI Design
– PLDs
– ROM

Logic Circuit Design

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 Programmable Logic Definitions

✓ Digital integrated circuit (MSI, LSI, VLSI)

– manufactured as a standard off-the-shelf component
– containing “regular” array of logic gates and flip-flops
– whose logic functions are determined by the application design engineer
and implemented locally

✓ Many types of programmable logic

– sometimes generically called PLDs (Programmable Logic Devices)
– PAL or PLD
– PROM
– FPGA

Logic Circuit Design

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 Programmable Logic Definitions

✓ PLA
– Programmable Logic Array
– first PLDs
– simple programmable
AND/OR array
– programmed by “blowing
fuses” by hand or by mask

Logic Circuit Design

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 Programmable Logic
✓ PAL
– Programmable Array Logic
– similar to a PLA, but the OR array
is fixed
– most commonly used PLD
– may include input/output flipflops

✓ GAL
– Generic Array Logic
– can be configured to emulate
the AND/OR, flip-flop, and
output structure of a variety of
combinational and sequential
PAL devices

Logic Circuit Design

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 Read - Only Memory (ROM)
➢ A combinational circuit with n inputs and b outputs:

➢ Programmable values determined by user

➢ Nonvolatile contents retained without
power
➢Uniform (Random) Access delay is uniform
for all addresses

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 Read - Only Memory (ROM)

✓ Two views:
– ROM stores 2n words of b bits each, or
– ROM stores an n-input, b-output truth table

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 Using ROMs for Combinational Logic
A 3-input, 4-output combinational logic function:

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Equivalent Decoder in Discrete Logic

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 Internal Structure of 4 X 4 Diode ROM

Why use diodes?

Why not replace them with wires?

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 Types of ROMs (1)

✓ Mask ROM
– Connections made by the semiconductor
vendor
– Expensive setup cost
– Several weeks for delivery
– High volume only
– Bipolar or MOS technology

✓ PROM
– Programmable ROM
– Connections made by equipment manufacturer
– Vaporize (blow) fusible links with PROM programmer using
high voltage/current pulses
– Bipolar technology
– One-time programmable

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 Internal Structure of Transistor ROM

✓ Replace diodes with MOS transistors

✓ Change decoder to active-high outputs

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EPROM and EEPROM Structure

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 Types of ROMs (2)
✓ EPROM
– Erasable Programmable ROM
– Charge trapped on extra “floating gate” of MOS
transistors
– Exposure to UV light removes charge
➢ 10-20 minutes
➢ Quartz Lid = expensive package
– Limited number of erasures (10-100)

✓ EEPROM (E2ROM)
– Electrically Erasable ROM
– Floating gates charged/discharged electrically
– Not RAM! (relatively slow charge/discharge)
– limited number of charge/discharge cycles (10,000)

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 Types of ROMs (3)

✓ Flash Memory
– Electronically erasable in blocks
– 100,000 erase cycles
– Simpler and denser than EEPROM
– Often used for firmware

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ROM Type Summary

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 Consider a 64 x 1 ROM

This Decoder needs 64 6-input gates!

Very tall, narrow chip (BAD) How can we make it more square?
Even worse for larger chips!

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 64 x 1 ROM with 2 - Dimensional Decoding

Decoder and mux = 8 3-input gates + 8 4-input gates

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Internal 2n x b ROM Control Structure

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 Programmable Logic
✓ Advantages
– Design flexibility
– Better design automation
– Higher density, fewer packages (compared to SSI-MSI)
– Less expensive
– Lower power
– Higher performance

✓ Programming Technologies
– Interconnections usually made by pass transistors controlled by memory bits of
some type:
– Antifuse - permanent connections made electrically
– EPROM - charged floating gate, UV erasable
– EEPROM - charged floating gate, electrically erasable
– Flash Memory - charged floating gate, electrically erasable
– Programmed using CAD - Hardware Description Languages

Logic Circuit Design

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