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ADE UNIT 2 - xcvbgfre

Object Oriented Design And Programming (SRM Institute of Science and Technology)

Studocu is not sponsored or endorsed by any college or university

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UNIT-2nd

Transistor as a Switch:-
A transistor works in active region when worked as an Amplifier. When a transistor works as a Switch it
works in Cutoff and Saturation Regions. In the Cutoff State both Emitter Base Junction and Collector Base
junctions are reverse biased. But in saturation region both junctions are forward biased. Switch is a very
useful and important application of transistors. In most digital IC’s transistors will work as a switch to
make power consumption very low. It is also a very useful circuit for an electronics hobbyist as it can
be used as a driver, inverter etc.

Circuti Diagram

From the above circuit we can see that the control input Vin is given to base through a current
limiting resistor Rb and Rc is the collector resistor which limits the current through the transistor. In
most cases output is taken from collector but in some cases load is connected in the place of Rc.

 ON = Saturation

 OFF = Cutoff

Transistor will become ON ( saturation ) when a sufficient voltage V is given to input. During this
condition the Collector Emitter voltage Vce will be approximately equal to zero, ie the transistor acts
as a short circuit. For a silicon transistor it is equal to 0.3v. Thus collector current Ic = Vcc/Rc will
flows.

Transistor will be in OFF ( cutoff ) when the input Vin equal to zero. During this state transistor acts
as an open circuit and thus the entire voltage Vcc will be available at collector.

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Characteristics of Digital ICs:-

1. Fan out
2. Power dissipation
3. Propagation Delay
4. Noise Margin
5. Fan In
6. Operating temperature
7. Power supply requirements

1. Fan-out

Fan out specifies the number of standard loads that the output of the gate can drive without
impairment of its normal operation
2. power dissipation

Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.
3. propagation delay

Propagation delay is the average transition delay time for the signal to propagate from input to output
when the signals change in value. It is expressed in ns.
4. Noise margin

It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an
undesirable change in the circuit output. It is expressed in volts.
5. Fan in

Fan in is the number of inputs connected to the gate without any degradation in the voltage level.

6. Operating temperature

All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which
the performance of the IC is effective is called as operating temperature. Operating temperature of the
IC vary from 00 C to 700 c.

Digital Logic Families:-

1. Diode Logic (DL):-

In DL (diode logic), only Diode and Resistors are used for implementing a particular Logic.
Remember that the Diode conducts only when it is Forward Biased.

Disadvantages of Diode Logic

Diode Logic suffers from voltage degradation from one stage to the next.
Diode Logic only permits OR and AND functions.

2. Resistor Transistor Logic (RTL):-

In RTL (resistor transistor logic), all the logic are implemented using resistors and transistors. One

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basic thing about the transistor (NPN), is that HIGH at input causes output to be LOW (i.e. like a
inverter). In the case of PNP transistor, the LOW at input causes output to be HIGH.

The resistor-transistor logic, also termed as RTL, was most popular kind of logic before the invention
of IC fabrication technologies. As its name suggests, RTL circuits mainly consists of resistors and
transistors that comprises RTL devices. The basic RTL device is a NOR gate, shown in figure aside.
Inputs to the NOR gate shown above are ‘input1’ & ‘input2’. The inputs applied at these terminals
represent either logic level HIGH (1) or LOW (0).
The logic level LOW is the voltage that drives corresponding transistor in cut-off region, while logic
level HIGH drives it into saturation region. If both the inputs are LOW, then both the transistors are
in cut-off i.e. they are turned-off. Thus, voltage Vcc appears at output I.e. HIGH.
If either transistor or both of them are applied HIGH input, the voltage Vcc drops across Rc
and output is LOW. RTL family is characterized by poor noise margin, poor fan-out capability, low
speed and high power dissipation. Due to these undesirable characteristics, this family is now
obsolete.

Advantage:

 Less number of Transistors

Disadvantage:

 High Power Dissipation

 Low Fan In

3. Diode Transistor Logic (DTL):-

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In DTL (Diode transistor logic), all the logic is implemented using diodes and transistors

The diode-transistor logic, also termed as DTL, replaced RTL family because of greater fan-out
capability and more noise margin. As its name suggests, DTL circuits mainly consists of diodes and
transistors that comprises DTL devices. Three inputs to the gate are applied through three diodes viz.
D1, D2. The diode will conduct only when corresponding input is LOW. If any of the diode is
conducting i.e. when at least one input is LOW, the voltage at cathode of didoe DA is such that it
keeps transistor T in cut-off and subsequently, output of transistor is HIGH.
If all inputs are HIGH, all diodes are non-conducting, transistor T is in saturation, and its output is
LOW. Due to number of diodes used in this circuit, the speed of the circuit is significantly low.
Hence this family of logic gates is modified to transistor-transistor logic i.e. TTL family.

Disadvantage:
Large Propagation Delay

4. Transistor Transistor Logic (TTL):-

In Transistor Transistor logic or just TTL, logic gates are built only around transistors.
TTL family is a modification to the DTL. It has come to existence so as to overcome the speed
limitations of DTL family. The basic gate of this family is TTL NAND gate.

Modifications to DTL NAND-

1. The diodes D1, D2 and D3 are replaced by emitter-base junctions of a multiple-emitter

transistor labeled T1.

2. Diode DA is replaced by collector-base junction of T1.

3. Diode DB is replaced by emitter-base junction of transistor labeled T2.

The working of this circuit is identical to that of DTL circuit.

Case1- When at least one input is logic LOW, transistor T2 and T3 are in cut-off and
hence, output of T3 is HIGH.

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Case2- When all inputs are HIGH, T1 operates in active inverse mode, driving T2 & T3 in
saturation. Since T3 is ON, the output is LOW.

Case3- While all inputs are HIGH, if any of the inputs suddenly goes LOW, then T2 and T3 will be
turned off only when stored base charge is removed. The collector-base junction of T1 is back-biased
and T1 operates in normal active region. A large collector current of T1 is in such direction that it
helps removing base charge of T2 and T3. In this way, the circuit speed is increased in TTL over
speed of DTL

Fig: TTL NAND Logic

5. Emitter Coupled Logic (ECL):-

ECL logic family implements the gates in differential amplifier configuration in which transistors are
never driven in the saturation region thereby improving the speed of circuit to a great extent. The
ECL family is fastest of all logic families. The basic gate of ECL family is NOR gate (OR and NOR
together) as shown in diagram. The output1 is NOR output while ouput2 is OR output. Transistor T1
is applied with input and additional inputs are applied to transistors (T1”, T1’’,) in parallel with T1.
Thus transistor(s) T1 and T2 are connected in differential amplifier configuration. Transistors T3 and
T4 are emitter-followers used for DC level-shifting of output voltages. The positive supply terminal
of the circuit is grounded while negative supply terminal is at negative 5.2V. This is done to minimize
the effect of noise introduced by the power supply and also to protect the gate from short-circuit that
might occur accidently.

Both the outputs (HIGH/LOW) for OR and NOR are negative. Thus, to interface this logic family
with other, a translator circuit is needed which converts negative voltages to compatible positive
voltage levels.

The basic circuit shown in figure below is a combined OR/NOR circuit and is operated from a VEE =
-5.2V supply. A built-in constant-current source provided current to the emitters. Strictly speaking,

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logic 1 is represented by -0.8V (less negative) and logic 0 by -1.7V (more negative). Please note that
it is a positive logic.

When All inputs are logical 0 i.e. -1.7V

In this case, base potential of T2 is less negative (or more positive) than the basic potential of either
T1 T1”, T1’’. Hence, T2 conducts, while T1 T1”, T1’’do not. Only enough base current is drawn by
T2 from RVS so as to remain out of saturation. The collector current of T2 develops a voltage of -
0.9V across RC2 which makes T4 to conduct. Transistor T4 gives an output voltage at the emitter of
about -0.9 -0.8 = -1.7V which represents output1 at logic 0. Since, collector potentials of T1, T1’ and
T1’’ are nearly zero (because they are cut off), the output voltage at the emitter of T3 is 0-0.8 = -
.0.8V (ie. Output2 is 1) which is a logic 1. Obviously, the two outputs are complements of each other.

When either input is at logical 1 i.e. -0.8V. In that case, the associated transistor (either T1, T1’ or
T1’’) is turned ON while T2 is turned OFF. The collector potentials of T1/T1’/T1’’ and T2 are
opposite of the previous case. Hence, now T4 output is at logical 1 and T3 output is at logical 0.

6. Integrated injection logic (IIL, I2L, or I2L)

Integrated injection logic (IIL, I2L, or I2L is a class of digital circuits built with multiple
collector bipolar junction transistors (BJT). When introduced it had speed comparable
to TTL yet was almost as low power as CMOS, making it ideal for use in VLSI (and
larger) integrated circuits. Although the logic voltage levels are very close (High: 0.7V, Low:
0.2V), I2L has high noise immunity because it operates by current instead of voltage.
The heart of an I2L circuit is the common emitter open collector inverter. Typically, an
inverter consists of an NPN transistor with the emitter connected to ground and the base
biased with a forward current. The input is supplied to the base as either a current sink (low
logic level) or as a high-z floating condition (high logic level). The output of an inverter is at
the collector. Likewise, it is either a current sink (low logic level) or a high-z floating
condition (high logic level). Like direct-coupled transistor logic, there is no resistor between
the output (collector) of one NPN transistor and the input (base) of the following transistor.

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Fig: I2L for NOT Gate

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Metal Oxide SEMICONDUCTOR Field Effect Transistor ( MOSFET):-

The symbols and basic construction for both configurations of MOSFETs are shown below.

Depletion Type (D- Type) MOSFET OR Normally ON MOSFET

D- Type can work in two modes

It may be N-Channel

Or P- Channel

(1) Depletion Mode

(2) Enhancement Mode

(Enhancement Type) E- Type MOSFET OR Normally OFF MOSFET

E- Type can work in Enhancement Mode only.

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Basic MOSFET Structure:-

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The construction of the Metal Oxide Semiconductor FET is very different to that of the Junction FET.
Both the Depletion and Enhancement type MOSFETs use an electrical field produced by a gate
voltage to alter the flow of charge carriers, electrons for N-channel or holes for P-channel, through
the semi conductive drain-source channel. The gate electrode is placed on top of a very thin insulating
layer and there are a pair of small N-type regions just under the drain and source electrodes.

Characteristics of D-MOSFET.

Typical drain characteristics, for various levels of gate-source voltage, of an N-channel MOSFET are
shown in figure. The upper curves are for positive VGS and the lower curves are for negative VGS. The
bottom drain curve is for VGS = V GS(OFF). For a specified drain-source voltage VDS, VGS (OFF) is the
gate-source voltage at which drain current reduces to a certain specified negligibly small value, as
shown in figure. This voltage corresponds to the pinch-off voltage Vp of JFET. For VGS between
VGS (0FF) and zero, the device operates in depletion-mode while for VGS exceeding zero the device
operates in enhancement mode .These drain curves again display an ohmic region, a constant-current
source region and a cut-off region. MOSFET has two major applications: a constant current source
and a voltage variable resistor.

Transfer Characteristics of D-MOSFET

The transfer (or transconductance) characteristic for an N-channel D-MOSFET is shown in figure.
IDSS is the drain current with a shorted gate. Since the curve extends to the right of the origin, IDSS is no
longer the maximum possible drain current.
Mathematically, the curve is still part of a parabola and the same square-law relation exists as with a
JFET. In fact, the depletion-mode MOSFET has a drain current given by the same transconductance
equation as before, equation. Furthermore, it has the same equivalent circuits as a JFET. Because of

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this, the analysis of a depletion-mode MOSFET circuit is almost identical to that of a JFET circuit.
The only difference is the analysis for a positive gate, but even here the same basic formulas are used
to determine the drain current ID, gate-source voltage VGS etc.

Characteristics of an EMOSFET.
Drain characteristics of an N-channel E-MOSFET are shown in figure. The lowest curve is the
VGST curve. When VGS is lesser than VGST, ID is approximately zero. When VGS is greater than VGST, the
device turns- on and the drain current ID is controlled by the gate voltage. The characteristic curves
have almost vertical and almost horizontal parts. The almost vertical components of the curves
correspond to the ohmic region, and the horizontal components correspond to the constant current
region. Thus E-MOSFET can be operated in either of these regions i.e. it can be used as a variable-
voltage resistor (WR) or as a constant current source.

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The following are modes of MOSFET as a capacitor:

(1) Accumulation ( Vgs < 0 v)

(2) Depletion (0< Vgs< Vt) (Vt= Threshold Voltage)

(3) Inversion Region (Vgs > Vt).

MOS Logic family:-

MOS logic family implements the logic gates using MOSFET devices. MOSFETs are high density
devices which can easily and economically fabricated on ICs. MOS logic gates can be fabricated
using either only NMOS or only PMOS devices. MOS logic is vastly used in LSI and VLSI devices,
such as microprocessor chips, due to their high density characteristic.

NMOS NOR gate is shown in figure. (2-input NOR gate)

If both transistors T1 and T2 are off i.e. A = B = LOW, then output is HIGH = VDD.

If either of the inputs is HIGH, then corresponding transistor(s) is/are ON, thus connecting output to
GND i.e. LOW.

CMOS Logic family:-

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MOS stands for complementary-MOS, in which both p-channel and n-channel enhancement
MOSFET devices are fabricated on same chip. This causes density to be reduced and
complex fabrication process. However, CMOS devices consume negligible power and hence are
preferred over MOS devices in battery operated applications.

PMOS logic

The structure of PMOS logic can be obtained by replacing NMOS transistors in the CMOS Circuit by
a pull down resistor. Operation of a PMOS logic family can be explained by considering a PMOS
NAND gate.

Two input PMOS NAND

When logic low is applied to either A or B, the corresponding transistor will be turned ON. This
makes a direct connection between power supply and output terminal. Now the output is raised to
logic high value. In other cases output will remain at logic low (pulled down by the pull-down
resistor).

Two input PMOS NAND

NMOS logic

NMOS logic is similar to that of PMOS logic. Instead of PMOS here we use NMOS transistor along
with a pull up resistor. NMOS is preferred over PMOS and CMOS logic families because of its speed
and easiness in the manufacturing. When output is at logic low, static power dissipation is very high.
So in application requiring minimum static power dissipation, NMOS logic is replaced by CMOS
logic.

Two input NMOS NAND

A two input NMOS NAND gate has two NMOS transistor connected in series from the output to
ground terminal and a pull-up resistor from output terminal to power supply. When both inputs are at
logic high, both transistors will be ON establishing a connection between output terminal and ground.

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Thus output is pulled down to ground voltage. When any one the input is at logic high then the
transistor will be OFF, cutting off the path between output terminal and ground. Thus output will
remain at high voltage, pulled up by the pull-up resistor.

Two input NMOS NAND

CMOS logic

Because of high noise immunity and low static power dissipation, now CMOS logic families is most
preferred in large scale integrated circuits. CMOS (Complementary Metal Oxide Semiconductor) has
complementary and symmetrical NMOS and PMOS transistors. Figure shown below is a CMOS
inverter.

Depending on the input value, only one transistor of the CMOS inverter will be ON at a time. So in
both states, there is no direct connection between power supply and ground, thereby reducing static
power loss of a transistor.

Two input CMOS NAND gate

When both inputs of a CMOS NAND gate are at high, then transistors T1, T2 will be ON and
transistors T3, T4 will be OFF. Now there is a direct connection between output and ground through
transistor T3 and T4. Output is pulled down to zero.

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When any of the input is low, either transistor T3 or T4 will be off. This breaks the connection
between output terminal and ground. At the same time, one of the PMOS transistors is ON, so there is
connection between output and power supply. Now output is pulled up to logic high.

Comparison of Logic Families:-

Propagation Delay:-
Definition: The time required for the output of a digital circuit to change states after a change at one
or more of its inputs. The speed of a digital circuit is specified in terms of the propagation delay time.
The delay times are measured between the 50 percent voltage levels of input and output waveforms.
There are two delay times, tpHL: when the output goes from the HIGH state to the LOW state
and tpLH, corresponding to the output making a transition from the LOW state to the HIGH state.
The propagation delay time of the logic gate is taken as the average of these two delay times.

Tristate Logic

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The problem with connecting multiple “normal” outputs together on a bus is that each has to be in
one logic state (0) or the other (1) - driving voltage on each bus signal high or low. This represents a
conflict over the state of the signal. We resolve this conflict with tri-state logic

The logical element has output enable pin to go from a floating output to drive the output from the
circuit. Inverters and buffers are used as bus drivers or buffers.

Tristate Buffer:

Tristate Invertor:

Applications

1. Bidirectional buffer: Two such drivers or buffers in opposite directions are used to make the
connection bi-directional. The gates also provide more “drive” onto the bus so that the bus signals are
stronger and the bus can be longer.

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FPGA Basics:-
The FPGA is Field Programmable Gate Array. It is a type of device that is widely used in electronic
circuits. FPGAs are semiconductor devices which contain programmable logic blocks and
interconnection circuits. It can be programmed or reprogrammed to the required functionality after
manufacturing.

In FPGAs, there is no processor to run the software and we are the one designing the circuit. We can
configure an FPGA as simple as an AND gate or a complex as the multi-core processor.

The FPGA stores the configuration in RAM, that is the configuration is lost when there is no power
connectivity. Hence, they must be configured every time power is supplied.

FPGA Architecture

FPGAs are prefabricated silicon chips that can be programmed electrically to implement digital
designs. The first static memory based FPGA called SRAM is used for configuring both logic and
interconnection using a stream of configuration bits.

The FPGA Architecture consists of three major components

1. Programmable Logic Blocks, which implement logic functions

2. Programmable Routing (interconnects), which implements functions

3. I/O blocks, which are used to make off-chip connections

1. Programmable Logic Blocks

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The programmable logic block provides basic computation and storage elements used in digital
systems. A basic logic element consists of programmable combinational logic, a flip-flop, and some
fast carry logic to reduce area and delay cost.

Modern FPGAs contain a heterogeneous mixture of different blocks like dedicated memory blocks,
multiplexers. Configuration memory is used throughout the logic blocks to control the specific
function of each element.

2. Programmable Routing

The programmable routing establishes a connection between logic blocks and Input/Output blocks to
complete a user-defined design unit.

It consists of multiplexers pass transistors and tri-state buffers. Pass transistors and multiplexers are
used in a logic cluster to connect the logic elements.

3. Programmable I/O

The programmable I/O pads are used to interface the logic blocks and routing architecture to the
external components. The I/O pad and the surrounding logic circuit form as an I/O cell.

These cells consume a large portion of the FPGA’s area. And the design of I/O programmable blocks
is complex, as there are great differences in the supply voltage and reference voltage.

The selection of standards is important in I/O architecture design. Supporting a large number of
standards can increase the silicon chip area required for I/O cells.

With advancement, the basic FPGA Architecture has developed through the addition of more
specialized programmable function blocks.

Introduction to HDL and logic simulation:-

 HDL is a language that describes the hardware of digital systems in a textual form.
 It resembles a programming language, but is specifically oriented to describing hardware
structures and behaviors.
 The main difference with the traditional programming languages is HDL’s representation of
extensive parallel operations whereas traditional ones represents mostly serial operations.
 The most common use of a HDL is to provide an alternative to schematics.
 When a language is used for the above purpose (i.e. to provide an alternative to schematics), it
is referred to as a structural description in which the language describes an interconnection of
components.
 Such a structural description can be used as input to logic.
 Simulation just as a schematic is used. Models for each of the primitive components are
required.
 If an HDL is used, then these models can also be written in the HDL providing a more
uniform, portable representation for simulation input.
 HDL can be used to represent logic diagrams, Boolean expressions, and other more complex
digital circuits.

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 Thus, in top down design, a very high-level description of a entire system can be precisely
specified using an HDL.
 This high-level description can then be refined and partitioned into lower-level descriptions as
a part of the design process.
 As a documentation language, HDL is used to represent and document digital systems in a
form that can be read by both humans and computers and is suitable as an exchange language
between designers.
 The language content can be stored and retrieved easily and processed by computer software
in an efficient manner.
 There are two applications of HDL processing: Simulation and Synthesis.

Logic Simulation:
 A simulator interprets the HDL description and produces a readable output, such as a timing
diagram, that predicts how the hardware will behave before it is actually fabricated.
 Simulation allows the detection of functional errors in a design without having to physically
create the circuit.
 The stimulus that tests the functionality of the design is called a test bench.
 To simulate a digital system
 Design is first described in HDL
 Verified by simulating the design and checking it with a test bench which is also
written in HDL.
 Logic simulation is a fast, accurate method of analyzing a circuit to see its waveforms

HDL System primitives:-

User Defined Primitives (UDP):
 The logic gates used in HDL descriptions with keywords and, or, etc., are defined by the
system and are referred to as system primitives.
 The user can create additional primitives by defining them as system primitives in tabular
form.
 These types of circuits are referred to as user-defined primitives.
 UDP’s do not use the keyword module. Instead they are declared with There can be only one
output and it must be listed first in the port list & the keyword primitive and declared with an
output keyword.
 There can be any number of inputs. The order in which they are listed in the input declaration
must conform to the order in which they are given values in the table that follows.
 The truth table is enclosed within the keywords table and endtable.
 The values of the inputs are listed with a colon (:). The output is always the last entry in a row
followed by a semicolon (;). It ends with the keyword end primitive.

Stimulus to the design: -

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 In order to simulate a circuit with HDL, it is necessary to apply inputs to the circuit for the
simulator to generate an output response.
 An HDL description that provides the stimulus to a design is called a test bench.
 The initial statement specifies inputs between the keyword begin and end.
 Initially ABC=000 (A,B and C are each set to 1’b0 (one binary digit end with a value 0).
 $finish is a system task.

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