REPORT ON

ELECTRONICS AND DESIGN AUTOMATION

LABORATORY
Submitted to:
P.Kotilaxmi ,
Md. Misbahuddin.
ECE Dept.
University College Of Engineering, OU.

Submitted by:
Bejugama Soumitha,
1005-18-735003,
BE VI Semester,
Electronics and Communication Engineering,
University College of Engineering,
Osmania University, Hyderabad-500007
 INDEX

s.no Name of the experiment

1 Arithmetic Units: Adder and Subtractor.

2 Encoders, Decoders, Convert BCD number into seven

segment code , Priority Encoder and Comparator

3 . 8 – Bit Full Adder using 4bit carry look ahead adder

4 Arithmetic and Logic Unit with minimum of eight

instructions.

5 . D, SR and JK Flip flops -

6 Registers/Counters
 Experiment No. 1
Arithmetic Units: Adder and subtractor
Aim: To write Verilog code for adders and subtractors in various modelling and verify
using testbench.

1.Full adder circuit using gates:

Structural Model:
module fa_str (
input a,
input b,
input cin,
output cout,
output sum
);
wire x, y, z;
xor (x, a, b);
xor (sum, x, cin);
and (y, x, cin);
and (z, a, b);
or (cout, y, z);
endmodule

RTL Schematic:
Dataflow Modelling:

module fa_daf (
input a,
input b,
input cin,
output cout,
output sum
);
assign sum=a^b^cin;
assign cout=(a&b) | cin&(a^b);
endmodule

RTL Schematic:
Behavioral Modelling:

module fa_beh (
input a,
input b,
input cin,
output reg cout,
output reg sum
);

always@ (*) begin

sum=a^b^cin;
cout=(a&b) |(b&cin) |(cin&a);
end
endmodule

RTL Schematic:
Testbench:
module fourbit_beh_tb;
reg [3:0] a;
reg [3:0] b;
reg cin;
wire cout;
wire [3:0] sum;
fourbit_beh uut (
. a(a),
. b(b),
. cin(cin),
. cout(cout),
. sum(sum)
);
initial begin
a = 0;
b = 0;
cin = 0;
#100;
a=1010; b=0101; cin=1;
#100;
a=1010; b=0101; cin=0;
 #100;
a=1100; b=0011; cin=1;
#100;
a=1111; b=1111; cin=1;
end
endmodule

Output:

2.Using half adders

module ha (
input a,
input b,
output sum,
output cout
);
assign {cout, sum} = a+b;
endmodule

//full adder instantiation

module fa_ha (
input a,
input b,
input cin,
output cout,
output sum
);
wire stemp, ctemp, ctemp1;
ha inst1(a, b, stemp, ctemp);
ha inst2(stemp, cin, sum, ctemp1);
or (cout, ctemp1, ctemp);
endmodule
RTL Schematic:

Testbench:
module fa_ha_tb;
reg a;
reg b;
reg cin;
wire cout;
wire sum;
fa_ha uut (
. a(a),
. b(b),
. cin(cin),
. cout(cout),
. sum(sum)
);
initial begin
a = 0; b = 0; cin = 0;
#100;
a = 0; b = 0; cin = 1;
#100;
a = 0; b = 1; cin = 1;
#100;
a = 1; b = 1; cin = 1;
end
endmodule
Outputs:

3. 4-bit Full Adder:

Using 1bit Full Adder:

module fourbitadder (
input [3:0] x,
input [3:0] y,
input cin,
output [3:0] s,
output cout
);
wire c0, c1, c2;
fa_ha ins1(x [0], y[0],cin,c0,s[0]);
fa_ha ins2(x[1], y[1],c0,c1, s[1]);
fa_ha ins3(x[2], y[2],c1,c2,s[2]);
fa_ha ins4(x[3], y[3],c2,cout,s[3]);
endmodule

RTL Schematic:
 Dataflow Modelling:
module fourbit_df (
input [3:0] a,
input [3:0] b,
input cin,
output cout,
output [3:0] sum
);
wire [3:0] p, g;
wire [4:0]c;
assign p=a^b;
assign g=a&b;
assign c [0] =cin;
assign c[1] =c[0]*p[0] + g[0];
assign c[2] =c[1]*p[1] + g[1];
assign c[3] =c[2]*p[2] + g[2];
assign c[4] =c[3]*p[3] + g[3];
assign sum = c[3:0]^p;
assign cout= c[4];
endmodule

RTL Schematic:
Behavioral Modelling:
module fourbit_beh (
input [3:0] a,
input [3:0] b,
input cin,
output reg cout,
output reg [3:0] sum);
reg [4:0] s;
integer i;
always@(*) begin
s [0]=cin;
for(i=0;i<=3;i=i+1) begin
sum[i]=a[i]^b[i]^s[i];
s[i+1]=(a[i]&b[i])|(b[i]&s[i])|(s[i]&a[i]);
end
cout=s[4];
end
endmodule
RTL Schematic:
Testbench:
module fourbit_beh_tb;
reg [3:0] a;
reg [3:0] b;
reg cin;
wire cout;
wire [3:0] sum;
fourbit_beh uut (
.a(a),
.b(b),
.cin(cin),
.cout(cout),
.sum(sum)
);
initial begin
a = 0; b = 0; cin = 0;
#100;
a=1010; b=0101; cin=1;
#100;
a=1010; b=0101; cin=0;
#100;
a=1100; b=0011; cin=1;
#100;
a=1111; b=1111; cin=1;
end
endmodule

Output:

4. Adder/Subtractor Design
Using full adders:
module addsub(
input [3:0] a,
input [3:0] b,
input cin,
input k,
output [3:0] sum,
output cout
);
wire c0,c1,c2;
fa_ha in1(a[0],b[0]^k,cin,c0,sum[0]);
fa_ha in2(a[1],b[1]^k,c0,c1,sum[1]);
fa_ha in3(a[2],b[2]^k,c1,c2,sum[2]);
fa_ha in4(a[3],b[3]^k,c2,cout,sum[3]);
endmodule

RTL Schematic:

Dataflow Modelling:
module addsub_df (
input [3:0] a,
input [3:0] b,
input cin,
output cout,
output [3:0] sum
);
assign sum=a^(b^cin)^cin;
assign cout=(a&(b^cin))|((b^cin)&cin)|(cin&a);
endmodule
RTL Schematic:

Behavioral Modelling:
module addsub_beh (
input [3:0] a,
input [3:0] b,
input cin,
output reg cout,
output reg [3:0] sum
);
reg [4:0]temp;
integer i;
always@(*) begin
temp[0]=cin;
for(i=0;i<=3;i=i+1) begin
sum[i]=a[i]^(b[i]^cin)^temp[i];
temp[i+1]=(a[i]&(b[i]^cin))|((b[i]^cin)&temp[i])|(temp[i]&a[i]);
end
cout=temp[4];
end
endmodule
RTL Schematic:

Testbench:
module addsub_beh_tb;
reg [3:0] a;
reg [3:0] b;
reg cin;
wire cout;
wire [3:0] sum;
addsub_beh uut (
.a(a),
.b(b),
 .cin(cin),
.cout(cout),
.sum(sum)
);
initial begin
a = 0; b = 0; cin = 0;
#100;
a=1010; b=0101; cin=1;
#100;
a=1010; b=0101; cin=0;
#100;
a=1100; b=0011; cin=1;
#100;
a=1111; b=1111; cin=1;
#100;
a=1111; b=1111; cin=0;
end
endmodule

Outputs:
 Experiment. No. 2
Encoders, decoders, priority encoders and comparators
1.Encoder:

Structural Modelling:
module encoder_str(
input [7:0] D,
output [2:0] Q
);
or(Q[0],D[1],D[3],D[5],D[7]);
or(Q[1],D[2],D[3],D[6],D[7]);
or(Q[2],D[4],D[5],D[6],D[7]);
endmodule

RTL Schematic:
Dataflow Modelling:
module encoder_df(
input [7:0] d,
output [2:0] q
);
assign q[0]=d[1]+d[3]+d[5]+d[7];
assign q[1]=d[2]+d[3]+d[6]+d[7];
assign q[2]=d[4]+d[5]+d[6]+d[7];
endmodule

RTL Schematic:

3.Behavioral Modelling:
module encoder_beh(
input [7:0] d,
input enable,
output reg [2:0] out
);
always@(d,enable) begin
if(enable)
case(d)
8'b0000_0001:out=3'b000;
8'b0000_0010:out=3'b001;
8'b0000_0100:out=3'b010;
8'b0000_1000:out=3'b011;
8'b0001_0000:out=3'b100;
8'b0010_0000:out=3'b101;
8'b0100_0000:out=3'b110;
8'b1000_0000:out=3'b111;
default:out=1'b0;
endcase
else
out=1'bx;
end
endmodule

RTL Schematic:
Testbench:
module encoder_beh_tb;
reg [7:0] d;
reg enable;
wire [2:0] out;
encoder_beh uut (
.d(d),
.enable(enable),
.out(out)
);
 initial begin
d = 0;enable = 0;
#100;
d=0000_0001;enable=1;
#100;
d=0000_1000;enable=1;
#100;
d=1000_0000;enable=0;
#100;
d=0001_0000;enable=1;
#100;
d=1111_1111;enable=1;
end
endmodule

Outputs:

2.Decoders:

Structural Modelling:
module decoder_str(
input x,
input y,
input z,
output [7:0] D
);
wire xbar,ybar,zbar;
not(xbar,x);
not(ybar,y);
not(zbar,z);
and(D[0],xbar,ybar,zbar);
and(D[1],xbar,ybar,z);
and(D[2],xbar,y,zbar);
and(D[3],xbar,y,z); 2.DATA FLOW MODELLING
and(D[4],x,ybar,zbar);
and(D[5],x,ybar,z);
and(D[6],x,y,zbar);
and(D[7],x,y,z);
endmodule
RTL Schematic:

Dataflow Modelling:
module decoder_df(
input x,
input y,
input z,
 output [7:0] d
);
assign d[0]=~x&~y&~z;
assign d[1]=~x&~y&z;
assign d[2]=~x&y&~z;
assign d[3]=~x&y&z;
assign d[4]=x&~y&~z;
assign d[5]=x&~y&z;
assign d[6]=x&y&~z;
assign d[7]=x&y&z;
endmodule

RTL Schematic:

Behavioral Modelling:
module decoder(
input [2:0] in,
output reg [7:0] out
);
always@(in) begin
case(in)
3'b000:out=8'b00000001;
3'b001:out=8'b00000010;
3'b010:out=8'b00000100;
3'b011:out=8'b00001000;
3'b100:out=8'b00010000;
3'b101:out=8'b00100000;
3'b110:out=8'b01000000;
3'b111:out=8'b10000000;
default:out=8'bx;
endcase
end
endmodule

RTL Schematic:

Testbench:
module decoder_tb;
reg [2:0] in;
wire [7:0] out;
decoder uut (
.in(in),
.out(out)
);

initial begin
#50;
in=3'b000;
#50;
in=3'b001;
#50;
in=3'b010;
#50;
 in=3'b011;
#50;
in=3'b100;
#50;
in=3'b101;
#50;
in=3'b110;
#50;
in=3'b111;
end
endmodule

Outputs:

3.Priority Encoder

Structural Modelling:
module priorityenc_gate(
input [7:0] d,
output [2:0] q
);
wire [7:0]nd;
wire a,b,c,j,e,f;
not n0(nd[0],d[0]);
not n1(nd[1],d[1]);
not n2(nd[2],d[2]);
not n3(nd[3],d[3]);
not n4(nd[4],d[4]);
not n5(nd[5],d[5]);
not n6(nd[6],d[6]);
not n7(nd[7],d[7]);
and a1(a,nd[7],nd[5],nd[4],nd[3],nd[2],d[1]);
and a2(b,nd[7],nd[6],nd[5],nd[4],d[3]);
and a3(c,nd[7],nd[6],d[5]);
and a4(j,nd[7],nd[6],nd[5],nd[4],nd[3],d[2]);
and a5(e,nd[7],d[6]);
and a6(f,nd[7],nd[6],nd[5],d[4]);
or o1(q[0],a,c,d[7]);
or o2(q[1],b,j,e,d[7]);
or o3(q[2],c,e,f,d[7]);
endmodule

RTL Schematic:

Dataflow Modelling:
module priorityenc_data(
input d0,d1,d2,d3,d4,d5,d6,d7,
output [2:0] q
);
assign
q[2] = (~d7 & ~d6 & ~d5 & d4) | (~d7 & ~d6 & d5) | (~d7 & d6) | d7,
q[1] = (~d7 & ~d6 & ~d5 & ~d4 & ~d3 & d2) | (~d7 & ~d6 & ~d5 & ~d4 & d3 ) | (~d7
& d6) | d7,
q[0] = (~d7 & ~d6 & ~d5 & ~d4 & ~d3 & ~d2 & d1) | (~d7 & ~d6 & ~d5 & ~d4 & d3)
| (~d7 & ~d6 & d5) | d7;
endmodule

RTL Schematic:

Behavioral Modelling:
module priorityenc_beh(
input [7:0] d,
output reg [2:0] q
);
always @ (*)
begin
case (d)
8'b00000001 : q = 3'b000;
8'b0000001x : q = 3'b001;
8'b000001xx : q = 3'b010;
8'b00001xxx : q = 3'b011;
8'b0001xxxx : q = 3'b100;
8'b001xxxxx : q = 3'b101;
8'b01xxxxxx : q = 3'b110;
8'b1xxxxxxx : q = 3'b111;
endcase
end
endmodule

RTL Schematic:

Testbench:
module pri_tb;
reg [7:0] d;
wire [2:0] q;
prienco uut (
.d(d),
 .q(q) );
initial begin
d = 00000001;
#100;
d = 0000_0011;
#100;
d = 00000010;
#100
end
endmodule

Output:

4.BCD to Seven Segment Decoder:

Structural Modelling:
module bcd_to_7_segment_struct(
input i0,
input i1,
input i2,
input i3,
output d6,
output d5,
output d4,
output d3,
output d2,
output d1,
output d0);
wire j0,j1,j2,j3;
not n1(j0,i0);
not n2(j1,i1);
not n3(j2,i2);
not n4(j3,i3);
wire a,b,c,d,e,f,g,h;
and a1(a,i1,j2);
and a2(b,j2,j0);
and a3(c,i1,j0);
and a4(d,i2,i0,j1);
or g1(d0,i3,a,b,c,d);
or g2(d1,i3,i2,j1,i0);
or g3(d2,b,c);
and a5(e,i2,j1);
or g4(d3,i3,e,c,a);
and a6(f,j1,j0);
and a7(g,i1,i2);
or g5(d4,g,f,j2,i3);
and a8(h,i0,i2);
or g6(d5,i3,e,f,h);
or g7(d6,i3,i1,h,b);
endmodule
RTL Schematic:
Dataflow Modelling:
module bcd_data(
input [3:0] i,
output [6:0] d
);
assign
d[0] =i[3] | ~i[2] & i[1] | ~i[2] & ~i[0] | i[1] & ~i[0] | i[2] & i[0] & ~i[1],
d[1] = i[3] | i[2] | ~i[1] | i[0],
d[2] = ~i[2] & ~i[0] | ~i[0] & i[1],

d[3] = i[3] | i[2] & ~i[1] | i[1] & ~i[0] | ~i[2] & i[1],
d[4] = i[3] | ~i[2] | ~i[1] & ~i[0] | i[1] & i[0],
d[5] = i[3] | i[2] & ~i[1] | ~i[1] & ~i[0] | i[2] & i[0],
d[6] = i[3] | i[1] | i[2] & i[0] | ~i[2] & ~i[0];
endmodule

RTL Schematic:
Behavioral Modelling:
module bcdto7_beh(
input [3:0] d,
output reg [6:0] i
);
always@(d) begin
case(d)
4'b0000:i=7'b111_1110;
4'b0001:i=7'b011_0000;
4'b0010:i=7'b110_1101;
4'b0011:i=7'b111_1001;
4'b0100:i=7'b011_0011;
4'b0101:i=7'b101_1011;
4'b0110:i=7'b101_1111;
4'b0111:i=7'b111_0000;
4'b1000:i=7'b111_1111;
4'b1001:i=7'b111_0011;
default:i=7'b000_0000;
endcase
end
endmodule

RTL Schematic:

Testbench:
module bcdto7_b;
reg [3:0] d;
wire [6:0] i;
bcdto7_beh uut (
.d(d),
.i(i)
);
 initial begin
d=4'b0000;#100;
d=4'b0001;#100;
d=4'b0010;#100;
d=4'b0011;#100;
d=4'b0100;#100;
d=4'b0101;#100;
d=4'b0110;#100;
d=4'b0111;#100;
d=4'b1000;#100;
d=4'b1001;#100;
d=4'b1111;
end
endmodule

Outputs:

5.1 bit comparator

Structural Modelling:
module compa_1bit_gate(
input a,
input b,
output g,
output l,
output e
);
wire na,nb;
not n1(na,a);
not n2(nb,b);
and a1(l,na,b);
and a2(g,nb,a);
xnor x1(e,g,l);
endmodule

RTL Schematic:

Dataflow Modelling:

module comp_1bit_data(
input a,
input b,
output g,
output l,
output e
);
assign
g = ~b & a,
l = ~a & b,
e = ~( ~a & b + a & ~b);
endmodule
RTL Schematic:

Behavioral Modelling:
module onebitcomp_beh(
input a,
input b,
output reg lt,
output reg gt,
output reg eq
);
always@(*)begin
case({a,b})
2'b00:begin lt=1'b0;eq=1'b1;gt=1'b0; end
2'b01:begin lt=1'b1;eq=1'b0;gt=1'b0; end
2'b10:begin gt=1'b1;lt=1'b0;eq=1'b0; end
2'b11:begin eq=1'b1;lt=1'b0;gt=1'b0; end
default:begin lt=1'bx;gt=1'bx;eq=1'bx; end
endcase
end
endmodule

RTL Schematic:
 Testbench:
module onebitcomp_beh_tb;
reg a;
reg b;
wire lt;
wire gt;
wire eq;
onebitcomp_beh uut (
.a(a),
.b(b),
.lt(lt),
.gt(gt),
.eq(eq)
);
initial begin
a = 0; b = 0;
#100;
a=0;b=1;
#100;
a=1;b=0;
#100;
a=1;b=1;
end
endmodule

Output:

6. 4 bit Magnitude Comparator

Structural Modelling:
module comp_4bit_gate(
input [3:0] a,
input [3:0] b,
output g,
output l,
output e
);
wire [3:0]na; wire [3:0]nb;
not n1(na[0],a[0]);
not n2(na[1],a[1]);
not n3(na[2],a[2]);not n4(na[3],a[3]);
not n6(nb[0],b[0]);not n5(nb[1],b[1]);
not n7(nb[2],b[2]);
not n8(nb[3],b[3]);
wire i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12;
xnor g1(i5,a[3],b[3]);
xnor g2(i6,a[2],b[2]);
xnor g3(i7,a[1],b[1]);
xnor g4(i8,a[0],b[0]);
and g5(i1,a[3],nb[3]);
and g6(i2,a[2],nb[2],i5);
and g7(i3,a[1],nb[1],i5,i6);
and g8(i4,a[0],nb[0],i5,i6,i7);
and g9(i9,b[3],na[3]);
and g10(i10,b[2],na[2],i5);
and g11(i11,b[1],na[1],i5,i6);
and g12(i12,b[0],na[0],i5,i6,i7);
or g13(g,i1,i2,i3,i4);
and g14(e,i5,i6,i7,i8);
or g15(l,i9,i10,i11,i12);
endmodule

RTL Schematic:

Dataflow Modelling:
module comp_4bit_data(
input [3:0] a,
input [3:0] b,
output g,
output l,
output e);
assign
g = a[3] & ~b[3] | ~(a[3] ^b[3]) & a[2] & ~b[2] | ~(a[3] ^b[3]) & ~(a[2] ^b[2])&
a[1] & ~b[1] | ~(a[3] ^b[3]) & ~(a[2] ^b[2]) & ~(a[1] ^b[1]) & a[0] & ~b[0],
l = ~a[3] & b[3] | ~(a[3] ^b[3]) & ~a[2] & b[2] | ~(a[3] ^b[3]) & ~(a[2] ^b[2]) &
~a[1] & b[1] | ~(a[3] ^b[3]) & ~(a[2] ^b[2]) & ~(a[1] ^b[1]) & ~a[0] & b[0],
e = ~(a[3] ^b[3]) & ~(a[2] ^b[2]) & ~(a[1] ^b[1]) & ~(a[0] ^b[0]);
endmodule
RTL Schematic:

Behavioral Modelling:
module fourbitcomp_beh(
input [3:0] a,
input [3:0] b,
output reg lt,
output reg gt,
output reg eq
);
always@(*) begin
if(a==b)begin
eq=1'b1;lt=1'b0;gt=1'b0;end
else if(a>b)begin
eq=1'b0;lt=1'b0;gt=1'b1;end
else begin
eq=1'b0;lt=1'b1;gt=1'b0;end
end
endmodule
RTL Schematic:

Testbench:
module fourbitcomp_beh_tb;
reg [3:0] a;
reg [3:0] b;
wire lt;
wire gt;
wire eq;
fourbitcomp_beh uut (
.a(a),
.b(b),
.lt(lt),
.gt(gt),
.eq(eq)
);
initial begin
// Initialize Inputs
a = 4'b1101;
b = 4'b1101;
#100;
a=4'b0110;b=4'b1101;
#100;
a=4'b1101;b=4'b1001;
end
endmodule
Outputs:
 Experiment No. 3
8-Bit Full Adder using 4-Bit Carry Look Ahead Adder

4bit Carry Look Ahead Adder

module fa_cla(
input [3:0] a,
input [3:0] b,
input cin,
output cout,
output [3:0] sum
);
wire [3:0]p;
wire [3:0]g;
wire [4:0]c;
assign p = a^b;
assign g=a&b;
assign c[0]=cin,
c[1]=c[0]*p[0]+g[0],
c[2]=c[1]*p[1]+g[1],
c[3]=c[2]*p[2]+g[2],
c[4]=c[3]*p[3]+g[3];
assign sum[0] = c[0]^p[0],
sum[1] = c[1]^p[1],
sum[2] = c[2]^p[2],
sum[3] = c[3]^p[3],
cout = c[4];
endmodule

RTL Schematic:
Testbench:
module fa_cla_test;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire cout;
wire [3:0] sum;
// Instantiate the Unit Under Test (UUT)
fa_cla uut (
.a(a),
.b(b),
.cin(cin),
.cout(cout),
.sum(sum)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 3;
b = 5;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 3;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 3;
b = 3;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

Outputs:
8 bit full adder using carry look ahead adder
module fa8_cla(
input [7:0] a,
input [7:0] b,
input cin,
output cout,
output [7:0] sum
);
wire c;
fa_cla f1(a[3:0],b[3:0],cin,c,sum[3:0]);
fa_cla f2(a[7:4],b[7:4],c,cout,sum[7:4]);
endmodule

RTL Schematic:

Testbench:
module fa8_cla_test;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg cin;
// Outputs
wire cout;
wire [7:0] sum;
// Instantiate the Unit Under Test (UUT)
fa8_cla uut (
.a(a),
.b(b),
.cin(cin),
 .cout(cout),
.sum(sum)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 88;
b = 88;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 111;
b = 22;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 213;
b = 123;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 125;
b = 11;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

Output:
 Experiment No. 4
Arithmetic and Logic Unit

Aim: To develop an arithmetic and logic unit with minimum of eight operations.

1.ALU Module(8 bit)

module alu8(output reg [7:0]y,input [7:0]a,b,input [2:0]s);

always@(*)
begin
case(s)
3'b000:begin y=a+b;end
3'b001:begin y=a-b;end
3'b010:begin y=a*b;end
3'd011:begin y=a/b;end
3'd100:begin y=a&b;end
3'd101:begin y=a|b;end
3'd110:begin y=a^b;end
3'd111:begin y=~(a^b);end
endcase
end
endmodule

RTL Schematic:

Testbench:
module alu8_tb;
reg [7:0] a;
reg [7:0] b;
reg [2:0] s;
 wire [7:0] y;
alu8 uut (
.y(y),
.a(a),
.b(b),
.s(s)
);

initial begin
a = 8'b11110000; b = 8'b00001111;s = 3'd0;
#100;
a = 8'b11110000;b = 8'b00001111;s = 3'd1;
#100;
a = 8'b11110000;b = 8'b00001111;s = 3'd2;
#100;
a = 8'b11110000;b = 8'b00001111;s = 3'd3;
#100;
a = 8'b11110000;b = 8'b00001111;s = 3'd4;
#100;
a = 8'b11110000;b = 8'b00001111;s = 3'd5;
#100;
a = 8'b11110000;b = 8'b00001111;s = 3'd6;
#100;
a = 8'b11110000;b = 8'b00001111;
s = 3'd7;
end
endmodule

Outputs:

2.Shifter(8bit)
module shifter8(output reg [7:0]y,input [7:0]i,input s,input [2:0]p);
always@(*)
begin
if(s)begin
y=i>>p;end
else begin
y=i<<p;end
end
endmodule
RTL Schematic:

Testbench:
module shifter8_tb;
reg [7:0] i;
reg s;
reg [2:0] p;
wire [7:0] y;
shifter8 uut (
.y(y),
.i(i),
.s(s),
.p(p)
);
initial begin
i = 8'd4;s = 0;p = 3'd1;
#100;
i = 8'd4; s = 1;p = 3'd1;
#100;
i = 8'd4;s = 0;p = 3'd2;
end
endmodule

Outputs:

3.ALU+Shifter
module alushift8(output [7:0]y,input [7:0]a,b,input [2:0]sa,p,input ss);
wire [7:0]w;
alu8 a0(w,a,b,sa);
shifter8 s0(y,w,ss,p);
endmodule

RTL Schematic:

Testbench:
module alushift8_tb;
reg [7:0] a;
reg [7:0] b;
reg [2:0] sa;
reg [2:0] p;
 reg ss;
wire [7:0] y;
alushift8 uut (
.y(y),
.a(a),
.b(b),
.sa(sa),
.p(p),
.ss(ss)
);
initial begin
a = 8'b11110000;
b = 8'b00001111;
sa = 3'd0;
p = 3'd4;
ss = 0;
#100;
a = 8'b11110000;
b = 8'b00001111;
sa = 3'd5;
p = 3'd4;
ss = 1;
#100;
end
endmodule

Output:
 Experiment No. 5
Flip flops
Aim: Develop structural and behavioral models for D, SR and JK Flip flops and verify their
operation.
D Flipflop:

Structural modelling:
module d_str(
input d,
input clk,
output q,
output qbar
);
wire dbar,temp1,temp2;
not(dbar,d);
nand n1(temp1,d,clk);
nand n2(temp2,dbar,clk);
nand n3(q,temp1,qbar);
nand n4(qbar,q,temp2);
endmodule

RTL Schematic:
Behavioral Modelling:
module dbeh(
input d,
input clk,
input rst,
output reg q
);
always@(posedge clk)//synchronous clear
if(rst)
q<=0;
else
q<=d;
endmodule

RTL Schematic:
Testbench:
module dbeh_tb;
reg d;
reg clk;
reg rst;
wire q;
dbeh uut (
.d(d),
.clk(clk),
.rst(rst),
.q(q)
);
initial begin
clk=0;
forever #20 clk=~clk;
end
initial begin
d = 0; rst = 0;
#100;
d=0;rst=1;
#100;
d=1;rst=0;
#100;
d=1;rst=1;
end
endmodule

Outputs:
SR Flipflop:

Structural Modelling:
module sr_str(
input s,
input r,
input clk,
output q,
output qbar
);
wire temp1,temp2;
nand n1(temp1,s,clk);
nand n2(temp2,r,clk);
nand n3(q,temp1,qbar);
nand n4(qbar,temp2,q);
endmodule
RTL Schematic:
Behavioral Modelling:
module sr_beh(
input s,
input r,
input clk,
input rst,
output reg q
);
always@(posedge clk)
begin
if(rst)
q<=0;
else begin
case({s,r})
2'b00:q<=q;
2'b01:q<=0;
2'b10:q<=1;
2'b11:q<=1'bx;
default:q<=1'bx;
endcase
end
end
endmodule

RTL Schematic:

TestBench:
module sr_beh_tb;
reg s;
reg r;
reg clk;
reg rst;
wire q;
 sr_beh uut (
.s(s),
.r(r),
.clk(clk),
.rst(rst),
.q(q)
);
initial begin
clk=1'b1;
forever #30 clk=~clk;
end
initial begin
s = 0; r = 0;rst = 0;
#100;
s=0;r=0;rst=1;
#100;
s=0;r=1;rst=0;
#100;
s=0;r=1;rst=1;
#100;
s=1;r=0;rst=0;
#100;
s=1;r=0;rst=1;
#100;
s=1;r=1;rst=0;
#100;
s=1;r=1;rst=1;
end
endmodule

Outputs:
JK Flipflop:

Behavioral Modelling:
module jkbeh(
input j,
input k,
input clk,
input rst,
output reg q
);
always@(posedge clk)begin
if(rst)
q<=1'b0;
else
begin
case({j,k})
2'b00:q<=q;
2'b01:q<=1'b0;
2'b10:q<=1'b1;
2'b11:q<=(~q);
default:q<=1'bx;
endcase
end
end
endmodule

RTL Schematic:

Testbench:
module jkbeh_tb;
reg j;
reg k;
reg clk;
reg rst;
wire q;
jkbeh uut (
.j(j),
.k(k),
.clk(clk),
.rst(rst),
.q(q)
);
initial begin
clk=1'b1;
forever #30 clk=~clk;
end
initial begin
j = 0;k = 0;rst = 0;
#100;
j=0;k=0;rst=1;
#100;
 j=0;k=1;rst=0;
#100;
j=0;k=1;rst=1;
#100;
j=1;k=0;rst=0;
#100;
j=1;k=0;rst=1;
#100;
j=1;k=1;rst=0;
#100;
j=1;k=1;rst=1;
end
endmodule

Outputs:
 Experiment No. 6
Registers/Counters
Aim: To develop HDL code for various registers and counters and verify their
operation using testbench.

1.PIPO 8bit register with clear input

module pipo(
input [7:0]d,
input clk,
input clr,
output reg [7:0]q
);
always@(posedge clk)begin
if(clr)q<=0;
else q<=d;
end
endmodule

RTL Schematic:

Testbench:
module pipo_tb;
reg [7:0] d;
reg clk;
wire [7:0] q;
pipo uut (
.d(d),
.clk(clk),
.q(q)
);
initial begin
clk=1'b0;
forever #30 clk=~clk;
end
initial begin
d = 8'b0000_0000;
#100;
d=8'b1010_1010;
#100;
d=8'b0101_0101;
#100;
d=8'b1011_0101;
#100;
d=8'b1100_1100;
#100;
d=8'b1111_1111;
end
endmodule

Outputs:

2.SISO 8bit register with clear input

module siso(
input serial_in,
input clk,
input clr,
output serial_out
);
reg [7:0]q=0;
always@(posedge clk)begin
if(clr)q<=0;
else begin
q[7]<=serial_in;
q[6]<=q[7];
q[5]<=q[6];
q[4]<=q[5];
q[3]<=q[4];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
end
assign serial_out=q[0];
endmodule

RTL Schematic:

Testbench:
module sisotb;
reg serial_in;
reg clk;
reg clr;
wire serial_out;
siso uut (
.serial_in(serial_in),
.clk(clk),
.clr(clr),
 .serial_out(serial_out)
);

initial begin
clk=0;
forever #20 clk=~clk;
end
initial begin
serial_in = 0;
#100;serial_in=1;clr=0;
#100;serial_in=1;clr=1;
#100;serial_in=0;clr=0;
#100;serial_in=1;clr=0;
#100;serial_in=0;clr=1;
#100;serial_in=0;clr=0;
#100;serial_in=1;clr=0;
end
endmodule

Outputs:

3.Universal Shift Register

module univshift(
 input [7:0] d,
input [1:0] sel,
input reset,
output [7:0] q
);
reg[7:0] curr_state,next_state;
always@(posedge clk,posedge reset)begin
if(reset)
curr_state<=0;
else
curr_state<=next_state;
end
always@(*)begin
case(sel)
2'b00:next_state=curr_state;//no change
2'b01:next_state={curr_state[6:0],d[0]};//shift left
2'b10:next_state={d[7],curr_state[7:1]};//shift right
2'b11:next_state=d;//parallel load
endcase
end
assign q=curr_state;
endmodule

RTL Schematic:

Testbench:
module univshift_tb;
reg [7:0] d;
reg [1:0] sel;
reg clk;
reg reset;
wire [7:0] q;

univshift uut (
 .d(d),
.sel(sel),
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
clk=0;
forever #20 clk=~clk;
end
initial begin
d = 1011_0101;
sel = 11;
reset = 0;
#50;
d=1011_0101;sel=01;reset=0;
#50;
d=1011_0101;sel=10;reset=0;
#50;
d=1011_0101;sel=00;reset=0;
#50;
d=1011_0101;sel=11;reset=1;
#50;
d=1011_0101;sel=01;reset=1;
#50;
d=1011_0101;sel=10;reset=1;
#50;
d=1011_0101;sel=00;reset=1;
end
endmodule

Outputs:

4. A 4- bit straight binary counter with synchronous preset and clear.

module binary4(
 input clk,
input [3:0] preset,
input load, //load is active low
input clear, //clear is active low
output reg [3:0] out
);
always@(posedge clk) begin
if(!clear)
out<=0;
else if(!load)
out<=preset;
else if(out==4'b1111)
out<=0;
else
out<=out+1'b1;
end
endmodule

RTL Schematic:

Testbench:
module binary4_tb;
reg clk;
reg [3:0] preset;
reg load;
reg clear;
wire [3:0] out;
binary4 uut (
.clk(clk),
.preset(preset),
.load(load),
.clear(clear),
.out(out)
 );
initial begin
clk=1'b0;
forever #20 clk=~clk;
end
initial begin
preset = 4'b1100;
load = 0;
clear = 1;
#200;
preset=4'b1100;load=1;clear=1;
#200;
preset=4'b1010;load=1;clear=0;
end
endmodule

Outputs:

5.MOD 10 Counter

module mod10(
input clk,
input rst,
output reg[3:0] out
);
always@(posedge clk) begin
if(rst)
out<=0;
else if(out<9)
out<=out+1;
else
out<=0;
end
endmodule

RTL Schematic:

Testbench:
module mod10_tb;
reg clk;
reg rst;
wire [3:0] out;
mod10 uut (
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
clk=0;
forever #10 clk=~clk;
end
initial begin
rst =1;
#100;
rst=0;
#1000;
end
endmodule

Outputs:
6. A 4-bit straight binary down counter with synchronous preset and
asynchronous clear

module binary4down(
input [3:0] in,
input clk,
input load,//active low
input clear,//active low
output reg [3:0] out
);//synchronous preset,asynchronous clear
always@(posedge clk or negedge clear) begin
if(!clear)
out<=0;
else if(!load)
out<=in;
else if(out==4'b0000)
out<=4'b1111;
else
out<=out-1'b1;
end
endmodule
RTL Schematic:

Testbench:
module binary4down_tb;
reg [3:0] in;
reg clk;
reg load;
reg clear;
wire [3:0] out;
binary4down uut (
.in(in),
.clk(clk),
.load(load),
.clear(clear),
.out(out)
);
initial begin
clk=1'b0;
forever #20 clk=~clk;
end
initial begin
in= 4'b0110;load = 0; clear = 1;
#200;
in=4'b0110;load=1;clear=1;
#200;
in=4'b1010;load=1;clear=0;
end
endmodule

Outputs: