Week 4: Assignment 4

Q1. In a CMOS dynamic circuit design, if the pull-down network is off, the output should be at
VDD during the evaluation phase. However, the charge gradually leaks away. Explain Why?
(A) Due to the leakage current
(B) Due to the latch-up effect
(C) Due to the Johnson effect
(D) None of these
Answer: (A) Due to the leakage current
Q2. Logic reduces the transistor counts which are used to make different logic gates by eliminating
the redundant transistor is called _________.
(A) Resistive transistor logic
(B) Transistor transistor logic
(C) Pass transistor logic
(D) None of these
Answer: (C) Pass transistor logic
Q3. Considering the given CMOS topology, implement the Boolean expression available at the
OUT1 node.

(A) (A + B) . (C + D) . (E + F + (G . H))
(B) (A . B) . (C . D) . (E + F + (G . H))
(C) (A + B + C + D) . (E . F . G . H)
(D) None of these
Answer: (A) (A + B) . (C + D) . (E + F + (G . H))
Q4. What logic family is this complex logic circuit a member of?

(A) DCVSL
(B) NP CMOS
(C) Domino
(D) NORA
Answer: (A) DCVSL
Q5. Statement: NP CMOS logic is an alternative to cascade dynamic logic.
Is the given statement true or false?
(A) False
(B) True
(C) None of these

Answer: (B) True

Q6. Would the circuit still function correctly if the PMOS transistor was removed?

(A) Yes
(B) No
(C) None of these

Answer: (B) No
Q7. Identify the transistor network shown in the figure enclosed by the dotted lines?

(A) Pass transistor network

(B) Transmission gate network
(C) PMOS only network
(D) PROTEUS

Answer: (A) Pass transistor network

Q8. Considering the circuit diagram shown below. Are the logic functions of these two circuits
(namely Circuit A and Circuit B) the same?

(A) No, the logic function of Circuit A is different from Circuit B

(B) Yes, the logic function of Circuit A is the same as Circuit B
(C) None of these
Answer: (B) Yes, the logic function of Circuit A is the same as Circuit B
Q9. Which logic family is the circuit a member of?

(A) Pseudo-NMOS logic

(B) Pseudo-PMOS logic
(C) Pseudo-BJT logic
(D) None of these

Answer: (A) Pseudo-NMOS logic

Q10. Assume that all the transistors from M1 to M6 have W/L of (0.5 µm/0.25 µm). Let us assume
that the drain current for each transistor (NMOS and PMOS) be 1 µA for NMOS at VGS = VTH and
PMOS at VSG = VTH. What input vector generates the worst-case leakage power for each output
value?

(A) When two transistors leak in parallel, the worst-case scenario occurs
(B) When zero transistors leak in parallel, the worst-case scenario occurs
(C) When only one transistors leaks, the worst-case scenario occurs
(D) None of these
Answer: (A) When two transistors leak in parallel, the worst-case scenario occurs
 Week 4: Assignment 4: Brief Explanations

Q1. Explanation: In a CMOS dynamic circuit design, if the pull-down network is off, then the
output should be at VDD during the evaluation phase. However, the charge gradually leaks away.
This is due to the leakage current.
Q2. Explanation: Pass transistor logic (PTL) reduces the count of transistors used to make
different logic gates by eliminating redundant transistors.
Q3. Explanation: Using the simple CMOS rule of both PMOS and NMOS connections, one can
easily derive the Boolean expression available at the OUT1 node is (A + B) . (C + D) . (E + F +
(G . H)).
Q4. Explanation: It belongs to the Differential Cascode Voltage Switch Logic (DCVSL) logic
family.
Q5. Explanation: The given statement is true. Since the NP Domino circuit has no inverter at the
output of each stage, it is generally composed of fewer transistors than Domino CMOS circuits. It
also offers more logical flexibility by providing both inverting and noninverting signals at the
output.
Q6. Explanation: No, removing the PMOS would cause the output node to remain low when
AB=00 because it would be floating. When the output node would otherwise be in a high
impedance state, the PMOS device pulls it high.
Q7. Explanation: The transistor network shown in the figure enclosed by the dotted lines is a pass
transistor network.
Q8. Explanation: Yes, the logic function of Circuit A is the same as Circuit B because Circuit A
and B both have the same logic function of F = A + B + C and G = A + B + C + D.

Q9. Explanation: The circuit implements Out = A + BC. It is in the Pseudo NMOS logic family.

Q10. Explanation: When the output is high, the worst-case leakage occurs when two transistors
leak in parallel: ABC = 100. When the output is low, the worst-case leakage also occurs when two
transistors leak in parallel: ABC = 110 or ABC = 101.