Week 3: Assignment 3

Q1. Name some of the basic design methodologies to reduce switching activity in CMOS
combinational logic circuits.
(A) Logic restructuring
(B) Input ordering
(C) Time multiplexing resources
(D) All of these
Answer: (D) All of these
Q2. Identify the load elements that can be used in a ratioed logic design?
(A) Resistive load
(B) NMOS load
(C) PMOS load
(D) All of these
Answer: (D) All of these
Q3. What is the name of the given CMOS logic circuit?

(A) Pseudo-NMOS NOR gate

(B) Pseudo-NMOS NAND gate
(C) PMOS only NOR gate
(D) NMOS only NOR gate
Answer: (A) Pseudo-NMOS NOR gate
Q4. Statement: DCVSL has been introduced to eliminate the static power dissipation and achieve
rail-to-rail voltage swing.
Is the given statement true or false?
(A) False
(B) True
(C) None of these
Answer: (B) True
Q5. The propagation delay of a complex network follows________.
(A) Jacob delay theorem
(B) Johnson delay rule
(C) Elmore delay rule
(D) None of these

Ans: (C) Elmore delay rule

Q6. Determine the activity coefficient of a 2-input CMOS NOR gate.

(A) 0.1999
(B) 0.1758
(C) 0.1875
(D) 0.1993

Ans: (C) 0.1875

Q7. A general purpose open source analog simulator is _________.
(A) SPICE
(B) MATLAB
(C) C++
(D) PROTEUS

Ans: (A) SPICE

Q8. Choose the statement that is used to store an estimate of DC operating point during transient
analysis?
(A) .OP
(B) .OPT
(C) .TRAN
(D) None of these
Answer: (A) .OP
Q9. Statement: When the NMOS transistor in turned ON in a pseudo-NMOS logic, the dynamic
power is decreased.
Is the given statement true or false?
(A) True
(B) False
(C) None of these

Answer: (A) True

Q10. Statement: When the input voltage is less than the threshold voltage in a Pseudo-NMOS
logic, zero current is drawn from the supply.
Is the given statement true or false?
(A) True
(B) False
(C) None of these
Answer: (A) True
______________________________________________________________________________

Week 3: Assignment 3: Brief Explanations

Q1. Explanation: Logic restructuring, Input ordering, and Time multiplexing

resources are primary design methodologies to reduce the switching activity in
CMOS combinational logic circuits.
Q2. Explanation: The load elements that can be used in a ratioed logic design are
(a) Resistive load (b) NMOS load (c) PMOS load

Q3. Explanation: The name of the given CMOS logic circuit is Pseudo-NMOS NOR gate.
Q4. Explanation: The given statement is true because Differential Cascode Voltage Switch Logic
(DCVSL) is a CMOS circuit technique that has potential advantages over conventional
NAND/NOR logic in terms of power dissipation, circuit delay, layout density, and logic flexibility.
Q5. Explanation: The propagation delay of a complex network follows the Elmore delay rule
because Elmore delay is a simple approximation to the delay through an RC network in an
electronic system.
Q6. Explanation: For the NOR gate, the probability the output is at 0, p0 = 0.75
Probability the output is at 1, p1 = 0.25
The activity coefficient, a = p0•p1 = 0.75(0.25) = 0.1875.

Q7. Explanation: SPICE is the general-purpose, open-source analog circuit simulator available
in the market.

Q8. Explanation: The SPICE statement .OP represents the DC operating point during transient
analysis.

Q9. Explanation: When the NMOS transistor is turned ON in a pseudo-NMOS logic, the dynamic
power is decreased.
The given statement is true because When the NMOS is turned “ON”, a direct path between VDD
and ground exists, and static power will be drawn. However, the dynamic power is reduced due to
lower capacitive loading. When the input voltage is less than the threshold voltage. The output is
“High”, and no current is drawn from the VDD.

Q10. Explanation: When the input voltage is less than the threshold voltage in a Pseudo-NMOS
logic, zero current is drawn from the supply because the output is high and no current is being
drawn from the VDD supply.