Manual Buku Sony Panduan

MODIFICATION HISTORY
MODEL NAME : KE-42M1/P42M1/

MV42A1/MV42M1
SERVICE MANUAL
PARTS No. : 9-878-250-02
* Blue characters are linking.
Ver. DATE CONTENTS

1.0 2004. 6 Issued
1.1 2005.11 Addition of Taiwan, Hong Kong and Chinese Models.
Correction of Service parts. (P. 49)
Downloaded from www.Manualslib.com manuals search engine

KE-42M1/P42M1/MV42A1/MV42M1
PANEL MODULE SERVICE MANUAL
PDP Module Name
S42SD-YB03 KE-42M1 UC Model

KE-42M1 Canadian Model
KE-42M1 Taiwan Model
KE-P42M1 AEP Model
KE-MV42A1 Hong Kong Model
KE-MV42M1 Chinese Model
FLAT PANEL COLOR TV

CONTENTS
1. OUTLINE ································································································································ 3
1-1. Model Name of Plasma Display ······························································································ 3
1-2. External View ·························································································································· 3
1-3. Specifications ·························································································································· 4
2. PRECAUTIONS······················································································································ 5
2-1. Handling Precautions for Plasma Display ··············································································· 5
2-2. Safety Precautions for Service
(Handling, prevention of electrical shock, measure against power outage, etc)······················ 5
2-2-1. Safety Precautions ········································································································ 5
2-2-2. Precautions for servicing electrostatic sensitive devices ··············································· 6
3. NAME and FUNCTION ·········································································································· 8

3-1. Layout of Assemblies ·············································································································· 8
3-2. Block Diagrams ······················································································································· 10
3-2-1. Block Diagrams for Drive Circuit Operations ································································· 10
3-2-2. Logic Circuit Block Diagram··························································································· 12
3-3. Main Functions of Each Assembly ·························································································· 12
3-3-1. X-Main board ················································································································· 12
3-3-2. Y-Main board ················································································································· 13
3-3-3. Logic Main board ··········································································································· 13
3-3-4. Logic buffer (E, F)·········································································································· 13
3-3-5. Y-buffer board (upper/lower)·························································································· 13
3-3-6. COF (Chip on Flexible)·································································································· 13
3-4. Product/Serial Label Locations································································································ 14
4. OPERATION CHECKING AFTER RECTIFICATION ···························································· 15

4-1. Flow Charts ····························································································································· 15
4-1-1. No voltage output ·········································································································· 15
4-1-2. No video (Each voltage is normal.)················································································ 16
4-1-3. Abnormal display (Abnormal image is displayed.) ························································· 18
4-1-4. Sustain Open (No horizontal stripes are displayed.)······················································ 20
4-1-5. Sustain Short (Some horizontal stripes are linked.)······················································· 20
4-1-6. Address Open (No vertical stripes are displayed.)························································· 21
4-1-7. Address Short (Some vertical stripes are linked.)·························································· 22
4-2. Defects, Symptoms, and Defective Parts ·············································································· 23
5. DISASSEMBLING/REASSEMBLING···················································································· 31
5-1. Tools/Measurements··············································································································· 31
5-2. Exploded View························································································································· 31
5-3. Removal Procedures··············································································································· 32
5-3-1. Removing the Logic PCB Ass'y board from the Chassis Base ······································ 32
5-3-2. Removing the Y-Main Ass'y board from the Chassis Base············································ 32
5-3-3. Removing the X-Main Ass'y board from the Chassis Base············································ 32
5-3-4. Removing the Y-BUFFER board from the Chassis Base ·············································· 33
5-3-5. Removing the ADDRESS-BUFFER board from the Chassis Base································ 33
5-4. Installation Procedures············································································································ 34
5-4-1. Installing the TCPs on the Logic Buffer ········································································· 34
5-4-2. Installing the Y-Main Ass'y Board on the Y-Buffer ························································· 35
5-4-3. Installing X-Main and Y-Main Ass'y boards on the Chassis Base·································· 35
5-4-4. Installing the Logic PCB Ass'y board on the Chassis Base ··········································· 36
- 1 -

6. Operation Checks After Repair Service·············································································· 38
6-1. Check Items ···························································································································· 38
6-2. Check Procedure····················································································································· 38
7. Adjustment Procedure ········································································································· 39

7-1 Adjustment Spec. and locations ································································································· 39
7-2. Procedure·································································································································· 39
8. DATA······································································································································ 43
• Back Side (TCP type) ···················································································································· 43
• Logic Main Block Diagram ············································································································· 44
• Drive Waveform ····························································································································· 45
• Reset ············································································································································· 46
• Address (Scan) ······························································································································ 47
• Sustain Waveform ························································································································· 48
9. Service Parts ························································································································· 49
- 2 -

1. OUTLINE
1-1. Model Name of Plasma Display
MODEL : S42SD-YB03
1-2. External View
< M1 = X Board + Y Board + Logic Board >
- 3 -

1-3. Specifications
No Item Specification
1 Pixel 852 (H) x 480 (V) pixels (1 pixel = 1 R, G, B cells)
2 Number of Cells 2556 (H) x 480 (V)
3 Pixel pitch 1095 (H) x 1110 (V) mm
R 0.365 (H) x 1.110 (V) mm
4 Cell Pitch G 0.365 (H) x 1.110 (V) mm
B 0.365 (H) x 1.110 (V) mm
932.940 (H) x 532.800 (V) mm

5 Display size
[36.73 x 20.98 inches]
6 Screen size Diagonal 42" Color Plasma Display Module
7 Screen aspect 16 : 9
8 Display color 16.77 million colors
Over 160º
9 Viewing angle
(Angle with 50% and greater brightness perpendicular to PDP module.)
10 Dimensions 982 (W) x 582 (H) x 52.9 (D) mm
11 Weight Module 1 About 16.6 kg
12 Packing weight Module 1 240 ± 5kg (including modules) / 10pcs/BOX
13 Packing size L1175 x W1140 x H970 (mm)/10pcs / BOX
S42SD-YB03 60Hz/50Hz, LVDS
Broadcasting reception vertical

frequency
14 and
video/logic interface
- 4 -

2. PRECAUTIONS
To prevent the risks of unit damage, electrical shock and radiation, take the following safety, service, and ESD
precautions.
2-1. Handling Precautions for Plasma Display
2-2. Safety Precautions for Service (Handling, prevention of electrical shock, measure
against power outage, etc)
2-2-1. Safety Precautions
1) Before replacing a board, discharge forcibly the remaining electricity from the board.
2) When connecting FFC and TCPs to the module, recheck that they are securely
connected.
3) To prevent electrical shock, be careful not to touch leads during circuit operations.
4) To prevent the Logic circuit from being damaged, do not connect/disconnect signal
cables during circuit operations.
5) Follow voltage information when adjust it.
6) Before reinstalling the chassis and the chassis assembly, be sure to use necessary
protective stuffs.
7) Caution for design change: Do not install any additional devices to the module, and do
not change the electrical circuit design.
8) If any parts or wire is overheated or damaged, replace it with a new specified one
immediately, and identify the cause of the problem to resolve it.
- 5 -

9) Check that the wires are correctly arranged and connected. Do not change the
distances between the parts and the printed circuit board. Check that the AC power
cord is not damaged. Keep heating parts away from lead wires and other parts.
10) Product safety indication : Some electrical circuits and devices have specific safety
characteristics. Therefore when replacing parts, use the same parts as originals.
Safety and protective function will be lost even if parts with higher voltage and wattage
capability are used.
11) Be sure to disconnect the AC power cord before servicing.
12) After servicing, check that the screws, parts, and wires are correctly installed. Also
check that the peripheral parts are not damaged.
2-2-2. Precautions for servicing electrostatic sensitive devices
Some semiconductors (such as ICs and FETs) are easily damaged by electrostatic.
These devices are called electrostatic sensitive devices (ESD).
The rate of electrostatic damage to devices can be decreased by observing the
following precautions.
1) Before handling semiconductors and assemblies, discharge electrostatic from your

body with an earth ground, or wear an antistatic band.
(Be sure to discharge electrostatic before turning on the power, to prevent electrical
shock)
2) After removing the ESD assembly, place it on an antistatic mat with aluminum foil to
avoid electrostatic charge.
3) Use only a ground-tip soldering iron to solder and unsolder the ESD.
4) Use only an antistatic soldering removal device for the ESD. General soldering
removal devices are non-antistatic. Using such non-antistatic devices will damage the
ESD.
- 6 -

5) Before removing the protective material from the lead of a new ESD, bring the lead
into contact with the chassis or the circuit assembly that the ESD is to be installed on.
6) When handling an unpacked ESD for replacement, do not move around too much.
Moving (legs on the carpet, for example) generates enough electrostatic to damage
the ESD.
7) Do not take a new ESD from the protective case until the ESD is ready to be installed.
Most ESDs have a lead, which is easily short-circuited by conductive materials (such
as conductive foam and aluminum).
- 7 -

3. NAME and FUNCTION
3-1. Layout of Assemblies
3 2
5 1
6 7 8
No. Board
1 Logic Main
2 X-Main
3 Y-Main
4 Y-Buffer (upper)
5 Y-Buffer (lower)
6 Logic E Buffer
7 Logic F Buffer
8 Logic G Buffer
- 8 -

1. L-Main 5. Y-Buffer (lower)
2. X-Main 6. E-Buffer
3. Y-Main 7. F-Buffer
4, Y-Buffer (upper) 8. G-Buffer
- 9 -

3-2. Block Diagrams
3-2-1. Block Diagrams for Drive Circuit Operations
<Drive Y Board>
- 10 -

<Drive X Board>
<Drive Waveforms>
- 11 -

3-2-2. Logic Circuit Block Diagram
3-3. Main Functions of Each Assembly
3-3-1. X-Main board

The X-MAIN board generates a drive signal by switching the FET in synchronization
with the Logic Main board timing, and supplies the X electrode of the panel with the
drive signal through the connector. This board, connected to the panel’s X terminal,
has the following main functions.
1) Maintain voltage waveforms (including ERC).
2) Generate X Rising Ramp signal.
3) Maintain Ve bias between scan intervals.
- 12 -

3-3-2. Y-Main board
The Y-MAIN board generates a drive signal by switching the FET in synchronization
with the Logic Main board timing, and sequentially supplies the Y electrode of the
panel with the drive signal through the scan driver IC on the Y-buffer board. This
board, connected to the panel’s Y terminal, has the following main functions:
1) Maintain voltage waveforms (including ERC).
2) Generate Y Rising Ramp signal.
3) Maintain Vscan bias.
3-3-3. Logic Main board

The Logic Main board generates and outputs the address drive output signal and the
XY drive signal by processing the video signals. This board buffers the address drive
output signal and feeds it to the address driver IC (COF module).
(Video signal processing – XY drive signal generation - frame memory control –
address/data rearrangement – system control)
3-3-4. Logic buffer (E, F)

The logic buffer transmits data signals and control signals using a COF (Chip on
Flexible).
3-3-5. Y-buffer board (upper/lower)

The Y-buffer board consisting of the upper and lower boards supplies the Y terminal
with a scan waveform. The board comprises eight scan driver ICs (STMicroelectronics
STV7617: 64 or 65 output pins), but four ICs for the SD Class.
3-3-6. COF (Chip on Flexible)

The COF applies Va pulse to the address electrode, and constitutes address
discharge by the potential difference between the Va pulse and the pulse applied to
the Y electrode. The COF comprises four data driver ICs (STV7610A: 96 output pins).
Seven COFs are required for single scan.
- 13 -

3-4. Product/Serial Label Locations
Voltage information label Serial No. label Panel module label
Panel Module Label
Voltage information Label Serial No. Label

(Voltage specification)
- 14 -

4. OPERATION CHECKING AFTER RECTIFICATION
4-1. Flow Charts
4-1-1. No voltage output
Replace PSU and

check driver B’D in advance
(Refer to ‘4-1-2 No display’)
LED (Green)
RLY8001,8002
off
Go to ‘4-1-2
No Display’
Go to ‘4-1-2 No Display’
- 15 -

4-1-2. No video (Each voltage is normal.)
There is no strong association of the cause between no video and faulty board
(Y-Main, X-Main or Logic Main).
FUSE
- 16 -

FUSE
- 17 -

4-1-3. Abnormal display (Abnormal image is displayed)
(Except sustain or address line problems)
Y-MAIN, X-MAIN, Logic Main or circuits may be defective.
FUSE
- 18 -

FUSE
- 19 -

4-1-4. Sustain Open (No horizontal stripes are displayed.)
4-1-5. Sustain Short (Some horizontal stripes are linked.)
- 20 -

4-1-6. Address Open (No vertical stripes are displayed.)
Logic Main, Logic Buffer, FFC, or TCP may be defective.
- 21 -

4-1-7. Address Short (Some vertical stripes are linked.)
Logic Main, Logic Buffer, FFC, or TPC may be defective.
- 22 -

4-2. Defects, Symptoms, and Defective Parts
Condition Name Description Related Board
No Voltage Output No power voltage is

No Voltage Output PSU
supplied.
Each power voltage is normal, but no

No Display Y-MAIN, X-MAIN, Logic Main, Cables
image is displayed.
Abnormal Display Abnormal image is displayed on screen. Y-MAIN, X-MAIN, Logic Main
Sustain Open No horizontal stripes are displayed. Scan Buffer, FPC of X / Y
Sustain Short Some horizontal stripes are linked. Scan Buffer, FPC of X / Y
Address Open No vertical stripes are displayed. Logic Main, Logic Buffer, FFC, TCP
Address Short Some vertical stripes are linked. Logic Main, Logic Buffer, FFC, TCP
- 23 -

Symptom Defect Cause / Description
Combined cells: Multiple cells

combined from side to side, or up and
Combined down.
cells/Dark dots Dark dots: A cell not lighting by
receiving signals due to a foreign
material or bubble, or abnormal ITO.
Bright dots: A cell lighting

abnormally due to a foreign material or
Bright dots
bubble, color mixture or blur of
phosphor, or rib barrier OPEN.
Phosphor blur: Rib barrier OPEN, or

Phosphor blur
a cell invaded by another cell.
Phosphor color mixture: A cell with

Phosphor dried particles given from another cell,
color mixture or a cell unable to display original color
due to mask hole.
- 24 -

Defect : 6. Address (Vertical Stripe) Open Defect: 7. Address (Vertical Stripe) Short
Symptom: A line or block does not light up in Symptom: Another color simultaneously appears because
Address electrode direction (1 Line open, Block adjacent data recognizes the single pattern signal.
Open).
Cause : Cause :
(1) Manufacturing : Panel electrode single (1) Manufacturing : Panel electrode short/Foreign
line/Foreign material/Electrostatic/COF defect material/Conductive foreign object inside COF
(2) Parts : COF/Board/Connector defect defect/Lighting electrode cutting defect
(3) Operation : Assembling error/Film damage (2) Parts : COF/Buffer connector defect
- 25 -

Defect: 8. Address Output Error Defect: 9. Sustain (Horizontal Stripe) Open
Symptom: A defect other than Address Open and Symptom: One or more lines do not light up in
Short. Data printout signal error occurring at a certain Sustain direction.
gradation or pattern.
Cause :
(1) Cause : Manufacturing: Panel bus electrode single

line/FPC pressure defect
(2) Parts: FPC/Board/Connector defect, or connector

disconnection
(3) Operation: Assembling error
- 26 -

Defect: 10. Sustain (Horizontal Stripe) Short Defect: 11. Dielectric material layer damage
Symptom: Combined or adjacent lines are Short in Symptom: Burn caused by the damage of Address
Sustain direction. The lines appear brighter than Bus dielectric layer appears in the panel
others at Ramp gradation pattern or low gradation discharge/non-discharge area. Also Open/Short
pattern. occurs by the damage of Address/Sustain printout.
<Add Block and Line Open>
<Add and Sus Open>
Cause: Cause:
(1) Manufacturing: Panel electrode short/Foreign Layer uneveny/Abnormal voltage/Foreign material/

material Repair failed
(2) Parts: Board/Connector/Pin defect
(3) Operation : Connecter/Assembling error
- 27 -

Defect: 20. F/White Low Discharge Defect: 21. Weak discharge
Symptom: Low discharge caused by unstable cells Symptom: Normal discharge, but cells appear darker
occurring at Full White pattern of high (60 degrees) or due to weak light emission occurring mainly at low (5
normal temperature. degrees) Full White/Red/Green/Blue patterns or
gradation pattern.
Cause : Cause :
(1) Panel: MgO source/Dielectric thickness/Cell (1) Panel : MgO deposition count and thickness/Aging
pitch/Phosphor condition
(2) Circuit : Drive waveform/Voltage condition (2) Circuit : Drive waveform/Voltage condition
- 28 -

Defect: 32. Remaining image Defect: 33. Abnormal noise
Symptom: The previous pattern does not disappear Symptom: Panel or circuit board noise
after a new pattern appears. 1) Noise caused by panel (exhaust pipe) damage
Example) 50"HD module: Cross Hatch pattern (30 2) Noise caused by element vibration due to
seconds) Full White Pattern Considered as insufficient soldering on circuit
defective if the image remains for 30 seconds or

more.)
Cause : Cause :
(1) Panel : Inside moisture or impure gas/Phosphor (1) Panel: Barrier rib uniformity/Adhesion clipping
and dielectric element/Exhaust and adhesion defect
condition/Aging condition (2) Circuit : Parts vibration/Insufficient soldering/Drive
(2) Circuit : X, Y Sustain Pulse angle and width FET switching noise
(3) Operation : Panel or exhaust pipe crack
- 29 -

Defect Name: 37. Panel Damage Defect Name: 38. Exhaust Pipe Damage
Symptom : Panel crack or break. No image appears Symptom: Crack or break of exhaust pipe. An image
in some cases, depending on the damaged part and is partially lacking or the panel noise occurs,
damage level. depending on the damaged part and with the passage
of time.
Cause : Cause : Careless panel handling
(1) Manufacturing : Flatness/Palette pin interruption

(2) Operation : Overload of panel corner/Careless
handling
(3) Panel: Flatness/Assembly error.
- 30 -

5. DISASSEMBLING/REASSEMBLING
5-1. Tools/Measurements
Electric screwdriver,
Oscilloscope,
Multi-meter,
etc
5-2. Exploded View
- 31 -

No. P/NAME
6 Y-Drive
7 X-Drive
8 Logic-Main
9 Y-Buffer (UP)
10 Y-Buffer (Lower)
11 Logic-Buffer (E)
12 Logic-Buffer (F)
13 Logic-Buffer (G)
5-3. Removal Procedures
5-3-1. Removing the Logic PCB Ass'y board from the Chassis Base
1) Disconnect the FFC and other cables between the Logic board and the X and Y
boards.
2) Remove the screws from the Logic board using the electric screwdriver, and remove
the board from the Chassis Base.
5-3-2. Removing the Y-Main Ass'y board from the Chassis Base
1) Disconnect the FFC from the Y-Main Ass'y board, and disconnect the connectors
between the Y-Main Ass'y board and the Y-Buffer board.
2) Remove the screws from the Y-Main Ass'y board using the electric screwdriver, and
remove the board from the Chassis Base.
5-3-3. Removing the X-Main Ass'y board from the Chassis Base
1) Disconnect the FFC and the FPC connector from the X-Main Ass'y board.
2) Remove the screws from the X-Main Ass'y board using the electric screwdriver, and
- 32 -

5-3-4. Removing the Y-BUFFER board from the Chassis Base
1) Disconnect the FPC from the Y-BUFFER board.
2) Remove the screws from the Y-BUFFER board using the electric screwdriver, and
5-3-5. Removing the ADDRESS-BUFFER board from the Chassis Base

1) Remove the screws from the TCP heatsink, and remove the TCP heatsink from the
ADDRESS-BUFFER board.
2) Remove the screws from the ADDRESS-BUFFER board using the electric
screwdriver, and remove the board from the Chassis Base.
- 33 -

5-4. Installation Procedures
5-4-1. Installing the TCPs on the Logic Buffer
1) Install the Logic Buffer on the boss holes of the Chassis Base.
2) Stand the connector covers of the Logic Buffer vertically.
3) Connect the TCP film connectors to the Logic Buffer connectors horizontally.
4) Check that the TCP films are securely connected to the Logic Buffer connectors.
5) Place the TCP Cover Plate on the screw holes, and tighten the screws.
6) Tighten the TCP Cover Plate screws in the order of center, and then right and left.
7) Check that the TCP Cover Plate is secured with the screws.
1. Logic Buffer position (E/F/G Buffers) 2. TCP/Logic Buffer assembling
3. Installed TCP 4. TCP Cover Plate assembling
- 34 -

5-4-2. Installing the Y-Main Ass'y Board on the Y-Buffer
Connector 1
Y-MAIN ASSY BOARD
Y-BUFFER
5-4-3. Installing X-Main and Y-Main Ass'y boards on the Chassis Base
Chassis Base
F Type
Y-MAIN
ASSY BOARD
X-MAIN ASSY
BOARD
- 35 -

1) Install the X-Main and Y-Main Ass'y boards onto the Chassis Base as shown in the
figure on the previous page, using the following specified screws.
Board Screw Number of screws
X-MAIN M3 x L10 8
Y-MAIN M3 x L10 7
Y-BUFFER M3 x L10 10
2) The securing order is as follows: (1) center of each Main Board Ass'y, (2) right and left
of the Main Board Ass'y, and (3) others.
(The order depends on the alignment of the Chassis Base and the Main Board Ass'y.)
2) Tighten securely the screws on each Main Board Ass'y using the electric screwdriver.
5-4-4. Installing the Logic PCB Ass'y board on the Chassis Base
Chas
sis Base
Chassis Base
FF Type
Type
LOGIC MAIN
LOGIC MAIN
ASSYBOARD
ASSY BOARD
- 36 -

1) Install the Logic Main Board Ass'y onto the Chassis Base as shown in the figure on
the previous page, using the following specified screws.
Board Screw Number of screws
LOGIC BOARD M3 x L10 7
2) The securing order is as follows: (1) center of the Logic Main Board Ass'y, (2) right
and left of the Logic Main Board Ass'y, and (3) others.
(The order depends on the alignment of the Chassis Base and the Logic Main Board
Ass'y.)
3) Tighten securely the screws on the Logic Main Board Ass'y using the electric
screwdriver.
- 37 -

6. Operation Checks After Repair Service
6-1. Check Items
xxxxx Check Item Specification Remarks
TCP
Drive board
Securely connected or tightened
Module Y Buffer
assemble check Logic and Logic Buffer
Harness Securely connected
Foreign materials No foreign materials
6-2. Check Procedure

1) Check visually the following: (1) the module is correctly assembled, (2) the
connections have no problem, and (3) the grounding and easily short-circuited parts
are not damaged.
2) Check that the dip switch is inside the module.
3) Turn on the power of the PDP module, and check that the LED lights up and the unit
correctly functions.
4) Check the power voltages, and also check the display condition by tapping slightly the
Y-FPC several times.
5) Check that Full White pattern is normal.
6) If the pattern is abnormal, adjust each voltage using the multi-meter and adjustment
tools.
7) Adjust the waveforms using the oscilloscope.
8) Display each pattern image to check the discharge on the screen.
9) Vary video level of input signal and make sure image is displayed correctly without
any problems.
- 38 -

7. Adjustment Procedure
7-1. Adjustment Spec. and locations
TCP Ramp Curve adjustment (Y-Board)
1’st sub-field 3’rd sub-field
2’nd sub-field
Vset Adjustment: Vsch Adjustment:

10 uSec +/- 1 uSec by VR5002 40 volts +/- 1 volt by VR5004
rd
30 u Sec +/- 1 u Sec by VR5003 (In 3 Sub field)
30 u Sec +/- 1 u Sec by VR5001
7-2. Procedure
1) Provide Full White pattern signal.
(Change Dip SW from internal to external, as shown in Appendix 3.)
2) Set positive probe of Multi-meter to “Vsch” and negative probe to the ground. See
appendix 2.
Vary VR5004 and set 40 volts +/- 1.0 volt.
3) Use an Oscilloscope and display a waveform at test point (Out4) on Y-Buffer board.
Control Trigger and hold the waveform.
(Use V_TOGG on Logic board or V-Sync on B-bd as triggering source is one of idea.)
Adjust controls and set “1 TV field” to proper horizontal size on screen.
st
Adjust horizontal controls and pick up “1 Sub-Field”, as shown in appendix 1.
- 39 -

4) Vary VR5002 and set Vset to 10 uSec. +/- 1 uSec.
(Vertical control should be set 2volts/Div or 5Volts/Div.)
5) Vary VR5003 and set Falling hold period to 30 uSec. +/- 1 uSec.
rd
6) Adjust Horizontal controls and puck up “3 Sub-Field”. Vary VR5001 and set Falling
hold period to 30 uSec. +/- 1 uSec.
(Vertical control should be set 2volts/Div or 5Volts/Div.)
Note;
st rd
Adjusting 1 sub-field first and then go to 3 sub-field.
Appendix 1) Drive waveform
1’st sub-field 3’rd sub-field
Vset : 10µs
Falling : 30µs Falling : 30µs
- 40 -

Appendix 2) Location of VR5001 to 5004, and test point of “Vsch”
Y-Main board
VR5004 VR5001
VR5003
VR5002
Vsch voltage test
point
- 41 -

Appendix 3) “Dip Switch” setting
1 2 3 4 1 2 3 4
< Internal > <External>
- 42 -

8. DATA
42”SD Back Side (TCP type)
Scan
Buffer
(UP)
SMPS X-Main
Y-Main
Scan
Buffer
(Down) Logic-Main
E Buffer F Buffer G-Buffer
- 43 -

42”SD Logic Main Block Diagram
- 44 -

Drive Waveform
Vset
Y Vsc_H
12V 12V
Vs
Ve Vsc_L
- 45 -

Reset
Vsc_h
4
1 Vs Vset 3 Vb5 Vs
Xb
Yr
Cset Ramp Yrr1 Xr
YDCH SC_H
Ys XDCH
Xs
YDr Csc
XDr
Ypn
Ly Lx
Panel
YDf Ypp YDr Cxr
Cyr
SC_L
GND Yg Xg GND
10V Zener
Yf
Ramp Yer Xf
Yfr Ysc XDCL
YDCL Ramp
2
GND Vsc GND
- 46 -

Address (Scan)
Vsc_h
Vs Vset Vb 2 Vs
Xb
Yr
Cset Ramp Yrr1 Xr
YDCH SC_H
Ys XDCH
Xs
YDr Csc
XDr
Ypn
Ly Lx
Panel
YDf Ypp YDr Cxr
Cyr
SC_L
GND Yg Xg GND
10V Zener
Yf
Ramp Yer Xf
Yfr Ysc XDCL
YDCL Ramp
1
GND Vsc GND
- 47 -

Sustain Waveform
Vs Vset Vsc_h Vs
Vb
1 6
Xb
Yr
Cset Ramp Yrr1 Xr
YDCH SC_H
Ys XDCH
5 YDr Csc
Xs
XDr
4 Ly
Ypn
Lx
Panel
YDf Ypp YDr Cxr
Cyr
SC_L
GND Yg Xg GND
10V Zener
Yf
Ramp Yer Xf
Yfr Ysc XDCL
YDCL Ramp
GND Vsc
2 3GND
- 48 -

9. Service parts
Model Name Sony P/N Sony Parts Description

1 KE-42M1(UC) A-1078-833-A Panel Module Assy
2 KE-P42M1(AEP) 178906211 X MAIN BOARD
3 KE-MV42M1(CH) 178906311 Y MAIN BOARD
4 KE-42M1(CND) 178906411 LOGIC BOARD
5 KE-42M1(WB) 178906432 LOGIC BOARD
6 178906511 Y BUFFER BOARD (UP)
7 178906611 Y BUFFER BOARD (LOW)
8 178906711 E BUFFER BOARD
9 178906811 F BUFFER BOARD
10 178906911 G BUFFER BOARD
11 KE-42M1(UC) A-1097-539-A Panel Module Assy
12 KE-MV42A1(HK) 178906212 X MAIN BOARD
13 KE-42M1(CND) 178906312 Y MAIN BOARD
14 178906422 LOGIC BOARD
15 178906512 Y BUFFER BOARD (UP)
16 178906612 Y BUFFER BOARD (LOW)
17 178906712 E BUFFER BOARD
18 178906812 F BUFFER BOARD
19 178906912 G BUFFER BOARD
- 49 -

English
Sony EMCS Corporation 2005KL08-Data
Made in Japan
9-878-250-02
Ichinomiya TEC  2005. 11

Manual Buku Sony Panduan

Uploaded by

Copyright:

Available Formats

You might also like

Manual Buku Sony Panduan

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Manual Buku Sony Panduan

Uploaded by

Copyright:

Available Formats

MODIFICATION HISTORY

MODEL NAME : KE-42M1/P42M1/

Ver. DATE CONTENTS

Downloaded from www.Manualslib.com manuals search engine

S42SD-YB03 KE-42M1 UC Model

FLAT PANEL COLOR TV

Downloaded from www.Manualslib.com manuals search engine

3. NAME and FUNCTION ·········································································································· 8

4. OPERATION CHECKING AFTER RECTIFICATION ···························································· 15

Downloaded from www.Manualslib.com manuals search engine

7. Adjustment Procedure ········································································································· 39

9. Service Parts ························································································································· 49

Downloaded from www.Manualslib.com manuals search engine

1-1. Model Name of Plasma Display

1-2. External View

< M1 = X Board + Y Board + Logic Board >

Downloaded from www.Manualslib.com manuals search engine

1 Pixel 852 (H) x 480 (V) pixels (1 pixel = 1 R, G, B cells)

2 Number of Cells 2556 (H) x 480 (V)

3 Pixel pitch 1095 (H) x 1110 (V) mm

R 0.365 (H) x 1.110 (V) mm

4 Cell Pitch G 0.365 (H) x 1.110 (V) mm

B 0.365 (H) x 1.110 (V) mm

932.940 (H) x 532.800 (V) mm

6 Screen size Diagonal 42" Color Plasma Display Module

8 Display color 16.77 million colors

10 Dimensions 982 (W) x 582 (H) x 52.9 (D) mm

11 Weight Module 1 About 16.6 kg

12 Packing weight Module 1 240 ± 5kg (including modules) / 10pcs/BOX

13 Packing size L1175 x W1140 x H970 (mm)/10pcs / BOX

S42SD-YB03 60Hz/50Hz, LVDS

Broadcasting reception vertical

Downloaded from www.Manualslib.com manuals search engine

2-1. Handling Precautions for Plasma Display

2-2-1. Safety Precautions

5) Follow voltage information when adjust it.

Downloaded from www.Manualslib.com manuals search engine

11) Be sure to disconnect the AC power cord before servicing.

2-2-2. Precautions for servicing electrostatic sensitive devices

1) Before handling semiconductors and assemblies, discharge electrostatic from your

Downloaded from www.Manualslib.com manuals search engine

Downloaded from www.Manualslib.com manuals search engine

3-1. Layout of Assemblies

Downloaded from www.Manualslib.com manuals search engine

4, Y-Buffer (upper) 8. G-Buffer

Downloaded from www.Manualslib.com manuals search engine

3-2-1. Block Diagrams for Drive Circuit Operations

Downloaded from www.Manualslib.com manuals search engine

Downloaded from www.Manualslib.com manuals search engine

3-3. Main Functions of Each Assembly

3-3-1. X-Main board

Downloaded from www.Manualslib.com manuals search engine

3-3-3. Logic Main board

3-3-4. Logic buffer (E, F)

3-3-5. Y-buffer board (upper/lower)

3-3-6. COF (Chip on Flexible)

Downloaded from www.Manualslib.com manuals search engine