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Onboard Data Handling and Telemetry
Onboard Data Handling and Telemetry
Cross-strapping
Cross-strapping is the term used referring how to interconnect redundant modules. At physical
level there are several types of implantation and configurations (e.g. if cold redundancy is used,
the redundant modules that are switch off shall not disturb the active modules).
The objective of cross-strapping is to increase the reliability of a functional chain by better
exploiting the available redundant resources. However, it may introduce additional cases of
failure propagation, dependencies, and single point failures. Usually, electronics digital
components are not prepared to receive current/voltage signal at their inputs while the
component is not powered. This could lead to unwanted leakage currents, perturbances,
malfunctions or premature component degradation. Cross-strapping techniques shall be
carefully considered in the design, especially in the CDHS.
LESSON 3: THE COMPLETE CDHS ARCHITECTURE
For those medium/large satellites (usually with more than one payload instrument ) and
with a specific Payload Data System (not integrated in the Spacecraft platform) the
architectures we can find varies more than the platform CDHS. Nevertheless, we can
identify common elements to provide an overview of a Payload Data Architecture.
• On-board payload data processing encompasses the data acquisition, transfer, storage,
data compression or reduction and transmission to ground of instrument and sensor
data. Quite often the amount of raw data generated by modern instruments is in excess
of what can be transmitted to ground. This makes it is necessary to use various signal
processing and compression techniques to reduce the amount of data. It is equally
important to have high speed data links, large on-board storage capabilities and digital
signal processors available that are fast enough handle data in the range of gigabytes
per second [RD10].
This is the reason why several platform elements we have seen for the CDHS are
replicated in the payload architecture -> there is need of dedicated hardware for the large
amount of data generated by modern instruments.
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
• The instrument (or better said instruments as many medium/large satellites includes
several of them) are the main objective of the satellite itself.
• The nature and complexity varies in function of the mission objective, although the
tendency is including in each new mission more complex and more on-board
processing demanding payloads, what is leading to more complex and sophisticated
Payload Data architectures:
• Advance imaging processing
• Regenerative/adaptative telecom payloads
• Autonomous payloads for distant missions (exploration)
• …
• This implies that the Payload Data Architecture is increasing in complexity as an
independent system from the platform OBDH architecture. Accordingly components
used for payload data management are more performance demanding: high
performance ADCs, processors, memories,…
ALL of this makes the use of COTS components (screened) more common in nowadays
payload data architectures.
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
• “The data routing function is responsible for passing data from the instruments to the
data storage system, for passing configuration and control information to all of the
instruments and payload data-handling units, and for gathering housekeeping
information from the instruments” [RD12]
• Each instrument generates a different amount of data at a different frequency (from
kbit/s to Gbit/sec) thus changing the management strategy of that data Routing:
• Directly forwarding the data to the payload dedicated or platform mass memory (large amount of data
generated)
• Using a common high-speed network with a central router for all the instruments.
• It is more efficient if all the payload data generated by the various instruments is packet
using a common data format so its data handling (storage) is simplified.
• A dedicated mass storage memory for the payload is common in medium/large missions
generating a significant amount of payload data.
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
• The payload telemetry encoder essentially works in the same way as the platform
telemetry encoder but at significantly higher data rates.
• To manage the entire mass memory operation it is common to have a dedicated
memory controller.
• The memory controller is often based around a general purpose processor since it
receives rather complex commands from the plat-form computer, either via the payload
data bus or via a high-speed serial link.
• There is normally an access path from the platform computer to the mass memory. This
path is used to send housekeeping telemetry packets that are necessary to interpret the
science data properly, like spacecraft attitude and position at regular points in time. For
debugging purposes it is sometimes possible to read out the stored data to the platform
computer.
• Processing of data to support the control or operation of an instrument is normally done
within the instrument itself. An example is data compression. These processing
functions are normally implemented in a separate unit or board within a unit (to
increasing the effective downlink data rate and thereby reduce the time to send the
information to ground).
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
• CubeSat has volume, mass, and power limitations more extreme than in other
satellites. Therefore all subsystems are highly integrated:
• Integration of several subsystems in one hardware element.
• Replace some hardware by software
• Risk is a key parameter: small satellites can assume higher risks compared
to large satellites as the cost is significantly lower. In this way small satellites
can take advantage of the latest technologies improving efficiency, costs and
capabilities, moving fast for including disruptive technologies in their design
and increasing their competitiveness.
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
Considering the large amount of CubeSat developed in the last years and the
one under development and the lack of standardization it is difficult to stablish a
general OBDH architecture for CubeSats.
Nevertheless, in general w.r.t OBDH in CubeSats the OBC absorbs a great part
of the different functions of the OBDH subsystem and it is usually implanted in
1 PCB including mass memory, a microprocessor as central processing unit,
clock , analog interfaces and other subsystem functions (as attitude control
system features or imaging processing features).
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
The layering of CSP corresponds to the same layers as the TCP/IP model. The
implementation consists of a connection oriented transport protocol (Layer 4), a
router-core (Layer 3), and several network-interfaces (Layer 1-2).
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
• Interfaces:
I 2 C master or slave mode ▪ SPI master mode (up to 8 slaves) ▪ 2x UART (RS232 + RS232 / RS485 /
RS422) ▪ General Purpose Input / Output pins (GPIO) ▪ ADC (10-bit, 8 channels) ▪ Pulse Width Modulation
(PWM) ▪ JTAG for programming and debugging ▪ Dedicated debug LEDs and UART ▪ USB host and device
▪ Image Sensor Interface
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
Extracted from
https://gomspace.com/home.aspx
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
Main Features
Performance:
• Perfect for on-board payload data
processing
• Xilinx Zynq 7030 Programmable SoC
• Dual ARM Cortex A9 MPCore up to 800
MHz
• 1 GB DDR3 RAM and 32 GB storage
• Powerful FPGA module – 125k logic
cells
Interfaces:
• Linux operating system
• Requires a NanoDock SDR for
integration into PC104 type stack
Extracted from
• SPI, I2C, UART and CAN data interfaces
https://gomspace.com/home.aspx
• 75 LVDS pairs or 150 CMOS
(combinable)
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
Extracted from
https://gomspace.com/home.aspx
LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
• OrbitalSystems OBC
• Functional Characteristics
• Processing Unit MCU ARM STM32F427 Clock Speed Up to 180 MHz SRAM 256kB internal,
1 MB external Flash Memory 2MB and 2GB shielded external System bus I2C or CAN
• Interfaces
• PC-104 Standard
• I2C, SPI, CAN, USART, Ethernet, USB
• Communication module interface o 2 x UHF com. Interface o Support of IQ Wireless
HISPICO • MEMS 3D Gyro for attitude determination • External Watchdog • Real Time Clock
• PC-104 System Bus Connectors • Designed for CubeSat Kit • ADC channels for external
use
Biography
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LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
Biography
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LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
Biography
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LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
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LESSON 3: CDHS ARCHITECTURE EXAMPLES | PAYLOAD CDHS ARCHITECTURES | OBDH SUBSYSTEM IN CUBESATS
Biography