Geethanjali College of Engineering and Technology

Department of Electronics and Communication Engineering

VLSI Design Objective Question Bank

Unit – I: Introduction to IC Technology

1. According to Moore’s first law, the number of transistors per chip doubles every
(a) 16 months (b) 14 months
(c) 18 months (d) 6 months

2. The p-type substrate used for the fabrication of nMOS devices is

(a) lightly doped (b) moderately doped
(c) heavily doped (d) not doped

3. In pMOS transistor, the current flow is due to _______________

(a) electrons (b) holes
(c) electrons and holes (d) immobile ions

4. The minimum gate voltage required to establish the channel in MOSFET is called
(a) threshold voltage (b) pinch off voltage
(c) early voltage (d) cut off voltage

5. In nMOS inverter, the transistor which is present at the top is called

(a) pull-up transistor (b) push-down transistor
(c) push-up transistor (d) pull-down transistor

6. The potential of the silicon integrated circuit is because of the rapid growth in the
number of ___________ being integrated into circuits on a single chip.
(a) transistors (b) switches
(c) diodes (d) buffers

7. The photoresist layer deposited in the nMOS fabrication process is exposed to

____________
(a) visible light (b) ultraviolet light
(c) infra-red light (d) LED

8. In nMOS transistor, gate material is made up of ____________

(a) silicon (b) polysilicon
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(c) boron (d) phosphorous

9. The source and drain regions in nMOS transistor are isolated by the formation of
____________
(a) a single diode (b) two diodes
(c) three diodes (d) four diodes

10. In depletion mode transistor structure, source and drain regions are connected by
____________
(a) an insulating channel (b) a conducting channel
(c) Vdd (d) Vss

11. What is meant by Lithography?

(a) Process used to transfer a pattern to a layer on the chip
(b) Process used to develop an oxidation layer on the chip
(c) Process used to develop a metal layer on the chip
(d) Process used to produce the chip

12. In nMOS and CMOS fabrication processes, silicon dioxide is patterned on the silicon
substrate using ____________
(a) physical lithography
(b) photolithography
(c) chemical lithography
(d) mechanical lithography

13. In MOSFET, the body effect is considered when the substrate terminal is biased with
respect to ___________
(a) source (b) drain
(c) gate (d) Vss

14. On increasing the substrate to source voltage in MOSFET, the threshold voltage of
the device
(a) does not affect (b) decreases
(c) increases (d) exponentially increases
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VLSI Design Objective Question Bank

15. The parameter transconductance (gm) in MOSFET gives the relationship between
___________
(a) input current and output voltage
(b) output current and input voltage
(c) input current and input voltage
(d) output current and output voltage

16. The drain current Ids in MOSFET is _______ to width (W) of the channel
(a) directly proportional
(b) inversely proportional
(c) not related
(d) logarithmically related

17. The switching speed of a MOSFET device depends on the following parameter(s).
(a) gate voltage above a threshold
(b) carrier mobility
(c) length of channel
(d) all of the above

18. Surface mobility of charge carriers in MOSFET device depends on ___________

(a) effective drain voltage (b) effective gate voltage
(c) channel length (d) effective source voltage

19. When the size of the die shrinks, the complexity of making the masks for fabrication
____________
(a) increases (b) decreases
(c) remains the same (d) cannot be determined

20. The condition of MOSFET for operating in non-saturated region is?

(a) Vds = Vgs – Vt (b) Vgs lesser than Vt
(c) Vds less than Vgs – Vt (d) Vds greater than Vgs – Vt

21. The condition of MOSFET for operating in saturated region is?

(a) Vds less than Vgs – Vt (b) Vds greater than Vgs – Vt
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(c) Vgs = Vds = 0 (d) Vgs = Vds = Vs = 0

22. The structure of MOSFET device is ____________

(a) symmetrical (b) non symmetrical
(c) semi symmetrical (d) pseudo symmetrical

23. The mobility of electrons is approximately ___________ than the mobility of holes.
(a) 2.5 times greater (b) 2.5 times smaller
(c) 1.5 times greater (d) 1.5 times smaller

24. Inversion layer formed in nMOS enhancement mode transistor consists of

____________
(a) positive carriers (b) negative carriers
(c) both in equal quantity (d) neutral carriers

25. Electron transit time in a MOSFET device is given by __________

(a) L / v (b) v / L
(c) v x L (d) v x d

Answer Key:

1. (c) 2. (b) 3. (b) 4. (a) 5. (a) 6. (a) 7. (b)

8. (b) 9. (b) 10. (b) 11. (a) 12. (b) 13. (a) 14. (c)

15. (b) 16. (a) 17. (d) 18. (b) 19. (a) 20. (c) 21. (b)

22. (a) 23. (a) 24. (b) 25. (a)

Unit – II: MOS Circuit Design Processes

1. Which of the following is used to convey layer information through the use of color
code?
(a) Layout (b) Stick Diagram
(c) Photo Mask (d) Schematic

2. The process of verifying the functionality of a given circuit is called as

(a) synthesis (b) debugging
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(c) simulation (d) verification

3. The process of generating Net list is called as

(a) synthesis (b) debugging
(c) simulation (d) verification

4. ________________ is used to check the dimensions of the Layout

(a) LVS (b) GDSII
(c) RC Extraction (d) DRC

5. Which of the following tool is used to encrypt the design to protect from the mediator?
(a) LVS (b) GDSII
(c) RC Extraction (d) DRC

6. _____________ is used to compare Layout with Schematic.

(a) LVS (b) GDSII
(c) RC Extraction (d) DRC

7. GDSII stands for -------------------

(a) Graphical Design Stream Information Interchange
(b) Graphical Data Stream Information Interchange
(c) Graphical Data Stream Interchange Information
(d) Graphical Design Stream Interchange Information

8. In stick diagrams, which color is used to represent polysilicon?

(a) Green (b) Yellow
(c) Red (d) Blue

9. Which color is used to represent implant in stick diagrams?

(a) Green (b) Yellow
(c) Red (d) Blue

10. Ion implantation is used in ---------------

(a) Enhancement type NMOS Fabrication
(b) Bi-CMOS fabrication
(c) CMOS fabrication
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(d) Depletion type of NMOS fabrication

11. As per λ based design rules, the minimum separation between any diffusion and
polysilicon is --------
(a) 5λ (b) 3λ (c) 1λ (d) 4λ

12. As per λ based design rules; width of Metal 2 is --------

(a) 5λ (b) 3λ (c) 1λ (d) 4λ

13. ‘Via’ is used to connect ---------------

(a) metal 2 with poly (b) metal 1 with poly
(c) metal 2 with metal 1 (d) metal 1 with diffusion

14. Which contact is used to connect Poly. to diffusion using metal.

(a) Cut (b) Butting contact
(c) Buried contact (d) Via

15. Buried contact is used to connect--------------

(a) Poly. to Metal and Metal to diffusion
(b) Poly. to diffusion using metal
(c) Metal to Poly.
(d) Poly. to diffusion

16. Which of the following is true?

(a) Poly. and diffusion can cross the Demarcation line
(b) Poly. and diffusion should not cross the Demarcation line
(c) Poly. and metal can cross the Demarcation line
(d) diffusion and metal can cross the Demarcation line

17. ___________ is the representation of an IC in terms of planar geometric shapes

which corresponds to diffusion, poly, metal etc.,
(a) Layout (b) Stick Diagram
(c) Photomask (d) Schematic

18. The Boolean expression Y= (A+B+C)’ represents

(a) two input OR gate (b) three input EXOR gate
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(c) three input NOR gate (d) two input NAND gate

19. How many depletion type NMOSFETs are required to realize the Boolean expression
Y= (A+B) +(C+D) using NMOS logic?
(a) 1 (b) 6 (c) 8 (d) 4

20. In stick diagrams, which color is used to represent contact cut?

(a) Black (b) Yellow
(c) Red (d) Blue

21. The Boolean expression Y= ((a)(b) C)’ represents

(a) two input OR gate
(b) three input EXOR gate
(c) three input NOR gate
(d) three input NAND gate

22. In stick diagrams, which color is used to represent Buried contact?

(a) Black
(b) Yellow
(c) Red
(d) Brown

23. Which of the following is true?

(a) PMOSFETs and NMOSFETS should be below Demarcation line
(b) PMOSFETs and NMOSFETS should be above Demarcation line
(c) NMOSFETS should be below Demarcation line and PMOSFETs should be above
Demarcation line
(d) NMOSFETS should be above Demarcation line and PMOSFETs should be below
Demarcation line

24. How many depletion type PMOSFETs are required to realize the Boolean expression
Y= (A+B) using CMOS logic?
(a) 1
(b) 3
(c) 8
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(d) 4

25. As per λ based design rules; the dimension of implant is --------

(a) 5λ X 5λ
(b) 6λ X 6λ
(c) 3λ X 3λ
(d) 2λ X 2λ

Answer Key:

1. (b) 2. (c) 3. (a) 4. (d) 5. (b) 6. (a) 7. (b)

8. (c) 9. (b) 10. (d) 11. (c) 12. (d) 13. (c) 14. (b)

15. (a) 16. (c) 17. (a) 18. (c) 19. (a) 20. (a) 21. (d)

22. (d) 23. (c) 24. (b) 25. (b)

Unit – III: Subsystem Design

1. The propagation delay (tpHL) is the delay when output switches from
(a) Low to Low (b) High to Low
(c) High to High (d) Low to High

2. What is the impact of the high number of fanout on gate propagation delay?
(a) It decreases (b) It remains constant
(c) It substantially increases (d) It does not depend

3. What is the inverter pair delay for inverters having 4: 1 ratio?

(a) 4RC (b) 5RC
(c) 6RC (d) 7RC

4. ________ capacitance is due to parallel fine metal lines running across the chip for
power connection.
(a) Interlayer (b) Wiring
(c) Fringing field (d) Parallel plate

5. The time necessary to change the output voltage by an amount that is equal to the
input change is given by
(a) CL/gm (b) 2CL*gm
(c) 2CL/gm (d) CL*gm
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VLSI Design Objective Question Bank

6. The overall propagation delay for cascaded pass transistors is given by, τd= ?
(a) 4n2rc (b) 3n2rc
(c) 2n2rc (d) n2rc

7. Interlayer capacitance does not depend on ___________

(a) separation between plates
(b) electric field between plates
(c) density of the material
(d) parallel plate effect

8. Total diffusion capacitance is equal to ___________

(a) peripheral capacitance
(b) area capacitance + peripheral capacitance
(c) area capacitance + fringing field capacitance
(d) peripheral capacitance + fringing field capacitance

9. Peripheral capacitance for 2 micrometer process is in the order of

_________ per micrometer.
(a) nano farad (b) pico farad
(c) micro farad (d) farad

10. For greater relative value of peripheral capacitance ___________ should be small.
(a) metal length (b) polysilicon layer area
(c) source and drain area (d) channel area

11. The subsystem of the circuits should have ______ interdependence.

(a) minimum (b) maximum
(c) no (d) more

12. The Switch logic is based on.

(a) pass transistors (b) transmission gates
(c) pass transistors and transmission gates (d) design rules

13. The switch logic approach takes _____ static current.

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(a) low (b) more

(c) no (d) very less

14. The CMOS inverter has _____ power dissipation.

(a) low (b) more
(c) no (d) very less

15. In CMOS NAND gate, p transistors are connected in

(a) series (b) parallel
(c) cascade (d) random

16. Which can handle high capacitance load?

(a) NAND (b) nMOS NAND
(c) CMOS NAND (d) BiCMOS NAND

17. In Pseudo-nMOS logic, n transistor operates in?

(a) cut off region (b) saturation region
(c) resistive region (d) non saturation region

18. In dynamic CMOS logic _____ is used.

(a) two phase clock (b) three phase clock
(c) one phase clock (d) four phase clock

19. In clocked CMOS logic, output in evaluated in

(a) on period (b) off period
(c) both periods (d) half of on period

20. CMOS domino logic is same as ______ with inverter at the output line
(a) clocked CMOS logic (b) dynamic CMOS logic
(c) gate logic (d) switch logic

21. CMOS domino logic has

(a) smaller parasitic capacitance (b) larger parasitic capacitance
(c) low operating speed (d) very large parasitic capacitance
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VLSI Design Objective Question Bank

22. Features of switch logic approach

(a) occupies more area (b) no undesirable threshold
voltage
(c) low power dissipation (d) all the above

23. When one pass transistor is driven using another, threshold voltage
__________ the logic levels
(a) affects (b) does not affect
(c) does not alter (d) greatly impacts

24. When two or more cuts of same type cross or touch each other, that
represents ____________
(a) contact cut (b) electrical contact
(c) like contact (d) cross contact

25. The n-MOS transistor is made up of:

(a) N-type source, n-type drain and p-type bulk
(b) N-type source, p-type drain and p-type bulk
(c) P-type source, n-type drain and n-type bulk
(d) P- type source, p-type drain and n-type bulk

Answer Key:

1. (b) 2. (c) 3. (b) 4. (c) 5. (a)

6. (d) 7. (c) 8. (b) 9. (b) 10. (c)
11. (a) 12. (a) 13. (a) 14. (a) 15. (b)
16. 17. (b) 18. (d) 19. (a) 20. (b)
(d)
21. 22. (d) 23. (a) 24. (b) 25. (a)
(a)
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Unit – IV: Data path Subsystems

1. Why is Static RAM preferable for volatile memory?

(a) low-cost (b) high-speed
(c) low power consumption (d) Less area per bit

2. What is the storage element used in Dynamic RAM?

(a) Inductor (b) Capacitor
(c) Resistor (d) MOSFET

3. Which one of the following is used for designing the cell in Static RAM?
(a) Capacitor (b) Inductor
(c) Transistor (d) Resistor

4. Frequent refreshing of data is needed in which of the below memories?

(a) SRAM (b) DRAM
(c) Flash memory (d) EPROM

5. ROM has the capability only to perform _____________

(a) write operation only
(b) read operation only
(c) both write and read operation
(d) erase operation

6. ROM is constructed using ___________

(a) Flip flops (b) Registers
(c) Decoder and NOR gates (d) Inverters

7. The full form of CAM is

(a) Carry and Multiply
(b) Content Addressable Memory
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(c) Content Additive Memory

(d) Cache Memory
8. The important factor to be considered for assessment of storage elements is
(a) memory access time
(b) address of a memory location
(c) data at a particular memory location
(d) shape of the memory

9. A single cell in Static RAM consists of ____________ transistors.

(a) ten (b) twelve
(c) six (d) two

10. Which one of the following is not an example of Serial Access Memory?
(a) Shift register (b) FIFO
(c) LIFO (d) Decoder

11. In circular shift operation, for a four bit word, a one-bit shift right is equivalent to
(a) one bit shift left
(b) two bit shift left
(c) three bit shift left
(d) four bit shift left

12. The heart of the ALU is

(a) Register (b) Memory
(c) Adder (d) I/O port

13. In Manchester carry chain element, the carry path is gated by a ____________
(a) cross bar switch (b) transmission type switch
(c) bus interconnection (d) pass transistor

14. Carry look ahead logic uses the concepts of ___________

(a) inverting the inputs
(b) complementing the outputs
(c) generating and propagating carries
(d) ripple factor
15. A magnitude comparator is defined as a digital comparator which has ____________
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VLSI Design Objective Question Bank

(a) only one output terminal

(b) two output terminals
(c) three output terminals
(d) no output terminal

16. For the bit pattern 10101011 the even and odd parity bits to be added are
(a) 0 and 1 (b) 1 and 0
(c) 1 and 1 (d) 0 and 0

17. Which of the following options is preferred for designing n-bit adder?
(a) many pass transistors in series
(b) many pass transistors with suitable buffer
(c) many pass transistors without suitable buffer
(d) many pass transistors in parallel

18. In the design of adders, the previous carry can be obtained from ____________
(a) propagate signal pk
(b) generate signal gk
(c) pk and gk
(d) sk

19. Manchester carry chain is a?

(a) chain of controlled inverter
(b) variation of a carry-look ahead adder
(c) variation of a full adder
(d) variation of a ripple carry adder

20. The main disadvantage of Manchester carry chain is ___________

(a) ripple factor
(b) propagation delay
(c) capacitive load
(d) both propagation delay and capacitive load
21. The key advantage of Ripple counter is____________
(a) easy to design
(b) propagation delay is huge
(c) power consumption is high
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(d) transistor count is high

22. 4-bit Zero’s detector consists of ______NOR gates

(a) 5 (b) 4 (c) 3 (d) 2

23. Ripple counters are also called ____________

(a) SSI counters
(b) Asynchronous counters
(c) Synchronous counters
(d) VLSI counter

24. Multipliers are built using

(a) binary adders (b) binary subtractors
(c) dividers (d) multiplexers

25. Which method is suitable for larger operands?

(a) Baugh-wooley algorithm
(b) Wallace trees
(c) Dadda multipliers
(d) Modified booth encoding

Answer Key:
1. (b) 2. (b) 3. (c) 4. (b) 5. (b)
6. (c) 7. (b) 8. (a) 9. (c) 10. (d)
11. (c) 12. (c) 13. (d) 14. (c) 15. (c)
16. 17. (b) 18. (c) 19. (b) 20. (d)
(b)
21. 22. (c) 23. (b) 24. (a) 25. (b)
(b)

Unit – V: Design Methodology

1. A MOS Programmable Logic Array device is realized by using the gate

(a) NOR (b) XOR
(c) AND (d) NOR
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2. A macro cell in CPLD is composed of

(a) J-K flip-flop (b) R-S-Flip-flop
(c) T –flip-flop (d) D-flip-flop

3. The full form of CPLD is

(a) Computer Programmable Logic Delay
(b) Complementary Peripheral Logic Device
(c) Computer Peripheral Logic Delay
(d) Complex Programmable Logic Device

4. Logic gates are placed in rows of standard cells of

(a) equal height (b) equal width
(c) variable height (d) constant width

5. The following is not a parameter that influences low power design

(a) Supply voltage
(b) Frequency of Operation
(c) Load capacitance
(d) Dimensions of the chip

6. Ease of observing a node by watching external output pins of the chip is called
(a) observability (b) controllability
(c) testability (d) All of them

7. _________ is tested by using design rule checker.

(a) Functionality (b) Layout
(c) Routing (d) Signal-integrity

8. The type of PLD should be used to program basic logic functions?

(a) PLA (b) PAL
(c) CPLD (d) SLD

9. Programmable Array Logic (PAL) contains ____________

(a) programmable AND, Fixed OR planes
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(b) programmable AND, programmable OR planes

(c) Fixed AND, Fixed OR planes
(d) Fixed AND, programmable OR planes

10. To check whether the design is meeting the timing-requirements ___________ is

performed.
(a) functional verification
(b) static timing analysis
(c) netlist-level Power Analysis
(d) LVS

11. In FPGA, vertical and horizontal directions are separated by ____________

(a) a line (b) a channel
(c) a strobe (d) a flip-flop

12. A Programmable Logic Array is similar to Read Only Memory in concept except that
____________
(a) It does not provide the capability to read only
(b) It does not provide the capability to read or write operation
(c) It does not provide full decoding to the variables
(d) It does not provide the capability to write only

13. The circuit should be tested at

(a) design level (b) chip level
(c) transistor level (d) switch level
14. In prototype testing, the circuits are ___________ for partitioning into subsystems.
(a) open circuited (b) short circuited
(c) tested as a whole circuit (d) programmed

15. Test pattern generation is assisted using

(a) automatic test pattern generator
(b) exhaustive pattern generator
(c) repeated pattern generator
(d) loop pattern generator

16. Observability is the process of

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(a) checking all inputs (b) checking all outputs

(c) checking all possible inputs (d) checking errors and performance

17. Buffers are needed to drive

(a) small capacitance (b) large capacitance
(c) small resistance (d) large resistance

18. Bonding pads are placed

(a) inside the chip (b) exactly at the centre of chip
(c) at the edge of the chip (d) above the chip

19. Testability of circuit in VLSI Design aims at

(a) facilitating test generation (b) facilitating test application
(c) avoiding timing problems (d) all the above

20. Partitioning should be made on a

(a) logical basis (b) functional basis
(c) time basis (d) structural basis

21. The design technique helps in improving

(a) controllability (b) observability
(c) controllability and observability (d) overall performance

22. Which signal is particularly employed to control the scan path movement
(a) Clock signal (b) Input signal
(c) Output signal (d) Delay signal

23. Which is not the function of LSSD method?

(a) Eliminates hazards
(b) Eliminates races
(c) Simplifies fault generation
(d) Stores the data

24. Signature analysis performs

(a) Addition (b) Multiplication
(c) Polynomial division (d) Amplifies
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25. Linear Feedback Shift Register circuit comprises of ____________

(a) AND gates (b) EX-OR gates
(c) OR gates (d) EX-OR gates and Flipflops

Answer Key:
1. (a) 2. (d) 3. (d) 4. (a) 5. (d)
6. (a) 7. (b) 8. (b) 9. (a) 10. (b)
11. (b) 12. (c) 13. (b) 14. (a) 15. (a)
16. 17. (b) 18. (c) 19. (d) 20. (a)
(b)
21. (c) 22. (a) 23. (d) 24. (c) 25. (d)