Pioneer Avh-P7500dvd crt3112

Service
Manual AVH-P7500DVD/UC
ORDER NO.
CRT3112
7 INCH WIDE FULLY MOTORIZED LCD COLOR DISPLAY WITH 5 CHANNEL HIGH-POWER DVD/VCD/CD RECEIVER
AVH-P7500DVD UC,EW
- This service manual should be used together with the following manual(s):
Model No. Order No. Mech. Module Remarks
AVH-P7500DVD CRT3039 SAFETY INFORMATION, SPECIFICATIONS,
/UC,EW EXPLODED VIEWS AND PARTS LIST,
BLOCK DIAGRAM AND SCHEMATIC DIAGRAM,
PCB CONNECTION DIAGRAM and ELECTRICAL PARTS LIST
CX-3016 CRT3056 MS3 DVD Mech. Module:Circuit Description, Mech.Description, Disassembly
NOTE:
- Manufactured under license from Dolby Laboratories. "Dolby" and the double-D symbol are trademarks of Dolby
Laboratories.
- Inverter for LCD back light becomes a high voltage.
For details, refer to "Important symbols for good services".
PIONEER CORPORATION 4-1, Meguro 1-Chome, Meguro-ku, Tokyo 153-8654, Japan

PIONEER ELECTRONICS (USA) INC. P.O.Box 1760, Long Beach, CA 90801-1760 U.S.A.
PIONEER EUROPE NV Haven 1087 Keetberglaan 1, 9120 Melsele, Belgium
PIONEER ELECTRONICS ASIACENTRE PTE.LTD. 253 Alexandra Road, #04-01, Singapore 159936
C PIONEER CORPORATION 2003 K-ZZU. JUNE 2003 Printed in Japan

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A [ Important symbols for good services ]

In this manual, the symbols shown-below indicate that adjustments, settings or cleaning should be made securely.
When you find the procedures bearing any of the symbols, be sure to fulfill them:
1. Product safety
You should conform to the regulations governing the product (safety, radio and noise, and other regulations), and
should keep the safety during servicing by following the safety instructions described in this manual.
2. Adjustments
To keep the original performances of the product, optimum adjustments or specification confirmation is indispensable.
In accordance with the procedures or instructions described in this manual, adjustments should be performed.
B
3. Cleaning
For optical pickups, tape-deck heads, lenses and mirrors used in projection monitors, and other parts requiring cleaning,
proper cleaning should be performed to restore their performances.
4. Shipping mode and shipping screws
To protect the product from damages or failures that may be caused during transit, the shipping mode should be set or
the shipping screws should be installed before shipping out in accordance with this manual, if necessary.
5. Lubricants, glues, and replacement parts

Appropriately applying grease or glue can maintain the product performances. But improper lubrication or applying
C glue may lead to failures or troubles in the product. By following the instructions in this manual, be sure to apply the
prescribed grease or glue to proper portions by the appropriate amount.For replacement parts or tools, the prescribed
ones should be used.
- DVD Player Service Precautions

1. Before disassembling the unit, be sure to turn off the power. Unplugging and plugging the connectors during
power-on mode may damage the ICs inside the unit.
2. To protect the pickup unit from electrostatic discharge during servicing, take an appropriate treatment (shorting-sol-
D
der) by referring to “ the DISASSEMBLY” on page 49.
3. Please adjusting the skew after changing the pickup unit(see page 8).
4. During disassembly, be sure to turn the power off since an internal IC might be destroyed when a connector is
plugged or unplugged.
2 AVH-P7500DVD/UC
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CONTENTS A
6. ADJUSTMENT.................................................................................................................4
6.1 JIG CONNECTION DIAGRAM................................................................................4
6.2 DVD ADJUSTMENT ...............................................................................................5
6.3 MAIN VIDEO LEVEL ADJUSTMENT ...................................................................25
6.4 MONITOR PCB ADJUSTMENT ...........................................................................27
6.5 INVERTER PCB ADJUSTMENT ...........................................................................31
6.6 MOTHER PCB ADJUSTMENT .............................................................................32
6.7 TUNER SELECTOR UNIT ADJUSTMENT(UC model)........................................34
6.8 TV TUNER UNIT(UC model)................................................................................36
B
6.9 MONITOR TEST MODE........................................................................................39
6.10 TOUCH PANEL CALIBRATION...........................................................................44
6.11 SYSTEM MICROCOMPUTER TEST PROGRAM ...............................................48
7. GENERAL INFORMATION ............................................................................................49
7.1 DIAGNOSIS...........................................................................................................49
7.1.1 DISASSEMBLY.............................................................................................49
7.1.2 PCB LOCATIONS .........................................................................................55
7.1.3 CONNECTOR FUNCTION DESCRIPTION ..................................................56
7.2 PARTS....................................................................................................................59
C
7.2.1 IC...................................................................................................................59
7.2.2 DISPLAY .....................................................................................................100
7.3 OPERATIONAL FLOW CHART ...........................................................................101
7.4 CLEANING ..........................................................................................................102
8.OPERATIONS................................................................................................................103
AVH-P7500DVD/UC 3
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A 6. ADJUSTMENT
6.1 JIG CONNECTION DIAGRAM
DVD Mechanism Module(MS3)
After connecting a tuner selector unit , please perform adjustment.
Function Name Jig No.

Mother PCB(CN451) <-> Main Unit(CN3801) PCB GGF1471
Mother PCB(CN451) <-> GGF1471 50P FFC GGD1250
E Mother PCB(CN452) <-> GGF1471 24P FFC GGD1337
Mother PCB(CN451,CN452) <-> Monitor PCB(CN4461,CN4481) PCB GGF1472
Monitor PCB(CN4461) <-> GGF1472 33P FFC GGD1288
Monitor PCB(CN4481) <-> GGF1472 24P FFC GGD1337
Mother PCB(CN421) <-> Panel PCB(CN5901) 17PFFC GGD1124
Mother PCB(CN503) <-> DVD Core Unit(MS3)(CN993) 13PFFC GGD1138
4 AVH-P7500DVD/UC
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6.2 DVD ADJUSTMENT A
If the reference voltage is connected to GND by mis-

1) Precautions take, turn the regulator OFF immediately, or turn the
This product uses 5V and 3.3V as standard voltages. power OFF.
The electrical potential that is the reference for signals, • Remove the filters and wires used for measurements
is not GND, but VREF (approximately 2.2V) and VHALF only after the regulator has been turned OFF.
(approximately 1.65V). • After the power supply is turned on, regulator ON the
During product adjustments, if the reference voltage is following adjustment and measurement are promptly
mistakenly taken as GND, and a grounding contact is done.
made, not only would it be impossible to measure the • Whenever the product is in the test mode, the software
accurate electrical potential, but also the servo motor will not take any protective action. For this reason, B
would malfunction, resulting in the application of a special care should be taken to make sure that no
strong impact on the pick up. The following precaution- mechanical or electrical shock could be applied to the
ary measures should be strictly adhered to, in order to product when taking measurements in the test mode.
avoid such problems. • Whenever the EJECT key is pressed to eject the disk,
The reference voltage and GND should not be confused no other keys, other than the EJECT key, should be
when using the minus probe of a measurement device. pressed until the disk eject action has been complet-
When an oscilloscope is being used special care should ed.
be taken to make sure that the reference voltage is not • Press the EJECT key only after the disk has stopped
connected to the probe of ch1 (on the minus side), completely.
while the probe of ch2 (on the minus side), is connected • If the product hangs up turn the power OFF immedi-
to GND. Further, since the body frame of most mea- ately.
surement devices have the same electrical potential as • Laser didoes may be damaged, if the volume switch for C
the minus side of the probe, the body frame of the mea- the laser power adjustment of the pick up unit, is turned.
surement device should be set to floating ground.
Attention)
• Test mode starting procedure
ACC ON while pressing the ANGLE- and EQ keys together.
• Test mode stopping procedure
ACC and Backup OFF.
AVH-P7500DVD/UC 5
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A - Front-End test mode flow chart
Start test mode

Test mode In
Note 1: At this stage select the media type. Various settings are carried out
according to the media selection made here.
Note 2: While measurements are being taken, only the operation, for which
Set source to DVD the measurement is being taken, is allowed.
Note 3: Reproduction (play) speed is selectable from
TEST DVD: x 1CLV ↔ x 1.3CLV, CD x 2CLV
RIGHT LEFT REAR
FE EDC1 EDC2
B test mode mode mode
0X00 0000 LEFT : DVD, single-layer
REAR : DVD, dual-layer
RIGHT LEFT~ATT EJECT Power off condition
BACK/TEXT: CD
FE offset coefficient
Power On Disc Type Eject ATT : CD-RW
TE offset coefficient (Note 1)
AS offset coefficient
ENV offset coefficient
TG offset coefficient
0FFF 0000 0000 0000 Power on condition
DBALt coefficient
1X00 0000 1A00 0000 LEFT
EQ RIGHT REAR BACK/TEXT ATT ANGLE-
Focus Search
Power Off Focus close CRG + CRG – LD_ON CRG_HOME
adjustment 1100 0000 LEFT
FE MAX level
FE MIN level
AS MAX level Focus Search
ENV MAX level 1FFF 0000 LD_ON :1100 0000
C FE normalization feature
Stop 1B00 0000 1C00 0000 1D00 0000
LD_OFF:1000 0000
Spindle gain coefficient
TEMAX level
TEMIN level EQ RIGHT LEFT REAR BACK/TEXT
T.Bal and Focus close condition 1
Power Off Focus Jump CRG + CRG –
other
adjustments
TBAL Coefficient(Layer 0) Layer L0:2000 0000 Operation while key is being pushed. Operation while key is being pushed.
2FFF 0000
TBAL Coefficient(Layer 1) Layer L1:2100 0000 2B00 0000 2C00 0000
TE normalization feature
(Layer0) Focus close condition 2
TE normalization feature EQ 3000 0000 RIGHT REAR BACK/TEXT
(Layer1)
Power Off Tracking close CRG + CRG –
adjustment
FBAL Coefficient(Layer0) 3FFF 0000 Operation while key is being pushed. Operation while key is being pushed. Tracking close condition
FBAL Coefficient(Layer1) 4000 0000 3B00 0000 3C00 0000
Focus Gain Coefficient(Layer0)
Focus Gain Coefficient(Layer1) 4X00 0000 REAR, ANGLE+
D Tracking Gain Coefficient(Layer0) EQ RIGHT LEFT ATT ANGLE- BACK/TEXT
Tracking Gain Coefficient(Layer1)
Power Off Error Rate Reproduction Focus Jump
AS normalization adjustment feature ID Search T. Jump Tracking
(Layer0) measurement speed switching
AS normalization adjustment feature
(Note 2) +/– Open
(Layer1) (Note 3)
Error Rate 4A00 0000 REAR Jump+:
DVD x 1CLV Layer L0:4X00 0000
DVD x 1.3CLV Layer L1:4X00 0000 4B00 0000
Tracking Gain Coefficient(Layer0)
CD x 2CLV
Tracking Gain Coefficient(Layer1) 4X00 0000 RIGHT ID Track number
~

(Layer0)
BACK/TEXT specification specification
(Layer1) ID display Track
number
ATT display BACK/TEXT
ID Jump start
Search Start
E
6 AVH-P7500DVD/UC
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EDC1 EDC2 A
mode mode
0000 0000 0000 0000
RIGHT LEFT RIGHT LEFT
Layer 0 Layer 1 Layer 0 Layer 1
selected selected selected selected
0000 0000 0100 0000 0000 0000 0100 0000
1003 0000 1103 0000 1003 0000 1103 0000
RIGHT RIGHT
~
~
BACK/TEXT BACK/TEXT
Layer0:10** **** Layer0:10** ****

ID Layer1:11** **** ID Layer1:11** ****
designation ** ****: ID specification value designation ** ****: ID specification value
B
ATT ATT
Layer0:20** **** Layer0:20** ****
EDC1 start Layer1:21** **** EDC2 start Layer1:21** ****
** ****: Present ID value ** ****: Present ID value
F-close and F-search cannot be executed, unless LD-ON is set.

[If F-close isn't executed within 9 seconds after LD-ON,
it switches to LD-OFF automatically. And even if F-search is executed
within 9 seconds after LD-ON, it also switches to LD-OFF.]
The track number designation is selected from the track numbers already prepared for selection.
Switching to cyclic operation is made at step REAR, and the decision is finalized (entered) in step BACK/TEXT.
For CD: Tracks 1, 4, 10, 11 and 32. C
For DVD: Tracks 1, 4, 10, 11, 32, 64 and 100.
Method for designating an ID address:

• A number of digits are determined through commands RIGHTand LEFT. Numerical UP/DOWN operations are performed
through commands REAR and BACK/TEXT. The decision is finalized (entered) with command ATT.
OSD display
Error Code List
Error status from
DVD micurocomputer Contents Display D
0X50 Mecha. error No dislay
0X40 No disc No dislay
0X30 The temperature is abnormal Thermal Protection in Motion
0X20 Read error Error-02-XX
0XE2 Non-playable disc NON-PLAYABLE DISC
0X90 Drrerent region disc DFFERENT REGION DISC
0XFF Undefined error Error-FF
Error code of read error(Part of XX)
Error Code Contents Display

E
0X99 Data cannot read Please condirm the disc
0X80 The address cannot be found Please condirm the disc
0X90 Focus error Please condirm the disc
0X91 Spindle lock NG DVD is stopping because mechanism detected abnormality
0X92 Carrige home NG DVD is stopping because mechanism detected abnormality
0X93 FOK error Please condirm the disc
0X94 ID/Subcode cannot be read Please condirm the disc
0X95 High spindle rotation Please condirm the disc
0X96 Row spindle rotation DVD is stopping because mechanism detected abnormality
0X98 TOC cannot be found Please condirm the disc
0X9A AV chip error DVD is stopping because mechanism detected abnormality
0X9B RecaveryNG(BE) DVD is stopping because mechanism detected abnormality F
AVH-P7500DVD/UC 7
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A - Skew adjustment
If any of the following replacements have been performed on the system, adjustments for pick up,
must be conducted:
1. Pick up unit replacement
2. Spindle motor replacement
3. Carriage chassis replacement
4. Pick up unit main shaft replacement
5. Pick up unit sub-shaft replacement
Measurement device and tools : Oscilloscope

B Allen key wrench
40-pin flexible extension
Screw rock(GYL1001)
Disk used : GGV1018

Measurement reference : GND1
Measurement point : RFOUT
Skew adjustment connection diagram

• DVD core unit (MS3)
IC1101
Oscilloscope
D RFOUT
IC1706
GND1
COMPO
GNDV
8 AVH-P7500DVD/UC
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Symptoms in case of poor adjustment: Error efficiency deteriorated: 10-3 (Optimum value: 10-4 or lower)
High jitter of the RF signal A
RF waveform deformed
Unstable operation in tracking closing and servo control
Caution: Avoid exposing your eyes to laser beams for a long time.
Preparation for adjustment: Clean both ends of the shafts.
Use brand new skew screws supplied with the service kit CXX1639.
Procedures:
1. Place the DVD mechanism module upside down.
2. After replacing the pickup (by referring to the procedures of “Removing the Pickup.”),
roughly adjust the three skew screws through visual check so that the pickup is mounted in parallel
to the CRG chassis around the inner and outer tracks.
3. Connect an oscilloscope as shown in the connecting diagram.
B
4. Turn on the power of the product. Load the test disc (GGV1018).
5. In the front-end test mode, set the disc type to DVD layer 1. Move the pickup toward the inner tracks.
6. Turn on the laser diodes.
7. With the focus servo closed, complete all automatic adjustments. Close the tracking servo, and
then complete all automatic adjustments.
8. Observing the RF waveform on the oscilloscope, slightly turn the skew adj. screw C to maximize the RF level.
Next, move the pickup toward the outer tracks. Slightly turn the skew adj. screw B to maximize the RF level.
Turn the skew adj. screws A and B in the same direction keeping their rotating angles the same until the RF level
becomes the maximum.
Lastly, move the pickup toward the inner tracks. Turn the skew adj. screw C so that the RF level
becomes the maximum.
Repeat the step 8 three times.
9. Turn off the power in the test mode. After confirming that the disc has stopped, eject the disc. C
10. Apply glue to the skew adj. screws and the shafts.
Skew adj. screw Skew adj. screw

Apply glue
Shaft
Prevent applied glue Prevent applied glue D
from extending beyond this position. from extending beyond this position.
B
E
AVH-P7500DVD/UC 9
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- Back end section check flow chart
Start
A
Are all
reproduced images and NO
sounds normal?
YES
NO Go to the F.E.
Is the F.E. section
normal? section check
B YES
Are all NG
power supply
voltages
OK
Are all NG
clocks operating
normally?
C OK
Is
the NG
streaming I/F
OK
Is the audio NG
circuit operating normally?
OK
D
Is
the video NG
circuit operating
normally?
OK
Is
SDRAM NG
I/F operating
normally?
OK
E
Is
the microprocessor Repair or replace
operating normally? any defective unit
NO
All checks normal?
YES
F Check
completed
10 AVH-P7500DVD/UC
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Check 1: Are all power supply voltages normal? A

Reproduce DVD-REF-A1 Title 1.
Verify the voltage of the sensing pin.
If results are not satisfactory, check to see if there are any problems with the resin flux cored solder,
parts and components.
NO. Verification location Rated value Unit

1 VD8-PGND 8±0.4 V
B
2 VD33-GND 3.3±0.3 V
3 SRVDD33-GND 3.3±0.3 V
4 VCC5-GND 5±0.25 V
5 AVCC5-GND 5±0.3 V
6 VCC33-GND 3.3±0.15 V
7 VCC18-GND 1.8±0.15 V
8 VCC25-GND 2.5±0.2 V
AVH-P7500DVD/UC 11
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A
Check 2: Are all clocks operating normally?
Checks are to be conducted with a GND reference.
If locations listed under "verification location 2", can be verified, there will be no need to perform verifications
for the locations listed under "verification location 1."
If the result is not satisfactory, check to see if there are any problems with the resin flux cored solder,
parts and components, in the vicinity of IC1507.
Verification Verification
NO. location 1 location 2 Media Rated value1 Rated value 2 Rated value 3
B (contact
measurements)
1 CLK27 IC1503 96pin ALL 2.65V~VCC33 GND~0.65V 27MHz±50ppm
2 EXTCK1 IC1503 100pin DVD 2.65V~VCC33 GND~0.65V 36.8640MHz±100ppm
3 EXTCK1 IC1503 100pin CD 2.65V~VCC33 GND~0.65V 33.8688MHz±100ppm
4 MCK16 IC1301 79pin ALL 2.33~VCC33 GND~0.99V 16.9344MHz±100ppm
5 MCK33 IC1601 3,33pin ALL 2.33~VCC33 GND~0.10V 33.8688MHz~40.0000MHz
C
Rated value 1 Rated value 3
GND Rated value 2
Clock rated values
12 AVH-P7500DVD/UC
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Clock generator
MPEG stream
System Computer I/F
AVH-P7500DVD/UC 13
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A
Check 3: Is the streaming I/F operating normally?
Checks are to be conducted with a GND reference.
If the locations listed under "verification location 2" can be verified, then there is no need to conduct verifications
for the locations listed under "verification location 1."
If the result is not satisfactory, check to see if there are any problems with the resin flux cored solder, parts
and components, in areas where a problem occurs, for the overall sequence of“output " input"of the checked location.
Verification
NO. location 1 Verification Verification Rated Rated Reference Others
(contact location2 Media value 1 value 2 waveform
B measurements)
1 STD0 IC1503 81pin DVD 2V~VCC33 GND~0.8V Waveform 1 Line name OHDD8 at R1425
C
9 STCLK IC1503 70pin DVD 2V~VCC33 GND~0.8V Waveform 2 Line name ODA2 at IC1405
10 STVALID IC1503 69pin DVD 2V~VCC33 GND~0.8V Waveform 2 Line name OINTRQ at IC1405
11 MASTER IC1301 176pin DVD 2V~VCC33 GND~0.8V Waveform 2 Line name STENABLE at IC1405
Rated value 1
D
GND Rated value 2
Streaming I/F rated value
14 AVH-P7500DVD/UC
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D
MPEG stream
MPEG stream
System Computer I/F E
AVH-P7500DVD/UC 15
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Check 4: Is the audio circuit operating normally?

Reproduce DVD-REF-A1 Title 2 Chapter (48V/16-bit/1 kHz/0dB). Verify the circuit described in Figure 2.
Checks are to be conducted using GNDAU1 (sensing pins) as a reference.
A
If the locations, listed under "verification location 2", can be verified, there is no need to conduct verifications for
the locations listed under "verification location 1."
and components, in the vicinity of the main components.
NO. Verification Verification Rated Rated Reference

location 1 location 2 value 1 value 2 waveform
1 AOUT0 IC1503 90pin 2.0V 0.8V Waveform 3
and over and lower
2 SRCK IC1605 1pin 2.0V 0.8V Waveform 3

B
and over and lower
3 LRCK IC1605 3pin 2.0V 0.8V Waveform 3

and over and lower
Rated value1
GND Rated value 2
C
Three serial output rated values
Checks are conducted with the measurement circuit below.
NO. Verification Verification Rated value Reference

location 1 location 2 waveform
4 LO CN1611 36pin 1100±150mV Waveform 4
5 RO CN1611 34pin 1100±150mV Waveform 4
D
Rated value
Analog audio outputs (LO and RO) rated values
HOST I/F
LO
RO
E
22kΩ These resistors are inserted.
AAGND
LO and RO output measurement circuit
16 AVH-P7500DVD/UC
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C
MPEG stream
System Computer I/F
AVH-P7500DVD/UC 17
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A Check 5: Is the video circuit operated normally?

Reproduce DVD-REF-A1 Title 2 Chapters (White 100IRE).
Monitor the output with the oscilloscope, by setting the COMPO signal to a GND reference.
Set the Trigger mode to the TV trigger, and the Trigger line to line-150.
NO. Verification location Rated value Reference

(sensing pin) waveform
1 COMPO 1.0±0.05Vpp Waveform 5
B If the result is not satisfactory, check to see if there are any problems with resin flux cored solder, parts
and components, in the vicinity of line-150 (the section marked 5 in the circuit diagram) and peripheral components.
PEAK
COMPO signal Rated When the result is not satisfactory,

value adjust the noise level to 1.0 + 0.05 Vpp.
Color burst
Pedestal
C
BOTTOM
Horizontal periodic signal
Composite signal 100% output waveform
18 AVH-P7500DVD/UC
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C
MPEG stream
System Computer I/F
AVH-P7500DVD/UC 19
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A Check 6: Is SDRAM I/F operating normally?

Check the conductivity of both the "Verification location 1" and the "Verification location2."
and components, in areas where a problem occurs, for the overall sequence of “output " input" of the checked location.
NO. Signal name Verification location 1 Verification location 2 Rated value

1 MA0 IC1501 23pin IC1503 2pin 22Ω ± 5%
2 MA1 IC1501 24pin IC1503 4pin 22Ω ± 5%
3 MA2 IC1501 25pin IC1503 7pin 22Ω ± 5%
4 MA3 IC1501 26pin IC1503 10pin 22Ω ± 5%
5 MA4 IC1501 29pin IC1503 8pin 22Ω ± 5%
B 6 MA5 IC1501 30pin IC1503 6pin 22Ω ± 5%
7 MA6 IC1501 31pin IC1503 3pin 22Ω ± 5%
8 MA7 IC1501 32pin IC1503 207pin 22Ω ± 5%
9 MA8 IC1501 33pin IC1503 204pin 22Ω ± 5%
10 MA9 IC1501 34pin IC1503 201pin 22Ω ± 5%
11 MA10 IC1501 22pin IC1503 206pin 22Ω ± 5%
12 MA11 IC1501 20pin IC1503 203pin 22Ω ± 5%
13 MDQ0 IC1501 2pin IC1503 159pin 22Ω ± 5%
14 MDQ1 IC1501 4pin IC1503 162pin 22Ω ± 5%
15 MDQ2 IC1501 5pin IC1503 165pin 22Ω ± 5%
16 MDQ3 IC1501 7pin IC1503 168pin 22Ω ± 5%
17 MDQ4 IC1501 8pin IC1503 171pin 22Ω ± 5%
C 18 MDQ5 IC1501 10pin IC1503 175pin 22Ω ± 5%
19 MDQ6 IC1501 11pin IC1503 178pin 22Ω ± 5%
20 MDQ7 IC1501 13pin IC1503 181pin 22Ω ± 5%
21 MDQ8 IC1501 42pin IC1503 180pin 22Ω ± 5%
22 MDQ9 IC1501 44pin IC1503 177pin 22Ω ± 5%
23 MDQ10 IC1501 45pin IC1503 173pin 22Ω ± 5%
24 MDQ11 IC1501 47pin IC1503 170pin 22Ω ± 5%
25 MDQ12 IC1501 48pin IC1503 167pin 22Ω ± 5%
26 MDQ13 IC1501 50pin IC1503 164pin 22Ω ± 5%
27 MDQ14 IC1501 51pin IC1503 161pin 22Ω ± 5%
28 MDQ15 IC1501 53pin IC1503 158pin 22Ω ± 5%
29 MCK IC1501 38pin IC1503 185pin 22Ω ± 5%
D 30 XWE IC1501 16pin IC1503 193pin 22Ω ± 5%
31 XCAS IC1501 17pin IC1503 195pin 22Ω ± 5%
32 XRAS IC1501 18pin IC1503 196pin 22Ω ± 5%
33 XCSM IC1501 19pin IC1503 199pin 22Ω ± 5%
34 XCSE IC1501 35pin IC1503 198pin 22Ω ± 5%
35 DQMUM IC1501 39pin IC1503 192pin 22Ω ± 5%
36 DQMLM IC1501 15pin IC1503 189pin 22Ω ± 5%
37 DQMUE IC1501 21pin IC1503 190pin 22Ω ± 5%
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MPEG stream
System Computer I/F
AVH-P7500DVD/UC 21
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A Check 7: Is the microprocessor operating normally?

Check the conductivity of both the "Verification location 1" and the "Verification location2."
and components, in areas where a problem occurs, for the overall sequence of "output – input" of the checked location.
NO. Signal name Verification Verification Verification Rated value Others

location 1 location 2 Media
1 A1 IC1701 142pin IC1503 27pin ALL 0Ω
B 6 A6 IC1701 137pin IC1503 33pin ALL 0Ω
C 18 D0 IC1701 17pin IC1503 47pin ALL 0Ω
19 D1 IC1701 16pin IC1503 49pin ALL 0Ω
D 30 D12 IC1701 3pin IC1503 63pin ALL 0Ω
34 XCSAVR IC1701 101pin IC1706 1pin ALL 0Ω
35 XCSAVW IC1701 100pin IC1706 2pin ALL 0Ω
36 XCSAV IC1706 4pin IC1503 24pin ALL 0Ω
37 XAVINT IC1701 42pin IC1503 17pin ALL 0Ω
38 XAVINT2 IC1701 41pin IC1503 18pin ALL 0Ω
39 XRD IC1701 95pin IC1503 23pin ALL 0Ω
40 CLKOUT IC1701 90pin IC1505 3pin ALL 33Ω Dividing circuitFor verification location 2,
include also IC1502 pin-3
E 41 HCLK IC1502 5pin IC1503 26pin ALL 200Ω ± 5 %
42 XSRAMWR IC1701 105pin IC1505 1pin ALL 0Ω
43 XHWR IC1504 8pin IC1503 21pin ALL 68Ω ± 5 %
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D
System Computer I/F
MPEG stream
AVH-P7500DVD/UC 23
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Note:1 The encircled number denote measuring pointes in the circuit diagram.
A
2 Reference voltage VHALF : 1.65V
! CH1: STD1 % CH1: AVRTM % CH1: AVRTM

@ CH2: STD4 5V/div. 2µs/div. ^ CH2: STCLK 5V/div. 2µs/div. ^ CH2: STCLK 5V/div. 50µs/div.
# CH3: STD7 & CH3: STVALID & CH3: STVALID
$ CH4: STENABLE $ CH4: STENABLE $ CH4: STENABLE
←T ←T
G→ G→ G→
G→ G→ G→
G→ G→ G→
B
G→ ←T G→ G→
Wave 1 Wave 2(1) Wave 2(2)
* CH1: AOUT0 ¤ CH1: LO › CH1: COMPO 200mV/div. 10µs/div.

1V/div. 500µs/div.
( CH2: SRCKAV 2V/div. 2µs/div. ‹ CH2: RO [White 100% output]
) CH3: LRCKAV
G→
G→ ←T
C G→
G→
G→
G→ ←T
Wave 3 Wave 4 Wave 5
24 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
6.3 MAIN VIDEO LEVEL ADJUSTMENT

- Adjustment Point A
Mother PCB (Side A)
Mother PCB (Side B)
MONVGND
MONVBS
AVH-P7500DVD/UC 25
5 6 7 8
F
E
B
A
D
C
Input Output
26
Step Mother PCB (input test pin,specs, (measuring point, Measuring Specs Adjusting
adjustment other conditions) waveform) instruments point
1
1
Input test pin :

MONVBS←→MONVGND Measuring point :
....100 IRE MONVBS←→MONVGND 1.35V ± 0.05Vp-p
(white 100%), Measure between the
1 Main video level Oscilloscope VR321
sync tip and 100 IRE
(top level).
(1) The Video level (Vlevel) is out of spec.

When the Vlevel is more than 1.25Vp-p, the images become whitish.
When the Vlevel is less than 1.25Vp-p, the images become blackish.
2
2
AVH-P7500DVD/UC
3
3
4
4
5 6 7 8
6.4 MONITOR PCB ADJUSTMENT A
Notes: Flicker adjustment is needed when monitor PCB is exchanged.

- Test mode starting operation.
1)To enter the setting mode, while keeping the EPRTEST terminal at "Low",
turn reset the monitor micro computer. While pressing the [REAR] and [EQ] Kyes
at the same time,reset.
2)It shifts to [Flicker adjustment mode] in Power ON.
3)To switch between the adjustment modes, use the MENU button.
Flicker adjustment mode
Line adjustment 1 mode
B
Dimmer parameter setting mode
Dot clock adjustment mode
Please set the CONTRAST data in [Line adjustment 1 mode] and [Line adjustment 2 mode] to [88],
and used as reference data for other adjustment items.
4)The operation in each mode is as follows.
[↑ ↓] button: Used to select a desired adjustment item in each mode
[← →] button: Used to adjust the selected item
- Adj P i
C
PWRV1
AVH-P7500DVD/UC 27
5 6 7 8
F
E
B
A
D
C
Notes:
28
When the power supply for TC90A64AF-P (IC4001) is OFF, be careful not to apply any voltage to its terminals
1
1
except for IIC lines(SDA and SCL). The IIC lines can accept a maximum of 5V.
No Adjustment item Input Measuring Adjusting Measuring method Remarks

point point and specs.
3.3V power supply Apply 14.4V C852 hot side

1 verification to TP PWRV1. V33 = 3.3V ± 0.3V
(TP V33)
2
2
2.5V power supply Apply 14.4V IC841(TP V25)

2 verification V25 = 2.5V ± 0.2V
to TP PWRV1.
3 5V power supply Apply 14.4V (TP V5)

verification to TP PWRV1. V5 = 5.0V ± 0.3V
AVH-P7500DVD/UC
3
3
4 8V power supply Apply 14.4V (TP V8)

verification to TP PWRV1. V8 = 8.0V ± 0.6V
5 18.5V power supply Apply 14.4V

verification (TP V18) V18 = 18.5V ± 0.8V
to TP PWRV1.
6 -12V power supply Apply 14.4V

verification (TP VM12) VM12 = -12.0V ± 0.6V
to TP PWRV1.
4
4
Notes:
When the power supply for TC90A64AF-P is OFF, be careful not to apply any voltage to its terminals except for IIC
lines(SDA and SCL). The IIC lines can accept a maximum of 5V.
2) In the following table, SA**h is a sub-address of TC90A64AF-P.
Measuring Adjusting Measuring method
5
5
No Adjustment item Input point point and specs. Remarks

4.80 ± 0.20V
Vcom amp output Any input
7 Voltage waveform TP VCOM
signal
Verification
Input waveform Apply a white The signal generator should be

verification 100% signal TP ANR,ANG, 0.7V ± 0.02V used via 75 ohms. (specs in
8 toTP AVR,ANG.
(RGB) ANB desinging : 75.0 ± 0.2ohms)
ANB.
6
6
Input waveform Apply a white The signal generator should

9 verification 100% signal TP CVBS1 0.75 ± 0.02V
be used via75 ohms.
(composite) toTP CVBS 1.
Apply a black
AVH-P7500DVD/UC
RGB amp output signal to TP
10 voltage waveform ANR,ANG,ANB. TP VG 3.9 ± 0.2V The input signal has no setup.
verification (Video level:0%) (Apply a black signal to TP CVBS)
7
7
Apply a The first-step A = 0.50V ± 0.1V The input 10-step signal

has no setup.
11 Gamma 0 10-step
signal to TP TP VG
Verification A= A2
ANR,ANG,ANB. (A1+A2)/2 A1
The 10-step A = 3.10 ± 0.15V The input 10-step signal has no setup.
Apply a If the measured value is out of specs,
change the setting ofSA24h
12 Gamma 2 10-step TP VG D11 - 8 (γ 2 inflection point:
verification signal to TP A= A2 GAMMA2 in the line adjustment 1 mode)
8
8
ANR,ANG,ANB. (A1+A2)/2 A1 (Register setting specs: 6 ± 1)
29
F
E
B
A
D
C
F
E
B
A
D
C
Notes:
30
1) When the power supply for TC90A64AF-P is OFF, be careful not to apply any voltage to its terminals except for IIC
lines(SDA and SCL). The IIC lines can accept a maximum of 5V.
1
1
2) In the following table, SA**h is a sub-address of TC90A64AF-P.

Input Measuring Adjusting Measuring method
No Adjustment item point Remarks
point and specs.
Adjust the first step levels
Apply a of the G waveform and the B waveform. Register setting specs : 8 ± 2
10-step Register (specs in designing: 8 ± 1)
13 B SUB BRIGHT signal to TP VG and VB setting of In the Line adjustment
TP ANR,ANG, SA39h 2 mode, SUB BRI B can be
ANB. D11 - 8 used as the adjusting point.
Adjust the 10th step levels of the
Apply a G waveform and the B waveform. Register setting specs: 64 ± 3
10-step Register (specs in designing: 64 ± 2)
B SUB signal to setting of In the Line adjustment
14 CONTRAST TP VG and VB SA26h 2 mode, SUB CON B can be
2
2
TP ANR,ANG,
ANB. D7 - 1 used as the adjusting point.
Apply a Adjust the first step levels Register setting specs: 8 ± 2

Register of the G wave form and the (specs in designing: 8 ± 1)
10-step setting of R waveform.(Measuring point is
15 R SUB BRIGHT signal to In the Line adjustment
TP VG and VR SA39h the same as that of No,13.) 2 mode, SUB BRI R can be
TP ANR,ANG, D15 - 12
ANB. used as the adjusting point.
Apply a Adjust the 10th step levels Register setting specs: 64 ± 3

Register of the G waveform and the
AVH-P7500DVD/UC
10-step (specs in designing: 64 ± 2)
R SUB setting of R waveform.(Measuring point is In the Line adjustment
16 signal to TP VG and VR SA26h
CONTRAST TP ANR,ANG, the same as that of No,14.) 2 mode, SUB CON R can be
D15 - 9 used as the adjusting point.
ANB.
3
3
Register 6(0110) After being written in,the setting

Horizon dot Any input setting of value of EEP-ROM is checked.
17 position signal SA22h 2 mode,DOT CLK can be used
D3 - 0 as the adjusting point.
Block light lighting.

Keep the unit in the An animation is displayed.
18 Aging Any input operation mode for
signal 30 minutes or longer.
Input a signal for If it input a signal for alternate

alternate white white into TP CVBS, it is possible.
Register
4
4
(However, adjustment by RGB has

and black lines setting of Adjust so that the flickers priority.) The luminance level of the
19 Flicker to TP ANR, Screen become minimum in all
SA22h input signal: 50%. In the flicker
TP ANG and D15 - 8 adjustment mode, COM DC can be
TP ANB. used as the adjusting point.
Flicker adjustment has been deviated The images flicker.

5
5
Inverter PCB (Side A)

- Adjustment Point
6.5 INVERTER PCB ADJUSTMENT
VPPFL1
6
6
FL2
100kΩ
FL1
INVPUL
DIMDTY
Inverter PCB (Side B)
GNDFL1
No Adjustment item Measuring Adjusting Measuring method Remarks
Input signal point point and specs.
AVH-P7500DVD/UC
100k ohms is connected between TP FL1 and
Apply 14.4V ± 0.2V TP FL2. It acts as the monitor of the waveform
BACK LIGHT to TP VPPFL1 after potential. Don't acts as the monitor of the
7
7
1 DRIVE Apply 5.0V to TP DIMDTY TP:FL1,FL2 VR 5001 48.0 ± 0.1kHz TP FL2 directly. (there is a possibility that a
FREQUENCY TP GNDFL1 and TP INVPUL measuring instrument may be destroyed, for
: GND high voltage.) Out of spec., when frequency
change of following may become impossible.
Apply wave of 98.0V ± 1kHz to It checks that the waveform after potential is set
TP INVPUL to 49 kHz
2 FREQUENCY 5V TP:FL1,FL2 49.0 ± 0.5kHz

CHANGE CHECK 10 ± 2%
0V
Apply wave of 104.0V ± 1kHz to It checks that the waveform after potential is set
TP INVPUL
8
8
to 52 kHz
3 FREQUENCY 5V TP:FL1,FL2 52.0 ± 0.5kHz
CHANGE CHECK 10 ± 2%
31
0V
F
E
B
A
D
C
1 2 3 4
6.6 MOTHER PCB ADJUSTMENT

A
- Adjustment Point
Mother PCB (Side A)
A-9V
OSC
DOUT2
DD8
C
Mother PCB (Side B)
34(DDCCTL)
E 29(DALMON)
DD33
32 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- DC-DC converter adjustment A

Test condition
1.Resistance (40.0Ω) is added between DD8 and GND
Resistance (6.6Ω) is added between DD33 and GND
Resistance (90.0Ω) is added between A-9V and GND
2.DDCCTL=LOW(0V),DALMON=HIGH (5V) and DC-DC conveter input voltage 14.4±0.2V.
No ITEMS SPECIFICATIONS Adjustment point NOTE
1 Output Voltage 1 +8.1±0.4V DD8-GND

2 Output Voltage 2 +3.4±0.3V DD33-GND
3 Output Voltage 3 -9.0±0.4V A-9V-GND B
4 Frequency 1 370±5kHz DOUT2-GND
5 Frequency 2 370±5kHz OSC-GND
6 Output noise level -30dBs or less DD8-GND No filter
DD33-GND
A-9V-GND
AVH-P7500DVD/UC 33
5 6 7 8
1 2 3 4
6.7 TUNER SELECTOR UNIT ADJUSTMENT(UC model)

- Adjustment Point
A Tuner selector unit (Side A)
REVOUT
AVVOUT
S2
S1
S-MODE
Tuner selector unit (Side B)
AVIN
34 AVH-P7500DVD/UC
1 2 3 4
- Tuner Selector Unit
Step Adjustment item Input signal (input point, wave form, Output signal (measuring point, Measuring Specs. Adjusting point
specs. and other conditions) waveform and circuit) instrument
1 To enter the service Short-circuit S-MODE.
5
5
operation mode
2 Video output level Input: AV-BUS IN Measuring point : AVVOUT Oscilloscope 1.0±0.05Vp_p VR1221
(front) adjustment Signal: 100IRE(white 100%) Sync tip to 100IRE (waveform top)
Level: 1.0Vp-p(via 75Ω)
Measuring conditions: Select the 75Ω
terminal on the measuring instrument.
3 Video output level Input: AV-BUS IN Measuring point : REVOUT Oscilloscope 1.0±0.05Vp_p VR1220
(rear) adjustment Signal: 100IRE(white 100%) Sync tip to 100IRE (waveform top)
Level: 1.0Vp-p(via 75Ω)
6
6

4 To enter the service Open S1. Short-circuit S2,then reset the

operation mode2 unit by pressing the reset button.
5 OSD display position Input: none Measuring point : REVOUT Oscilloscope NTSC: TC1280
AVH-P7500DVD/UC
adjustment Signal: none The time between the Sync leading edge and 34.8±0.1µsec.
Level: none video leading edge
Mode: test mode(with positioning
7
7
adjustment OSD output)

6 To exit from the Open S2 and S-MODE, then reset

service mode the unit.
8
8
35
F
E
B
A
D
C
1 2 3 4
A 6.8 TV TUNER UNIT ADJUSTMENT(UC model)

- Adjustment Point
TV tuner unit (Side A)
TV tuner unit (Side B)
D
TVV
VDIV5V
TVMONO
VIDEO
E
REF
AFC
AGC
36 AVH-P7500DVD/UC
1 2 3 4
- TV Tuner Unit Notes:
1. TV sensitivity: based on 75-ohm loaded (UN BAL) voltage and video carrier level
2.The rated level: 59dBµV
3. Audio carrier level: (Video carrier level) -6dB
4. Adjustments should be made with the ANT1 selected.
5
5
Step Adjustment item Input signal (input point, waveform, specs, Output signal (measuring point, Adjusting instrument Specs.
and other conditions) waveform, adjusting method) and adjusting points
1 Video detection coil Apply the RF signal of the rated level (59dBµV at 75ohms) that is Measuring point: TP VIDEO DC meter Minimum within the allowable
adjustment synchronized with US11ch (P carrier: 199.25MHz) and modulated L2402 rotating range
with a white signal (White 100%, audio: monaural 400Hz, The DC level when the rated input is applied.
25kHz/div).
2 AGC start adjustment Measuring point: TP AGC DC meter Vb = Va -0.9V

VR2401
(1) Voltage with -20dBµV input: Va
(2) Voltage with 50dBµV input: Vb
3 Video output level Measuring point: TP TVV Oscilloscope 1.0 ± 0.1Vp-p
6
6
adjustment Sync tip to 100IRE (waveform top) VR2751
4 Audio detection coil Measuring point: TP.REF, TP AFC Center meter 0

adjustment L2301
The DC level between the above 2 points
5 IF trans adjustment Measuring point: TP TVMONO Noise meter Maximum

Output level with -15dBµV input L2353
AVH-P7500DVD/UC
6 Soft mute adjustment Measuring point: TP TVMONO Noise meter Vc -20 ± 1dB
7
7
VR2301
(1) Output level with the rated input: Vc
(2) Output level with -20dBµV input
7 Audio output level Measuring point: TP.TVMONO . Noise meter 375mVrms

adjustment VR2303
Output level with the rated input (reception: Hi-Z)
8
8
37
F
E
B
A
D
C
F
E
B
A
D
C
38
- TV Tuner Unit Notes:
1. TV sensitivity: based on 75-ohm loaded (UN BAL) voltage and video carrier level
2.The rated level: 59dBµV
1
1
3. Audio carrier level: (Video carrier level) -6dB

4. Adjustments should be made with the ANT1 selected.
Step Adjustment item Input signal (input point, waveform, specs, Output signal (measuring point, Adjusting instrument Specs.
and other conditions) waveform, adjusting method) and adjusting points
8 SD sensitivity Apply the RF signal of the rated level (59dBµV at 75ohms) that is Measuring point: TP SD DC meter (1) Low to High
(2) 37dBµV: H
adjustment and synchronized with US11ch (P carrier: 199.25MHz) and modulated VR2302 (3) 27dBµV: L
confirmation with a white signal (White 100%, audio: monaural 400Hz, (1) In case of 32dBµV input
(2) In case of 37dBµV
25kHz/div). (3) 27dBµV input DC levels
9 Diver Measuring point: TP VDIV5V ,TP CNT DC meter Vd=Ve/2 ± 0.1V
adjustment (1) TP CNT voltage with the rated input: Vd TC2110
(2)TP VDIV5V voltage: Ve
2
2
AVH-P7500DVD/UC
3
3
4
4
5 6 7 8
6.9 MONITOR TEST MODE

-EEPROM setting mode
[Operations]
To enter the setting mode, while keeping the EPRTEST terminal at "Low",
turn reset the monitor micro computer. While pressing the [REAR] and [EQ] Kyes at the same time,reset. A
Flicker adjustment mode
Dimmer parameter setting mode
Dot clock adjustment mode
[ ↑ ↓ ] button: Used to select a desired adjustment item in each mode
[ ←→ ] button: Used to adjust the selected item
Notes:
1) The setting values are written in the EEPROM and then the read-out data is displayed on the screen.
WRITE and READ operations are processed by the block data of 16 bits.
The total bits for the settings depend on adjusting items. B
2) For CS (Check Sum) items, when the settings are changed, the CS value is written in 8 bits by applying
the exclusive OR (XOR). The CS value is first written in the EEPROM and then the read-out data is displayed.
If the written data is different from the read-out data, the letter color for the read-out data is changed.
- Memory items and addresses on the EEPROM(S-93C46BR01-J8T1)
Memory EEPROM
array address Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00H Dimmer external light threshold (high) Dimmer external light threshold (low)
01H Backlight output (upper limit) Backlight output (lower limit)
02H Don'tcare Common reserve output amplitude (COM AMP)

Common reverse output center (COM DC) PIP SA:22h[B7-2]
03H Don'tcare Output clamp DC (RGB BIAS) Don'tcare γ 0 inflection point (GAMMA 0)
PIP SA:23h[B13-8] PIP SA:23h[B3-0] C
04H γ 3 inflection point (GAMMA 3) γ 2 inflection point (GAMMA 2) Don'tcare γ 1 inflection point (GAMMA 1)
PIP SA:24h[B15-12] PIP SA:24h[B11-8] PIP SA:24h[B7-3]
Output sub contrast R (SUB CON R) Output sub contrast B (SUB CON B)
05H Don'tcare Don'tcare
PIP SA:26h[B15-9] PIP SA:26h[B7-1]
Sub brightness R after γ circuit (SUB BRI R) Sub brightness B after g circuit (SUB BRI B)
06H Don'tcare
PIP SA:39h[B15-12] PIP SA:39h[B11-8]
Clock phase adjustment (DOT CLK)
PIP SA:2Ah[B3-0]
Sharpness (SHARPNESS)
PIP SA:05h[B2-1]
09H Touch panel X coordinates 1 Touch panel Y coordinates 1
0AH Touch panel X coordinates 2 Touch panel Y coordinates 2
0BH Touch panel X coordinates 3 Touch panel Y coordinates 3
0CH Touch panel X coordinates 4 Touch panel Y coordinates 4 D

0DH Touch panel X coordinates 5 Touch panel Y coordinates 5
Bank 1 0EH Touch panel X coordinates 6 Touch panel Y coordinates 6
0FH Touch panel X coordinates 7 Touch panel Y coordinates 7

E
19H Touch panel X coordinates 17 (Not used) Touch panel Y coordinates 17 (Not used)
1AH Outermost Xmin Outermost Ymin
1BH Outermost Xmax Outermost Ymax
1CH Check sum address
1DH Don'tcare Common reverse output center(Reference) F

1EH Don'tcare Clock phase adjustment initial value
1FH Don'tcare
AVH-P7500DVD/UC 39
5 6 7 8
1 2 3 4
Memory EEPROM
A array address Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
20H External light of dimmer adjustment(H) Back light of dimmer adjustment(H)
21H External light of dimmer adjustment(M) Back light of dimmer adjustment(M)

Bank 2
22H External light of dimmer adjustment(L) Back light of dimmer adjustment(L)
23H-3FH Don'tcare
- EEPROM initial value

B Item Meaning initial value(hex)
COM_DC Common reverse output center 8C
COM_AMP Common reverse output amplitude 24
RGB_BIAS Out clamp DC 00
GAMMA0 γ0 02
GAMMA3 γ3 08
GAMMA2 γ2 06
GAMMA1 γ1 13
SUB_CON_R Output sub contrast R 40
SUB_CON_B Output sub contrast B 40
C SUB_BRI_R Sub brightness R after γ circuit 08
SUB_BRI_B Sub brightness B after γ circuit 08
DOT_CLK Clock phase adjustment 08
SHARPNESS Sharpness 03
BL_MAX Back light output (Max.) C4
BL_MIN Back light output (Min.) 5B
REF_HIGH Dimmer (H) A0
REF_LOW Dimmer (L) 60
LUM_HIGH External light (H) E2
LUM_MID External light (M) 87
D LUM_LOW External light (L) 52
BL_HIGH Back light (H) C4
BL_MID Back light (M) C4
BL_LOW Back light (L) 68
40 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
[Displays in each mode] A

In the following figures, the letters and numbers surrounded by a large square are for OSD examples.
On the screen, the adjustment names and the settings (or written data) are listed.
The settings (or written data) will change when some adjustments are made in each mode.
(The following examples show the maximum values.)
(1) Flicker adjustment mode

Settings or
Adjustment
Adjustment item range Adjustable name written data
(DEC)
B
Common reverse output center [0 - 255] COM DC 140
C
Notes: The CONTRAST data is [88], and used as refference data for other adjustment items.
(2) Line adjustment 1 mode
Settings or
Adjustment Adjustable range written data
Adjustment item item (DEC)
Bright (SA22: B7-2) [0 - 63] BRIGHT 30 LINE1
Contrast (SA25: B7-1) [0 - 127] CONTRAST 88
Common reverse output center [0-255] COM DC 140
Common reverse output amplitude [0-63] COM AMP 30
Output clamp DC [0-63] RGB BIAS 0
γ 0 inflection point [0-15] GAMMA0 2
γ 3 inflection point [0-15] GAMMA3 4 D
CS AFC3
Notes:
1) CONTRAST data
The CONTRAST data is adjustable, and used as reference data for other adjustment items,
which is not memorized in the EEPROM.
2) BRIGHT and COM AMP data
E
The BRIGHT and COM AMP adjustments are made by using the same 2-screen IC register
(SA22h B7-2: common reverse output amplitude).
Therefore, adjusting one of the data will change the other one.
AVH-P7500DVD/UC 41
5 6 7 8
1 2 3 4
Notes: The CONTRAST data is [88], and used as refference data for other adjustment items,
(3) Line adjustment 2 mode
Settings or
Adjustment
Adjustment item range Adjustable name written data
(DEC)
A
Bright (SA22: B7-2) [0 - 63] BRIGHT 30 LINE2
Contrast (SA25: B7-1) [0 - 127] CONTRAST 88
Output sub contrast R [0 - 127] SUB CON R 64
Output sub contrast B [0 - 127] SUB CON B 64
Sub brightness R after γ circuit [0 - 15] SUB BRI R 8
Sub brightness B after γ circuit [0 - 15] SUB BRI B 8
Clock phase adjustment [0 - 15] DOT CLK 7
Sharpness [0 - 3] SHARPNESS
CS AFC3
Notes:
1) CONTRAST data
The CONTRAST data is adjustable, and used as reference data for other adjustment items,
which is not memorized in the EEPROM.
2) SUB BRI R and SUB BRI B data
The displayed value or EEPROM written data is different from the setting value for the 2-screen
IC register (TC90A64AFP : IC4001).
C
(Before displayed on the screen, the setting value is converted via some software.)
Displayed value EEPROM written value. 2-screen IC register
(adjusting value) (DEC) (DEC) setting (BIN)
15 15 0111 (MAX)
14 14 0110
9 9 0001
8 8 0000 (TIP)
7 7 1111
D
1 1 1001
0 0 1000 (MIN)
(4) Dimmer parameter setting mode

E Settings or
Backlight output (MAX) [0 - 255] BL MAX 196 DIMMER
Backlight output(MIN) [0 - 255] BL MIN 91
Dimmer threshold (high) [0 - 255] REF H 160
Dimmer threshold (low) [0 - 255] REF L 96
External light point (high) [0 - 255] LUM H 226
External light point (middle) [0 - 255] LUM M 135
External light point (low) [0 - 255] LUM L 82
Backlight point (high) [0 - 255] BL H 196
Backlight point (middle) [0 - 255] BL M 196
F Backlight point (low) [0 - 255] BL L 104 CS AFC3
Note: The dimmer point data is memorized in the EEPROM, but not treated as a CS item.
It's because the settings are adjustable by the user.
42 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
(5) Dot Clock adjustment mode

Settings or
Clock phase adjustment [0-15] DOT CLK 15
Factory [0-15] [FACTORY] 3
Common reverse [0-255] COM DC 255

output center [0-255] [FACTORY] 255
Common reverse B
output center adjustment
Factory
Note: At the time of dotclock, adjustment of DOTCLK/COMDC also change

COMDC/DOTCLK of Flicker/LINE1/LINE2 simultaneously.
At the time of Flicker/LINE1/LINE2, adjustment of COMDC/DOTCLK also change
factory value of dotclock simultaneously.
AVH-P7500DVD/UC 43
5 6 7 8
1 2 3 4
A 6.10 TOUCH PANEL CALIBRATION

1. Touch panel calibration
1.1 To enter the touch panel calibration mode

While pressing the ATT and BACK keys on the main unit, reset and start the unit.
1.2 Adjustment outline
1) Touch panel effective range check
2) Touch panel 16-point calibration
The touch panel calibration consists of the above two checks.
B When finishing the above checks, exit from the calibration mode by turning off the ACC.
1.3 Adjustment screen menu

Top menu
1) Setup TP effective range
The effective range (outer limit) of the touch panel is obtained.
2) Setup calibration
By touching the 16 points on the screen (excluding the last one for finalization), whole screen calibration will be per-
formed.
* Pressing any screen points far from the (+) marks will not allow you to proceed to the next (+) point.
C
* To stop the calibration, press the BAND/ESC key.
3) Touch-panel test (only for factory test)
For each (+) mark, the OSD coordinates, AD values, and coordinates before and after correction are displayed.
4) Calibration test (only for factory test)
For touched points, coordinates before and after correction are displayed.
0123456789 012345678901234567890
0 # # # Calibration / TP - TEST # # # 0
1 1
2 1. Setup TP effective range 2
D
3 2. Setup calibration 3
4 3. To u c h - p a n e l t e s t 4
5 4. Calibration test 5
6 6
7 [↑/↓] Cursor movement 7
8 [ENTER] Menu selection 8
9 [ACC OFF] End of test 9
1.4 Cautions on adjustment

1) Be sure to perform the touch panel effective range check (1.Setup TP effective range) first, and then the touch panel
16-point calibration (2. Setup calibration). If the TP effective range check is done again after the TP 16-point calibration,
E
you need to perform the 16-point calibration again.
2) At the TP effective range check, never use a pointed thing like nails to trace the edge of the screen. Use a round-
headed thing (R1 or more) and push the screen softly to prevent the screen from being damaged.
1.5 Detailed adjustment procedures

On the main unit or the remote control, use the ↑ /↓ keys to select the check item (1) or (2) from the menu, and then
press the ENTER key.
When finishing both checks, turn off the ACC to exit from the calibration mode.
44 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
(1) Setup TP effective range

A
The checking data for the edge of the TP screen is memorized in the EEPROM.
[Display]
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
# # Setup TP effective range # #
0 0
The present of touch - panel
1 1
effect range (before,after)
2 2
3 X min : (***.***) 3
4 Y min : (***.***) 4
5 X max : (***.***) 5
6 Y max : (***.***) 6
B
7 7
< CAUTION >
8 8
Please touch around panel.
9 9
[ E N T E R ] C h e c k t h e Va l u e
* The range (before) is the data that has been stored in the EEPROM before calibration.
* The range (after) is the data that will be stored after calibration. (Default: min 120, max 180)
Checking result - OK
0123456789 012345678901234567890
0 0
1 1
2 2 C
3 3
4 O K 4
5 5
6 6
7 [ENTER] Return to Menu 7
8 8
9 9
Checking result - NG
0123456789 012345678901234567890
0 0
1 1 D
2 2
3 3
4 N G 4
5 5
6 6
8 8
9 9
AVH-P7500DVD/UC 45
5 6 7 8
1 2 3 4
[Adjustment steps]
A
1) Trace the edge of the screen along the monitor resin frame with a round-headed thing (R1 or more) to obtain the
coordinates (as shown by a white line in the right figure).
B
* The black frame is the outer resin frame of the monitor.
Caution:
Never use a pointed thing like nails when tracing the edge of the screen. Use a round-headed thing (R1 or more) and
push the screen softly to prevent the screen from being damaged
2) Press the ENTER key on the main unit or remote control.
If the checking result is within the allowable range, "OK" will be displayed in the center of the screen. If not, "NG" will
be displayed.
* When the checking result exceeds the default values by 10% or more, "NG" is displayed on the screen.
C
3) To return to the top menu, press the ENTER key on the main unit or remote control.
Default data list

Coordinates Min. Max.
X 60 225
Y 65 222
46 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
(2) Setup calibration

A
By touching the (+) marks on the screen one by one, their calibration results are memorized in the EEPROM.
[Display]
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
0 +13 +12 +5 +4 0
1 1
2 2
3 +14 +11 +6 +3 3
4 4
5 5 B
6 +15 +10 +7 +2 6
7 7
8 8
9 +16 +17 +9 +8 +1 9
* Pressing any screen points far from the (+) marks is ignored.
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
0 0
1 1
C
2 2
3 FINISHED 3
4 4
5 5
7 7
8 8
9 9
* In the above figure, the numbers after (+) (from 1 to 17) shows the order where the cursor moves.
* When the 17th (+) mark is pressed, "FINISHED" will be displayed. D
[Adjustment steps]
1) Push the 16 (+) marks one by one by following the cursor's movement. (The plus marks appear in turn on the
screen. When you push one properly, the next mark will be displayed.)
2) Lastly, push the 17th (+) mark. "FINISHED" will be displayed in the center of the screen.
3) To return to the top menu, press the ENTER key on the main unit or remote control.
* If you press the BAND/ESC key during adjustment, the screen mode will return to the top menu without any adjust- E
ment results stored.
AVH-P7500DVD/UC 47
5 6 7 8
1 2 3 4
A
6.11 SYSTEM MICROCOMPUTER TEST PROGRAM
1. PCL output
In the normal operation mode (with the detachable panel installed, the ACC switched ON, the standby mode can-
celled), shift the TESTIN terminal to H. The clock signal is output from the CLKOUT terminal (Pin 36). The frequency of
the clock signal is 18.874MHz that is the fundamental frequency.
48 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
7. GENERAL INFORMATION A
7.1 DIAGNOSIS
7.1.1 DISASSEMBLY
- Removing the Grille Assy (Fig.1)
4
1 Remove the two screws and then remove 4
the Holder.
Disconnect the connector.
2 Remove the two screws and then remove 3 B

the Grille Assy.
3
3
- Removing the Case and Bracket
3 Remove the five screws.(Fig.1)
4 Remove the two screws and then remove

the Case.(Fig.1) C
Note) Inside the product there is a flexible substrate
that connects the Case and the Bracket.
Be very careful and do not give it a strong pull 1 1
3 3
when removing the Case, otherwise it may
be torn. 2 2
5 Remove the four screws. (Fig.2)
Disconnect the connector and then remove the Case Holder Grille Assy
Bracket. (Fig.2) Fig.1
Remove the Case.(Fig.1) D
5 5
5 5
Bracket F
Fig.2
AVH-P7500DVD/UC 49
5 6 7 8
1 2 3 4
A
- Removing the DVD Mechanism Module (Fig.3)
1 Remove the four screws.
Disconnect the connector and then remove the

DVD Mechanism Module.
B
1
1
1
C
DVD Mechanism Module Fig.3
- Removing the Mother PCB (Fig.4) Bracket
1 Straighten the tab at location indicated. 3

4
4 4
2 3
2 Remove the screw and then remove 4
the Holder.
D
3 Remove the two screws.
5
4 Remove the four screws and then remove 1
the Bracket. 5
5
5 Straighten the tabs at six locations
indicated.
5
6 Remove the screw and then remove
E
the Mother PCB.
5 5
Holder
Mother PCB
Fig.4
F
50 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- Removing the Case (Fig.5) A

3 3
1 Remove the two screws and then remove 1 1
the Holder.
3 3
2 Remove the screw. 3
2
3 Remove the five screws and then remove

the Case.
B
Case Holder
Fig.5
Motor Unit
- Removing the Display Assy (Fig.6) Switch
1 Remove the screw.
Disconnect the connector and then remove

the Motor Unit. C
1
the two Holders.
3 Pull out the Display Assy in the arrow
indicated direction.
Note) When reassembling, hold the switch down

with tweezers or the like and put the Display Assy
back to the Chassis. Otherwise, the switch may be
damaged and not function properly.
D
2 2
Holder 33 Holder
Display Assy
Fig.6
- Removing the Main Unit (Fig.7) Bracket Shaft Unit
2 3 2
3
1 Remove the screw and then remove E
the Bracket.
2 1 2
2 Remove the four screws and then
remove the Shaft Unit.
3
3 Remove the three screws.

the Main Unit. Main Unit Fig.7
F
AVH-P7500DVD/UC 51
5 6 7 8
1 2 3 4
A - Removing the Display Assy (Fig.8)

Display Assy Holder
the Holder.
1 1
2 Remove the three screws.
4 4
the Cover Unit.
B
4 Remove the four screws.
4 4
the Display Assy. 2 2 2
3 3
Cover Unit Fig.8
- Removing the Monitor PCB (Fig.9)

C 1 1
1 Straighten the tabs at two locations indicated.
2 Remove the screw.

the Monitor PCB.
Monitor PCB Fig.9
52 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- Precautions on handling the mechanism module

1. Hold the upper and main frames.
2. Do not hold the front portion of the upper frame. It is a delicate part.
A
3. Do not touch the switches on the top panel.
4. Be careful not to catch the flexible cables.
Do not touch here. Do not touch here.

C
Do not hold this delicate portion.
- Removing the DVD Core Unit(MS3)
1. Set the mechanism to the lock position (disc load standby position).
2. Place the mechanism module upside down.
3. Short the two lands on the pickup flexible cable as shown below.
4. Be sure to disconnect the pickup flexible cable and the CRG flexible cable from the connectors
to protect them from damages.
5. Remove solder from the load motor leads and clamp SW leads.
6. Loosen the two fixing screws. Lift the position A of the DVD Core Unit lightly and move it
in the direction B to remove it. Be careful not to damage the flexible cable C.
7. Disconnect the 8/12 detection flexible-cable from the connector. D
Short here.
DVD Core Unit(MS3)
Connector
(for pickup flexible cable)
Connector
(for 8/12 detection flexible cable)
Load motor A C
leads and clamp SW leads B
Connector F
(for CRG flexible cable)
AVH-P7500DVD/UC 53
5 6 7 8
1 2 3 4
A
- Removing the pickup unit
1. Remove the DVD Core Unit(MS3) in accordance with the procedure of "Removing the DVD Core Unit(MS3).”
2. While holding the pickup case, remove the skew screw (main).
3. Lifting the end of the pickup rack, slide the main shaft, and remove the pickup unit.
Notes:
Replacing the pickup unit requires the skew adjustment.
Remove glue from both ends of the main and sub shafts, and skew stud.
Do not reuse the old skew screw. Be sure to use a brand-new skew screw supplied with a new pickup unit.
Fix the skew screw with Screw lock (GYL1001) after adjustment.
Skew screw (main)
C Skew screw
Pickup unit
Sub shaft
Skew screw
54 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
7.1.2 PCB LOCATIONS
COMPOUND UNIT(A)
COMPOUND UNIT(B)
E
G
TUNER SELECTOR UNIT
Q F
TV TUNER UNIT
(UC model)
AVH-P7500DVD/UC 55
5 6 7 8
1 2 3 4
A 7.1.3 CONNECTOR FUNCTION DESCRIPTION
Auto Ant
REVERSE-GEAR SIGNAL INPUT
2 30
1 29
1 : CE1
2 : DO
3 : DI
4 : DGND
5 : SL
6 : CK
7 : TUNPW
C 1 11 2 30 8 : IPSEL1
9 : RDSCK
1 29 10 : H/A/SENS
1 15 11 : IPSEL2
2 16
12 : LDET
2 12 13 : NC
14 : RDSDATA
1 : FL- 1 : FL 1 : SELVGND 15 : RDSLOCK
2 : RL- 2 : FLGND 2 : SELVOUT 16 : (RF GND)
3 : FL+ 3 : FR 3 : GNDVBS2 17 : CE2
4 : RL+ 4 : FRGND 4 : DVDVBS2 18 : REARMUTE
5 : FR- 5 : RL 5 : MS3VOUT 19 : AMPMUTE
6 : RR- 6 : RLGND 6 : VGND 20 : RDSHSLK
7 : FR+ 7 : RR 7 : MICSEN 21 : REM
8 : RR+ 8 : RRGND 8 : BUS-
D 9 : P.B. 9 : CENTER 1 : CCR
9 : SELPW
10 : VGND 10 : CNTGND 2 : CCG
10 : MUTE
11 : ACC 11 : SW 3 : CCB
11 : SCL
12 : B.REM 12 : SWGND 4 : CCSYNC
12 : SDA
13 : ILL 5 : GNDSIG
13 : AVON
14 : MUTE 6 : DVDVBS
14 : SYSPW
15 : B.UP 7 : GNDDVD
15 : ASENBO
16 : GND 8 : VS
16 : RESET
9 : NC
17 : H/A/DSENS
10 : CCAUL
18 : BUS+
11 : CCAUR
19 : SELMUTE
12 : GNDAU
20 : GNDIN
13 : ONSEI+
21 : HARin
14 : ONSEI-
22 : HALin
15 : REAUR
E 23 : AGND3
16 : REAUL
24 : CENTER
17 : GNDRAU
25 : AGND2
18 : CCREM
26 : NAVRch
19 : OSEN
27 : NAVLch
20 : TVON
28 : AGND1
21 : GION
29 : MS3Rch
22 : MONON
30 : MS3Lch
23 : VSWS
24 : HTXD
25 : HRXD
26 : GNDD
56 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- UC model
V L R 4 3 2 1
TV ANTENNA IN
REAR MONITOER OUT
B
5 6
1 2 3 4
2 30
8 9 10 11
1 29
1 5
7
1. GNDH 1 : SELVGND 16 : RESET
2. GNDV 2 : SELVOUT 17 : H/A/DSENS 1. BUS+
3. SPOUT- 3 : GNDVBS2 18 : BUS+ 2. GND
4. SPOUT+ 4 : DVDVBS2 19 : SELMUTE 3. GND
5. BUP 5 : MS3VOUT 20 : GNDIN 4. NC
6 : VGND 21 : HARin 5. BUS-
7 : MICSEN 22 : HALin 6. GND
8 : BUS- 23 : AGND3 7. BUS L+ INPUT C
9 : SELPW 24 : CENTER 8. ASENB
10 : MUTE 25 : AGND2 9. BUS R+ INPUT
11 : SCL 26 : NAVRch 10. BUS R- INPUT
12 : SDA 27 : NAVLch 11. BUS L- INPUT
13 : AVON 28 : AGND1
14 : SYSPW 29 : MS3Rch
15 : ASENBO 30 : MS3Lch
1 : CE1
2 : DO
3 : DI
4 : DGND
5 : SL
Antenna jack 6 : CK
7 : TUNPW
8 : IPSEL1
9 : RDSCK
V L R 10 : H/A/SENS
11 : IPSEL2
VCR IN 12 : LDET
13 : NC
14 : RDSDATA E
BACK CAMERA IN
15 : RDSLOCK
16 : (RF GND)
17 : CE2
18 : REARMUTE
Auto-EQ and T 19 : AMPMUTE
AV-BUSinput(Blue) 20 : RDSHSLK
21 : REM
1. COMP GND
2. COMP
5. IP_SEL1
4. IP_SEL2
12. AV_ON
6. LED_V
7. GND F
10. REMIN
11. NEW AV SENS
AVH-P7500DVD/UC 57
5 6 7 8
1 2 3 4
- EW model
V L R
REAR MONITOER OUT

B
5 6
1 2 3 4
2 30
8 9 10 11
1 29
1 5
7
1. GNDH 1 : SELVGND 16 : RESET
2. GNDV 2 : SELVOUT 17 : H/A/DSENS 1. BUS+
3. SPOUT- 3 : GNDVBS2 18 : BUS+ 2. GND
4. SPOUT+ 4 : DVDVBS2 19 : SELMUTE 3. GND
5. BUP 5 : MS3VOUT 20 : GNDIN 4. NC
6 : VGND 21 : HARin 5. BUS-
7 : MICSEN 22 : HALin 6. GND
C 8 : BUS- 23 : AGND3 7. BUS L+ INPUT
9 : SELPW 24 : CENTER 8. ASENB
10 : MUTE 25 : AGND2 9. BUS R+ INPUT
11 : SCL 26 : NAVRch 10. BUS R- INPUT
12 : SDA 27 : NAVLch 11. BUS L- INPUT
13 : AVON 28 : AGND1
14 : SYSPW 29 : MS3Rch
15 : ASENBO 30 : MS3Lch
1 : CE1
2 : DO
3 : DI
4 : DGND
5 : SL
Antenna jack 6 : CK
7 : TUNPW
8 : IPSEL1
9 : RDSCK
V L R 10 : H/A/SENS
11 : IPSEL2
VCR IN 12 : LDET
13 : NC
E BACK CAMERA IN 14 : RDSDATA
15 : RDSLOCK
16 : (RF GND)
17 : CE2
18 : REARMUTE
Auto-EQ and T 19 : AMPMUTE
AV-BUSinput(Blue) 20 : RDSHSLK
21 : REM
1. COMP GND
2. COMP
5. IP_SEL1
4. IP_SEL2
12. AV_ON
6. LED_V
F 7. GND
10. REMIN
11. NEW AV SENS
58 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
7.2 PARTS
7.2.1 IC
A
AK7720AVT PD6340A S-812C50AUA-C3E TC7SZ04FU
AN8011S PD6408D S-812C56AUA-C3K TC7SZ32FU
AN8015SH PD8113A S-818A38AUC-BGS TC7WB126FK
AN8471SAT1 PD8114A S-93C46BR0I-J8T1 TC7WHU04FU
AN8703FH PE5300A : UC model SI6544DQ TC7WU04FU
BP5451 NJW1303V : UC model SM5304AV MSM51V4265EP-70TS
M35014-001SP : UC model PE5366A SM8707FV TC90A64AF-P
M2V64S40DTP-6L PE5395A TC74LCX541FT TK15405MI : UC model
MN5B00UB PQ1X251M2ZP TC74VCX00FT XC25BS5118MR
MN677531KAUB PQ1X331M2ZP TC74VCX02FT YSS932-S B
MNZS26EDCUB S-80827CNUA-B8M TC74VCX32FT PE5363A : EW model
PCM1604Y-2 S-80835CNUA-B8U TC7MB3257FK PE5365A : UC model
PD5869A S-80841CNUA-B82 TC7PA04FU TA1290FN : UC model
PCM1742KE S-812C33AUA-C2N TC7SZ02FU CWB1093 : UC model
IC's marked by * are MOS type.

Be careful in handling them because they are
very liable to be damaged by electrostatic induction.
*AK7720AVT
C
TESTI1 TESTI2 PLL CKS LFLT LRCLK BITCLK XTI XTO
CLKO CLKO
PLL CKS LFLT LRCLK BITCLK XTI XTO SMODE SMODE
TESTI1 INIT_RESET INIT_RESET
SDINA TESTI2 CONTROLLER & PLL CODEC_RESET CODEC_RESET
DSP_RESET DSP_RESET
SDIN1 AINL+ AINL+

SDIN2 SW0 ADC AINL- AINL-
AINR+ AINR+
SDINA
RQ RQ SDATA AINR- AINR- D
VRADH VRADH
SI SI SDIN1
DSP SW1 VRADL VRADL
SO SO
SDIN2 DISE
SCLK SCLK
SW2
AOUTL+ AOUTL1+
RDY RDY SDOUTD1
DAC1
AOUTL- AOUTL1-
SDATA
DRDY DRDY AOUTR+ AOUTR1+
SW2
JX JX VRDAH,L SMUTEAOUTR- AOUTR1-
SDOUTD2
VRDAH,VRDAL
SW2
SMUTE
SDOUTD3
VRDAH,L SMUTE AOUTL+ AOUTL2+
SDOUT SDATA AOUTL- AOUTL2- E
SDOUT DAC2 AOUTR+ AOUTR2+
SDOUTD1 AOUTR- AOUTR2-
SDOUTD2
SW3
SDOUTD3A VRDAH,L SMUTEAOUTL+ AOUTL3+
SDATA AOUTL- AOUTL3-
EXTERNAL RAM DAC3 AOUTR+ AOUTR3+
CONTROLLER AOUTR- AOUTR3-
CAS RAS WE A[16:0] OE IO[7:0]
CAS RAS WE A[16:0] OE IO[7:0] F
AVH-P7500DVD/UC 59
5 6 7 8
1 2 3 4
*AK7720AVT
A
- DSP BLOCK
CP0,CP1 DP0,DP1 Data IO7~IO0 Address A16~A0
CRAM DRAM Delay Data Ext RAM OFRAM

512 X 16 384 X 24 24 /16bit Control 48 X 20
CBUS(16bit)
B DBUS(24bit)
Micon I/F
MPX16 MPX24 Control Serial I/F
X Y
DEC
PRAM
Multiply1 768 X 32
16 X 24 -> 40
C
24bit
PC
40bit Stack : 1level
MUL DBUS
34bit SHIFT
TMP 8 X 24bit
34bit
PTMP 24bit X 6
A B
ALU1
D 34bit 2 X 24 bit SDINA
Overflow Margin: 4bit
2 X 24/20/16bit SDIN1
DR0 ~ 3
24bit 2 X 24/20/16bit SDIN2
Over Flow Data Divider1

Generator 24 ÷24→24or16
E Peak Detector
2 X 24bit SDOUTD1
2 X 24bit SDOUTD2
2 X 24bit SDOUTD3
2 X 24bit SDOUT
F
60 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*AK7720AVT
NC(AVSS)
AOUTR3+
A
AOUTL3+
AOUTR3-
AOUTL3-
TESTI1
TESTI2
DVDD
DVDD
DVSS
DVSS
BVSS
A16
A15
A14
A13
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
OE
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AOUTR2- 76 50 A12
AOUTR2+ 77 49 A11
NC(AVSS) 78 48 A10
AOUTL2- 79 47 A9
AOUTL2+ 80 46 A8
NC(AVSS) 81 45 A7
B
AOUTR1- 82 44 A6
AOUTR1+ 83 43 A5
NC(AVSS) 84 42 A4
AOUTL1- 85 41 A3
AOUTL1+ 86 40 A2
VRDAL 87 39 A1
AVSS 88 38 A0
AVSS 89 37 DVSS
AVDD 90 36 DVDD
VRDAH 91 35 WE
NC 92 34 RAS
VRADL 93 33 CAS
AVSS 94 DRDY C
32
AVDD 95 31 RDY
VRADH 96 30 SO
AINR- 97 29 SI
AINR+ 98 28 SCLK
AINL- 99 27 RQ
AINL+ 100 26 JX
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
SDOUTD1
SDOUTD2
SDOUTD3A
SDOUT
SMODE
SDIN1
SDIN2
BVSS
AVSS
DVSS
CODEC_RESET
SDINA
CKS
SMUTE
XTO
INIT_RESET
DSP_RESET
AVDD
DVDD
CLKO
LFLT
XTI
PLL
LRCLK
BITCLK
AVH-P7500DVD/UC 61
5 6 7 8
1 2 3 4
*AN8011S
Latch
DTCI
Out1
FB-1
A
VREF
IN-1
IN+
VCC
16
15
14
13
12
11
10
9
Latch Error amp.
_
_ +
VREF PWM1
Unlatch pro. _
+
+ _
_ +
Short pro +
B U.V.L.O.
+
_
Unlatch pro. _
+
OSC _ PWM2
+
_
On/
Off
Error amp.
1
RT 2
8
IN-2
DTC2
FB2
Out2
GND
CT
On/Off
*AN8015SH
CT 1 10 FB
Triangular
wave OSC
D
Clamp
0.5V
Error
RT 2 S.C.P.
amp. 9 IN-
comp.
-
I -
+
+
S.C.P. 3 1.83V
8 IN+
VREF
2.46V
GND 4 S R R O 7 VREF
Latch U.V.L.O.
E Reference
supply
OUT 5 + 6 VCC
11.1V
PWM
comparator
62 AVH-P7500DVD/UC
1 2 3 4
*AN8471SAT1
5
5
1
32
VHB VLP
HIGH PRESS
2
31
H3L OSC CIRCUIT VM1
3
30
H3H BMS
4
29
H2L HEAT NC
PROTECTION
LOGIC CIRCUIT
5
28
H2H A12
6
27
H1L A11
6
6
7
26
H1H CS1
HALL
DISTRIBUTION PRE-
8
AMP
25
EC CIRCUIT DRIVER A22

MATRIX BRIDGE
9
24
ECR A21
10
23
FG1 CS2
AVH-P7500DVD/UC
PWMOUT
11
22
START A32
HALL DIRECTION
BIAS CHANGE
12
21
VPUMP A31
7
7
START/
13
20
BC1 FG2
SRESET
1
STOP
16
VT
17
64
14
19
BC2 VM2
x5
VCT CSOUT
15
18
BC3 VDD
*AN8703FH
16
17
BC4 GND
8
8
49
32
33
48
63
F
E
B
A
D
C
F
E
B
A
D
C
64
1
1
ASOUT
FBAL
FEOUT
RFOUT
DCRF
VFSHORT
TESTSG
RFINN
RFINP
PEAK
BOTTOM
RFENV
DCFLT
AGCLVL
DFLTOP
DFLTON
AGCBAL
AGCOFST
FEN
RFC
20 7 21 22 37 35 38 5 46 48 47 43 42 41 32 25 31 30 19 23
- Block diagram
+
+ - HOLD
-
+
-
VIN5 49 -
+
VIN6 50 FBAL +
- +
VIN7 51
-
VIN8 52
+ Level
- BDO Cont.
2
2
Cont 40 BDO
VGA EQ
Vel Adj. Level
+
OFTR Cont.
ADD - Det.
FC Boost 39 OFTR
Cont CONT
ADD SW +
VIN9 53 45 AGCO
- AGG
VIN10 54 Cont. 44 AGCG
ADD
AVH-P7500DVD/UC
A
M
P 29 VHALF
3
3
VIN11 62 27 VREF2
TBAL
VIN12 63
VIN1 57 EQ 56 VREF1
VIN2 58 EQ Differential 36 VCC3
TBAL
VIN3 59 EQ Phase Det. 28 VCC2
VIN4 60 EQ
55 VCC1
33 GND3
ADD Mirro
Det. REG 26 GND2
-
+
ADD + 61 GND1
-
+
-
LPC AMP SIF
4
4
J-Line S-Line
16 15 34 24 8 6 17 18 4 3 2 1 64 14 13 12 11 10 9
TEN
SCK
SEN
STDI
LPC2
LPC1
IDGT
MON
RSCL
TBAL
DTRD
JLINE
POFLT
LPCO2
LPCO1
TEOUT
RFDIFO
HDTYPE
STANBY
5 6 7 8
*BP5451
Over current
protect
PWM
controller
B
Over current
protect
C
1 2 3 4 5 7 8 9 10 11 12 13 15 16 17
- Pin Function (M35014-001SP)

Pin No. Pin Name I/O Function and Operation
1 OSC1 I External oscillation circuit I/O
2 OSC2 O External oscillation circuit I/O
3 cs I Chip select input
4 SCK I Serial clock input D
5 SIN I Serial data input
6 ac I Auto-clear input
7 VDD2 Power supply
8 CVIDEO O Composite video output
9 LECHA I Character level input
10 CVIN I Composite video input
11 VSS Ground
12-15 P0-3 O Output port P0-3
16 OSCOUT O External Sync oscillation circuit I/O
17 OSCIN I External Sync oscillation circuit I/O
18 HOR I H sync
E
19 VERT I V sync
20 VDD1 Power supply
*M35014-001SP: UC Model
10
1
11
20
AVH-P7500DVD/UC 65
5 6 7 8
1 2 3 4
*M2V64S40DTP-6L
A
Vdd 1 54 Vss
DQ0 2 53 DQ15
VddQ 3 52 VssQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VssQ 6 49 VddQ
DQ3 7 Pin name Function 48 DQ12
CLK Master clock
B DQ4 8 47 DQ11
CKE Clock enable
VddQ 9 cs Chip select 46 VssQ
ras Row address strobe
DQ5 10 45 DQ10
cas Column address strobe
DQ6 11 we Write enable 44 DQ9
VssQ 12 DQ0-15 Data input/output 43 VddQ
DQM(U/L) DQ mask enable(Upper/Lower)
DQ7 13 A0-11 Address input
42 DQ8
Vdd 14 BA0, 1 Bank address 41 Vss
VDD Power supply
DQML 15 40 NC
VDDQ Data output power supply
we 16 VSS GND 39 DQMU
C VSSQ Data output GND
cas 17 38 CLK
ras 18 37 CKE
cs 19 36 NC
BA0(A13) 20 35 A11
BA1(A12) 21 34 A9
A10 22 33 A8
A0 23 32 A7
A1 24 31 A6
D A2 25 30 A5
A3 26 29 A4
Vdd 27 28 Vss
66 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*MN5B00UB S P A
E C P E
P X E E A A X E
C D L X X N T U L X N
M D O V T R B P P O D S R B N H N
C V I U D E C C V C A U V I E C C H I H
K D N T D S K K S K T T S N E K K D N R
O D 2 0 I T 0 0 S 0 H 0 S 0 N 1 1 K T E
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
BPMOUT 61 40 VDD
B
VSS 62 39 NHCS
DOUT1 63 38 BOPT
CAPSHIFT 64 37 NHWE
VDD 65 36 VDD
BCKO 66 35 HA2
LRCKO 67 34 VSS
MINTESTGZ 68 33 EXDCK
VSS 69 32 N.C.
EXPCK1 70 31 NRESET
VDD 71 30 VDDI
ERR 72 29 HA1
AUXINFO 73 28 HA0
C
NRQ 74 27 HD7
VAL 75 26 HD6
DOUT2 76 25 VDD
STRIN7 77 24 VDD
NSDRDY 78 23 HD5
WRITE 79 22 VSS
RAMTEST 80 21 HD4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
N V E V S V F S H H T V C H V V H C D T
S D X S T D R Y D D D S P D D S D P I D
O D S S R D A N 0 1 S S U 2 D S 3 U N S
E I C O M C P S S 1 P
N K U E E E O
T L L
7 1 0
*MN677531KAUB
104
53
105 52 E
156 1
208
157
AVH-P7500DVD/UC 67
5 6 7 8
1 2 3 4
- Pin Functions (MN677531KAUB)

A Pin No. Pin Name I/O Function and Operation
1 VDD Power supply

2 MA0 O Bank sell and address
5 LVDD Lch Power supply
B 8 MA4 O Bank sell and address
9 VSS GND
11 VDD Power supply
12 HMD I Host CPU select
13 XRST I System reset
14 ERRMON O Error monitor
15 RFF O Repeat first field flag output
C
17 XHINT O Interrupt strobe
18 XHINT2 O Interrupt strobe
19 XKD O Data acknowledge to host
20 VSS GND
21 XWRH I Write enable from host
22 XWR I Write enable
23 XRD I Read enable
24 XCS I Chip select
D 25 VDD Power supply
26 HCLK I Host CPU clock
27-30 HA1-4 I Address bus
31 VSS I GND
43 VSS GND
E
47 HD0 I/O Data bus
48 VDD Power supply
49-52 HD1-4 I/O Data bus
53 VSS GND
61 VDD Power supply
F 62,63 HD11,12 I/O Data bus
68 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
Pin No. Pin Name I/O Function and Operation A
64 VSS GND
68 VDD Power supply
69 AUDSTR I Data strobe
70 VSTR I Data strobe
71 VRQ O DMA request
72 VSS GND
73-76 STD7-4 I Stream data/CD-Audio bypass port B
77 LVDD Lch power supply
78-81 STD3-0 I Stream data/CD-Audio bypass port
82 VSS GND
83 IECOUT O IEC958 data output
84 DMIX O Sound down mix. signal
85 VDD Power supply
86 DACCK O DAC clock output
87 LRCK O LR clock output
C
88 SRCK O Bit clock output
89 VSS GND
90-92 ADOUT0-2 O Audio data output
93 VDD Power supply
94 CLK121 I 121.5MHz clock input
95 CKIO I 81MHz clock select
96 CLK27 I 27MHz clock input
97 PLLVDD PLL
98 CLK81 I 81MHz clock input D

100 EXTCK I Outside clock output
101 PLLAVDD PLL analog power supply
102 TCPOUT O OPEN
103 PLLAVSS OPEN
104 VSS GND
105 VDD Power supply
106 PHCOPMO O OPEN
E
107 PLLAVDD PLL analog power supply
108 ACKIO I Audio PLL test mode
109 MODE121 I Clock mode select
110 DCTEST I DC test mode
111 APLLAVSS Analog PLL audio GND
112 APLLAVDD Analog PLL power supply
113 VREFCR I DAC reference input for CR signal
114 IREFCR I DAC resistance terminal for bias current setting for CR signal
115 COMPCR I DAC capacity connection terminal for stabilization for CR signal F
116 VCROUT O DAC output for CR signal
AVH-P7500DVD/UC 69
5 6 7 8
1 2 3 4
A Pin No. Pin Name I/O Function and Operation
117 AVDD Analog power supply

118 VREFC I DAC reference input
119 IREFC I DAC resistance terminal for bias current setting
120 COMPC I DAC capacity connection terminal for stabilization
121 VCOUT O Cr C analog output
122 AVSS Analog GND
123 VREFCB I DAC reference input for CB signal
B 124 IREFCB I DAC resistance terminal for bias current setting for CB signal
125 COMPCB I DAC capacity connection terminal for stabilization for CB signal
126 VCBOUT O DAC output for CB signal
127 AVDD Analog power supply
128 VREFY I DAC reference input
129 IREFY I DAC resistance terminal for bias current setting
130 COMPY I DAC capacity connection terminal for stabilization
131 VYOUT O Y analog output
132 AVSS Analog GND
C
133,134 TESTSEL1,0 I Test signal
135 VSS GND
136 VCLK I Video data clock
137-140 REC7-4 I/O OPEN
142,143 REC3,2 I/O OPEN
144 REC1/ I/O OPEN
XVSYNCO
D 145 REC0/ I/O OPEN
XHSYNCO
146 LVDD Lch power supply
147-150 VD0-3 O Video data bus
151 VSS GND
152-155 VD4-7 O Video data bus
157 VSS GND
158 MDQ15 I/O I/O data SDRAM
E
162 MD1 I/O I/O data SDRAM
163 VSS GND
F 167 MDQ12 I/O I/O data SDRAM
70 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
Pin No. Pin Name I/O Function and Operation A
169 VSS GND

176 VSS GND B
182 VSS GND
183 MCK1 I SSDRAM CLK input
C
185 MCK O SDRAM CLK
186 VSS GND
187 DQMLE O Lower byte DQ mask of extended SDRAM
189 DQMLM O Lower byte DQ mask of main SDRAM
190 DQMUE O Upper byte DQ mask of extended SDRAM
192 DQMUM O Upper byte DQ mask of main SDRAM
193 XWE O Write signal of SDRAM D
194 VSS GND

195 XCAS O CAS of SDRAM
196 XRAS O RAS of SDRAM
198 XCSE O CS of extended SDRAM
199 XCSM O CS of main SDRAM
200 VSS GND
E
208 VSS GND
AVH-P7500DVD/UC 71
5 6 7 8
1 2 3 4
- Pin Functions (MNZS26EDCUB)

A 1,2 NINT0,1 O System computer interrupt signal
3 VDD3 O Power supply
4 VSS GND
5 NINT2 System computer interrupt signal
6 WAITODC O System computer bus wait control out put
7 NMRST O Reset output to system computer
8 DASPST O DASP initialize value input
9-17 CPUADR17-9 I System computer address input
18 ADD18 Power supply for I O
19 VSS GND
20 DRAMVDD18 Power supply for DRAM
B 21 DRAMVSS GND for DRAM
22-30 CPUADR8-0 I System computer address
32 VSS GND
34 NCS I Chip select signal from system computer
35 NWR I Write signal input from system computer
36 NRD I Read signal input from system computer
37-44 CPUDT7-0 I/O System computer data
45 CLKOUT O System computer clock output
46 MMOD I GND
C
47 NRST I Reset input
48 MSTPOL I Pull up
49 SCLOCK I/O Pull up
50 SDATA I/O Pull up
51 OFTR I Off track signal input
52 BDO I RF dropout signal input
53-56 PWM1-4 I/O PWM output
59 DRAMVSS GND for DRAM
D 60 VSS GND
61-64 PWM5-8 I/O PWM put out
65 TBAL O Tracking balance adjustment output
66 FBAL O Focus balance adjustment output
67 TRSDRV O Traverse driver output
68 SPDRV O Spindle driver output
69 FG I FG signal input
70 TILTP O TILTP pin
71 TILT O TILT pin
72 TILTN O TILTN pin
73 TX O Digital audio interface data output
E 74 DTRD O Data read control signal output
75 IDGT O Not used
77 VSS GND
79 OSCI1 I Oscillator pin input
80 OSCO1 O Oscillator pin output
81 VSS GND
82 TSTSG O Calibration signal output
83 VFOSHORT O VFO short output
F
84 JLINE O J-LINE output
85 AVSSD GND for analog
86 ROUT O Analog audio right output
72 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8

87 LOUT O Analog audio left output A
88 AVDDD Power supply for analog
89 VCOS I JFVCO control voltage
90 TRCRS I Track cross production signal input
91 CMPIN I WOBBLE comparator input
92 LPFOUT O LPF output
93 LPFIN I LPF input
94 AVSSC GND for analog
95 HPFOUT O HPF output
96 FPFIN I HPF input
97 CSLFLT I Capacitor for CPDET
98 RFDIF I RF input for CPDET B
99 AVDDC Power supply for analog
100,101 PLFLT2,1 I PLL capacitor output
102 AVSSB GND for analog
103 RVI I VERFH reference current resistor input/output
104 VREFH I Reference voltage (2.2±0.1V)
105 PLPG I PLPG pin
106 VHALF I Reference voltage (1.65±0.1V)
107,108 DSLF2,1 I DSL capacitor input/output 1
109 AVDDB Power supply for analog
110 NARF I Equivalent RF-input
C
111 ARF I Equivalent RF+ input
112 JITOUT O Jitter signal monitor input/output
113 AVSSA GND for analog
114 DAC0 O Tracking drive output
115 DAC1 O Focus drive output
116 AVDDA Power supply for analog
117 AD0 I FE input
118 AD1 I TEph / TE3b / TEpp input
119 AD2 I AS input
120 AD3 I RF env input
121 AD4 I VHALF connect D
122 AD5/CAPAC2 I VHALF connect
123 AD6/CAPAC1 I VHALF connect
124 TECAPA I VHALF connect
126 VSS GND
127-130 MONI0-3 O Monitor for inside signal
131 NEJECT I/O Eject sense
132 NTRYCL I/O Try close sense
133 NDASP I/O ATAPI drive active/slave connect input/output
134 NCS3FX I ATAPI HOST chip select
135 NCS1FX I ATAPI HOST chip select E
136 DA2 I/O ATAPI HOST address input/output 2
138 NPDIAG I/O ATAPI slave/master diagnosis input/output
140 NIOCS16 O ATAPI HOST data bus width select output
141 INTRQ O ATAPI HOST interrupt request output
142 NDMACK I ATAPI HOST DMA response
144 VSS GND
145 IORDY O ATAPI HOST ready output
F
146 NIORD I/O ATAPI HOST data read
147 NIOWR I/O ATAPI HOST data write
AVH-P7500DVD/UC 73
5 6 7 8
1 2 3 4

148 DMARQ O ATAPI HOST DMA request output
149 HDD15 I/O ATAPI HOST data input/output 15
153 PO I (GND)
154 UATASEL I Internal clock select input
155 VSS GND
B
163 VSS GND
C 166 HDD10 I/O ATAPI HOST data input/output 10
169 HDD3 ATAPI HOST data input/output 3
170 VSS GND
174 VDDH ATAPI reference power supply (5.0V)
175 NRESET I ATAPI host reset input
176 MASTER I ATAPI master/slave select input/output
D
*MNZS26EDCUB
45
88
89 44
132 1
176
133
74 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*PCM1604Y-2
A
AGND0
AGND1
AGND2
MDO
VCC0
VCC1
VCC2
MDI
MC
ML
NC
NC
36 35 34 33 32 31 30 29 28 27 26 25
RST 37 24 VCC3
SCKI 38 23 ADND3
SCKO 39 22 VCC4
BCK 40 21 ADND4 B
LRCK 41 20 VCC5
TEST 42 19 ADND5
VDD 43 18 VCC6
DGND 44 17 ADND6
DATA1 45 16 CAP1
DATA2 46 15 CAP2
DATA3 47 14 VOUT1 C
ZEROA 48 13 VOUT2
1 2 3 4 5 6 7 8 9 10 11 12
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
AGND
VCC
VOUT6
VOUT5
VOUT4
VOUT3
D
CAP1
CAP2
- Block diagram
LRCK 2ch VOUT1

BCK LFP VOUT2
DATA1(VOUT1,2) Serial DAC +
input I/F Output Amp
DATA2(VOUT3,4)
DATA3(VOUT5,6) Multi Function. Multi Level
Digital Filter Module
2ch VOUT3
LFP VOUT4
ML DAC + E
MC Output Amp
Mode
Control
MDI BPZ
I/F
MDO Control 0 2ch VOUT5
indication LFP VOUT6
RST DAC +
Output Amp
ZEROA
ZERO1/GPO1
~
SCKI
Clock Manager +3.3V Power supply +5V
SCKO ZERO6/GPO6
VDD DGND VCC AGND VCC

AGND F
AVH-P7500DVD/UC 75
5 6 7 8
1 2 3 4
*PD5869A
P07
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
A
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PO6 61 40 P43
PO5 62 39 P50
PO4 63 38 P51
PO3 64 37 P52
PO2 65 36 P53
PO1 66 35 P54
PO0 67 34 P55
P107/AN7/KI3 68 33 P56
P106/AN6/KI2 69 32 P57/CLKOUT
B P105/AN5/KI1 70 31 P60/CTS0/RTS0
P104/AN4/KI0 71 30 P61/CLK0
P103/AN3 72 29 P62/RXD0
P102/AN2 73 28 P63/TXD0
P101/AN1 74 27 P64/CTS1/RTS1/CLKS1
AVSS 75 26 P65/CLK1
P100/AN0 76 25 P66/RXD1
VREF 77 24 P67/TXD1
AVCC 78 23 P70/TXD2/SDA/TA0OUT
P97/ADTRG/SIN4 79 22 P71/RXD2/SCL/TA0IN/TB5IN
P96/ANEX1/SOUT4 80 21 P76/TA3OUT
C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P95/ANEX0/CLK4
P94/DA1/TB4IN
P93/DA0/TB3IN
P92/TB2IN/SOUT3
P90/TB0IN/CLK3
CNVSS(BYTE)
P87/XCIN
P86/XCOUT
RESET
XOUT
VSS
XIN
VCC
P85/NMI
P84/INT2
P83/INT1
P82/INT0
P81/TA4IN
P80/TA4OUT
P77/TA3IN
8 8 8 4 8 8
I/O Port Port P0 Port P2 Port P3 Port P4 Port P5 Port P6

Port P7
Peripheral
System Clock 4
Timer A/D convert XIN-XOUT
Timer TA0(16 bit) XCIN-XCOUT
Timer TA1(16 bit)
Port P8
Timer TA2(16 bit) Clock synchronism SI/O

UART/Clock synchronism SI/O
Timer TA3(16 bit) (8 bit X 2 ch)
(8 bit X 3 ch)
Timer TA4(16 bit)
7
Timer TB0(16 bit)

E Timer TB1(16 bit)
CRC operation
Timer TB2(16 bit)
Port P85
Timer TB3(16 bit)

Timer TB4(16 bit) 16 bit CPU core
Timer TB5(16 bit) Memory
Resister Program Counter
PC ROM
Surveillance Timer (15 bit)
Port P9
R0H R0L Stack Pointer

R1H R1L ISP
R2 USP RAM
7
DMAC(2 ch) R3
A0 Vector Table
A1 INTB
Port P10
D/A convert FB
Flag Resister Multipler
SB FLG
F
8
76 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*PCM1742KE
BCK 1 16 SCK A
Audio
DATA 2 Serial 15 ML
Port
Output Amp and

DAC
LRCK 3 Low-Pass Filter 14 MC
4x/8x
Over sampling Enhanced
DGND 4 Digital Filter Multilevel 13 MD
with Delta-Sigma
Serial Function Modulator
Control Controller
VDD 5 Port Output Amp and
12 ZEROL/NA
DAC
Low-Pass Filter
VCC 6 11 ZEROR/ZEROA B
System Clock
VOUTL 7 Zero Detect 10 VCOM
System Clock
VOUTR 8 Manager 9 AGND
*PD6340A
32
17
C
33 16
48 1
D
49
64
- Pin Functions (PD6340A)

1-5 SEG5-1 O LCD segment output
6-9 COM4-1 O LCD common output
10 VLCD LCD drive power supply
11-14 KST4-1 O Key strobe output
15,16 KDT1,2 I Key data input (analogue input)
17 REM I Remote control reception input
18 DPDT I Display data input
E
19 NC Not used
20 KYDT O Key data output
21 MODA GND
22 X0 Crystal oscillator connection pin
23 X1 Crystal oscillator connection pin
24 VSS GND
25,26 KDT3,4 I Key data input
27 NC Not used
28 NC O Not used
29-32 NC Not used
56 VDD Power supply F
AVH-P7500DVD/UC 77
5 6 7 8
1 2 3 4
*PD6408D
A
A15 1 48 A16
A14 2 47 BYTE
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A-1,A0-A17 : Address input
A10 6 DQ0-DQ15 : Data input/output 43 DQ14
A9 7 ce : Chip enable 42 DQ6
B A8 8 oe : Output enable 41 DQ13
A19 9 we : Write enable 40 DQ5
reset : Hardware reset
N.C. 10 RY/by : Ready/Busy output 39 DQ12
WE 11 byte : 8bit,16bit mode select 38 DQ4
RESET 12 VCC : Supply voltage 37 VCC
VSS : GND
N.C. 13 N.C. : Not used 36 DQ11
N.C. 14 35 DQ3
RY/BY 15 34 DQ10
C A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE
A3 22 27 VSS
A2 23 26 CE
A1 24 25 A0
D
78 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*PD8113A A
*PD8114A
NC 1 44 A20
A18 2 43 A19
A17 3 42 A8
A7 4 41 A9
A6 5 40 A10
A5 6 39 A11
A4 7 38 A12 B
A3 8 37 A13
A2 9 36 A14
A1 10 35 A15
A0 11 34 A16
CE 12 33 BYTE
VSS 13 32 VSS
OE 14 31 D15/A-1
C
D0 15 30 D7
D8 16 29 D14
D1 17 28 D6
D9 18 27 D13
D2 19 26 D5
D10 20 25 D12
D3 21 24 D4
D11 22 23 VCC D
Pin Name Function

D15/A-1 Data output/Address input
A0~A20 Address input
D0~D14 Data input E
CE Chip enable
OE Output enable
BYTE Mode switch
VCC Power supply
VSS GND
NC Not connect
AVH-P7500DVD/UC 79
5 6 7 8
1 2 3 4
- Block diagram
A A-1
x8/x16 Output select
CE OE
BYTE
CE OE
A1
Row Decoder
A2
A3 Memory Cell Matrix
A4
A5
A6 2,097,152 x 16-Bit or 4,194,304 x 8-Bit
A7
Address Buffer
A8
A9
C A10
A11
A12
A13 Multiplexer
Colmn Decoder
A14
A15
A16
A17
A18 Output Buffer
A19
A20
D
D0 D2 D4 D6 D8 D10 D12 D14
D1 D3 D5 D7 D9 D11 D13 D15
80 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- Pin Function (PE5300A)

Pin No. Pin Name I/O Format Function and Operation A
1 NC OPEN (Not used: L fixed)
2 TVSDST I C Station/stereo detection input
3 TVBIL I C OPEN (Not used with this product)
4 AVSS Hideaway single operation test mode input
6 TVMPX O C OPEN (Not used with this product)
7 AVREF1 D/A converter reference voltage input
8-10 NC OPEN (Not used: L fixed)
11 SDTSDA I/O C Serial data input /output for TV tuner PLL
12 SCKSCL I/O C Serial clock input for TV tuner PLL
13 SCE O C OPEN (Not used with this product)
14 SDA I/O C Serial data input/output B
15 SCL I/O C Serial clock input
16 TSI I C Factory test mode data input
17 TSO O C Factory test mode data output
18 TSCK O C Factory test mode clock output
19 TVSEEK O C OPEN (Not used with this product)
20 TRAPSW O C TV tuner trap filter ON/OFF output
21 BRSBGI O C TV tuner country code BG/I output
22 BRSDKI O C TV tuner country code DK/I output
24 OSDDT O C OSD serial data output
25 OSDCK O C OSD serial clock output C
26 OSDCS O C OSD chip select output
27 OSDAC O C OSD all clear output
28 TVSEL O C TV tuner source on selection output
29 LEDPW O C OPEN (Not used with this product)
30 REMUPW O C OPEN (Not used with this product)
31 RVSEL O C OPEN (Not used with this product)
32 FVSEL O C Main video output selection control
33 VSS Microcomputer ground
34 RVMUTE O C Rear video output MUTE
35 FVMUTE O C Main video output MUTE
40 SMODE1 I C OSD position adjustment (for service) D
50 SMODE2 I C Video level adjustment (for service)
52 OSDARI I C Front monitor OSD ON/OFF (H:OFF, L:ON)
53 IPLASW I C IP-BUS slave address selection SW input (L fixed)
54 IPORAD O C OPEN (Not used with this product)
55 IPPW O C IP-BUS driver power supply control output
56 TX(IP-BUS) O C IP-BUS data output
57 RX(IP-BUS) I C IP-BUS data input
58 MUTEIP O C IP-OUT audio mute output
59 MUTERE O C Rear OUT audio mute output
E
60 RESET I Reset input
61 REMIN I C Remote control input
62 BSENS I C Backup sense input
63 ASENS I C ACC sense input
64 PBSENS I C OPEN (Not used with this product)
65 ILMSEN O C OPEN (Not used with this product)
66 DSENS O C OPEN (Not used with this product)
67 OPSENS O C OPEN (Not used with this product)
68 VDD Microcomputer power supply
69, 70 X2, 1 Microcomputer system clock oscillation crystal connection
71 IC(Vpp) Microcomputer ground connection
72 XT2 Sub clock input (Not connected) F
73 TESTIN I Chip test input
74 AVDD A/D converter analog power supply
AVH-P7500DVD/UC 81
5 6 7 8
1 2 3 4
Pin No. Pin Name I/O Format Function and Operation

A
75 AVREF0 A/D converter reference voltage input
76 TVSL I C TV tuner signal level analog input
77 TVSIM I C TV tuner version selection input
79 TVPW O C TV power supply control output
80 SYSPW O C System power supply control output
*PE5300A
Format Meaning
C C MOS
61
80
1 60
B
20 41
21
40
C
VCO FILTER 1
VCO FILTER 2
NJW1303V : UC model
VCO OUT
GND
BGP
LPF
VS
14 13 12 11 10 9 8
V Sync Sep V count down
BGP Generator
Reg H count down
Sync Sep Phase Det 32fH VCO

E
1 2 3 4 5 6 7
C SYNC OUT
SYNC IN
VCC
VD
HD
DIGREF
SW
82 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- Pin Function(PE5366A)
Pin No Pin Name I/O Format Function and Operation A
1-7 D14-8 I/O C Data bus
8 Vdd Power supply
9 Vss GND
10-17 D7-0 I/O C Data bus
18 MODE2/Vpp Mode select / Vpp
19 /IRL I C GDC request
20 MFLPW O C TFT backlight
21 MVIPW O C Video Power supply output
22 PAL/NTSC O C PAL/NTSC test output
23 NC O C Not used
24 /EPRRST I C EEPROM reset input
B
25 /EPRTEST I C EEPROM test input
26 NC O C Not used
27 Vdd Power supply
28 Vss GND
29-32 NC O C Not used
33 DIMMER O C Dimmer output
37 Vdd Power supply
38 Vss GND
39 NC O C Not used
40 PNLXV O C Hi output is carried out when X directions is detected
C
41 PNLYV O C Hi output is carried out when Y directions is detected
42 /STEST I C Monitor operation mode input
43 INVPUL O C Inverter pulse output
44 /STEST2 I C Touch panel test mode input
45 NC O C Not used
46 /NMI I C Not used
47 Vdd Power supply
48 Vss GND
49 NC O C Not used
50 GDCPW O C GDC IC power supply output
51 /GDCRES O C GDC IC reset output
D
52 RX2 O C Input terminal
53 TX2 O C Output terminal
54 LDIMMER O C LCD dimmer output
55,56 NC O C Not used
57,58 MODE1,0 Mode terminal
59 RESET Reset input
60 CKSEL Clock generator select
61 CVdd Clock generator power supply
62,63 X2,1 Oscillation pin
64 CVss Clock generator GND
65 LSWVDD O C LCD micro computer power supply control output
66 LKYDT I C Data input from LCD micro computer E
67 LDPDT O C Data output to LCD micro computer
68 LBKL O C LCD micro computer back light power supply control output
69 DPDT I C Data input for test mode/Data input from system micro computer
70 KYDT O C Data output for test mode/Data output to system micro computer
71 Avdd/Avref A/D power supply
72 Avss A/D GND
73-75 KDT2-0 I AD Key input
76 NC I AD Not used
77 SPEANA I AD Spectrumanalyzer level input
78 PNLADY I AD Y directions analog input
79 PNLADX I AD X directions analog input F
80 LSEN I AD Lens sense input
AVH-P7500DVD/UC 83
5 6 7 8
1 2 3 4
A Pin No Pin Name I/O Format Function and Operation

81 Vdd Power supply
82 Vss GND
83-85 SP2-0 O C Spectrumanalyzer band select output
86 EPRCS O C Memory for adjustment chip select output
87 EPRCLK O C Memory for adjustment clock output
88 EPRDO O C Memory for adjustment data output
89 EPRDI I C Memory for adjustment data input
90 /EPRPROT O C Memory for adjustment protect output
91 /WAIT I C GDC wait input
92 /VDDSENS I C EEPROM power supply
93 /YS STOP O C YS stop output
B
94 TOP OSD O C NAVI/GDC select output
95 /RD O C Read output
96 /UWR O C RAM write output
97 /LWR O C RAM write output
98 Vdd Power supply
99 Vss GND
100 SELFOUT O C Self write output
101 SELFIN I C Self write input
102 NC O C Not used
103 /CS4 O C RAM chip select output
104 /CS3 O C ROM chip select output
C
105 NC O C Not used
106 BK_REV O C Back camera reverse output
107 PIPDT I/O C Pin P IC data input output
108 PIPCLK I/O C Pin P IC clock output
109 /PIPRES I/O C Pin P IC reset output
110 SYNCKIND I C RGB signal input
111 DISPMUTE O C Video mute output
112 Vdd Power supply
113 Vss GND
114 A25 O C Not used
115 A24 O C Not used
D
116-123 A23-16 O C Address bus
125 Vss GND
135 Vss GND
143 A0 O C Not used
144 D15 I/O C Data bus
*PE5366A
E
109
144
1 108
F 36 73
37
72
84 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*PE5395A
PCD2/LBE/SDCAS
PCD0/SDCKE
PCD1/SDCLK
PDL15/D15
PAL10/A10
PAL11/A11
PAL12/A12
PAL13/A13
PAL14/A14
PAL15/A15
PAH0/A16
PAH1/A17
PAH2/A18
PAH3/A19
PAH4/A20
PAH5/A21
PAH6/A22
PAH7/A23
PAH8/A24
PAH9/A25
A
PAL0/A0
PAL1/A1
PAL2/A2
PAL3/A3
PAL4/A4
PAL5/A5
PAL6/A6
PAL7/A7
PAL8/A8
PAL9/A9
VDD
VDD
VDD
VSS
VSS
VSS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
D14/PDL14 1 108 PCD3/UBE/SDRAS
D13/PDL13 2 107 PCS0/CS0
D12/PDL12 3 106 PCS1/CS1/RAS1
D11/PDL11 4 105 PCS2/CS2/IOWR
D8/PDL8 7 102 PCS5/CS5/IORD
VDD 8 101 PCS6/CS6/RAS6
VSS 9 100 PCS7/CS7
D7/PDL7 10 99 VSS
D6/PDL6 11 98 VDD
D5/PDL5 12 97 PCT0/LCAS/LWR/LDQM
D4/PDL4 13 96 PCT1/UCAS/UWR/UDQM
D3/PDL3 14 95 PCT4/RD B
D2/PDL2 15 94 PCT5/WE
D1/PDL1 16 93 PCT6/OE
D0/PDL0 17 92 PCT7/BCYST
MODE2 18 91 PCM0/WAIT
DMARQ3/INTP103/P07 19 90 PCM1/CLKOUT/BUSCLK
DMARQ2/INTP102/P06 20 89 PCM2/HLDAK
DMARQ1/INTP101/P05 21 88 PCM3/HLDRQ
DMARQ0/INTP100/P04 22 87 PCM4/REFRQ
TO00/P03 23 86 PCM5/SELFREF
INTP001/P02 24 85 P50/INTP030/TI030
TI000/INTP000/P01 25 84 P51/INTP031
PWM0/P00 26 83 P52/TO03
VDD 27 82 VSS
VSS 28 81 VDD
DMAAK3/PBD3 29 80 P70/ANI0
TO01/P13 33 76 P74/ANI4
INTP011/P12 34 75 P75/ANI5
TI010/INTP010/P11 35 74 P76/ANI6
PWM1/P10 36 73 P77/ANI7
C
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NMI/P20
MODE1
MODE0
X2
X1
TXD2/INTP133/P33
TXD1/SO1/P43
TXD0/SO0/P40
VDD
VDD
VSS
VSS
TO02/P23
INTP021/P22
TI020/INTP020/P21
ADTRG/INTP123/P37
INTP122/P36
INTP121/P35
RXD2/INTP120/P34
SI2/INTP131/P31
SO2/INTP130/P30
RXD1/SI1/P44
RXD0/SI0/P41
AVSS
CVDD
TC3/INTP113/P27
TC0/INTP110/P24
SCK2/INTP132/P32
CVSS
CKSEL
SCK1/P45
SCK0/P42
TC2/INTP112/P26
TC1/INTP111/P25
RESET
AVDD/AVREF
- Block diagram
NMI HLDRQ
CPU BCU MEMC HLDAK
INTP100-INTP103, CS0,CS7
INTC
INTP110-INTP113, CS1/RAS1,CS3/RAS3
INTP120-INTP123, ROM CS4/RAS4,CS6/RAS6
INTP130-INTP133 Instruction DRAMC
PC CS2/IORD
Queue CS5/IOWR D
INTP000,INTP001, SELFREF
INTP010,INTP011, Multplier REFRQ
INTP020,INTP021, (32 x 32->64) BCYST
INTP030,INTP031 32bit LBE/SDCAS
RPU
Ballel Siffer UBE/SDRAS
TO00-TO03 SDCLK
SDCKE
TI000,TI010, WE
TI020,TI030 System RD
Registor OE
SIO RAM ALU UWR/UCAS/UDQM
ROMC
SO0/TXD0 LWR/LCAS/LDQM
SI0/RXD0 UART0/CSI0 WAIT
SCK0 General A0-A25
Register D0-D15
SO1/TXD1 (32bit x 32) BUSCLK
SI1/RXD1 UART1/CSI1
SCK1
DMARQ0-DMARQ3
TXD2 DMAC DMAAK0-DMAAK3 E
UART2 TC0-TC3
RXD2
SO2
SI2 CSI2
SCK2
PWM0 PWM0 Port CKSEL

CLKOUT
PWM1 PWM1 X1
PCM0-PCM5
CG
P20
PDL0-PDL15
PBD0-PBD3
P70-P77
P50-P52
P40-P45
P30-P37
P21-P27
P10-P13
P00-P17
PAL0-PAL15
PAH0-PAH9
PCS0-PCS7
PCD0-PCD3
PCT0,PCT1,PCT4,PCT7
X2
CVDD
ANI0-ANI7 CVSS
AVREF/AVDD ADC
AVSS
ADTRG MODE0-MODE2
F
System RESET
Controller VDD
VSS
AVH-P7500DVD/UC 85
5 6 7 8
1 2 3 4
PQ1X251M2ZP PQ1X331M2ZP
A
Vin 1 5 Vo VIN 1 5 Vo
GND 2 Controller GND 2 Controller
Vc 3 4 NR
Vc 3 4 Nr
B
*S-80827CNUA-B8M *S-80835CNUA-B8U
VSS NC
4 3
VREF
C VREF
1 2
OUT VDD
1 2
VDD 3
OUT
VSS
D
*S-80841CNUA-B82 *S-812C33AUA-C2N
E VREF
Reference
Voltage
1 2 3
1 2 3
GND
VIN
VOUT
VDD
OUT
VSS
86 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*S-812C50AUA-C3E *S-812C56AUA-C3K
A
Reference Reference
Voltage Voltage
1 2 3 1 2 3
B
GND
VIN
VOUT
GND
VIN
VOUT
*S-818A38AUC-BGS
VIN ON/OFF
5 4
VREF ON/OFF
1 2 3
VOUT VSS NC
D
*S-93C46BR0I-J8T1
NC 1 8 TEST
Memory Address
Aray Decoder
VCC 2 Data Resistor Output Buffer 7 GND

E
Mode Decode
Logic
CS 3 6 DO
Clock Pulse Voltage Ditector
Counter
SK 4 5 DI
Clock Oscillater
AVH-P7500DVD/UC 87
5 6 7 8
1 2 3 4
*SI6544DQ
A
1 8
2 7
3 6
B
4 5
*SM5304AV
VIN 1 8th Order

LPF
8 GSEL
ENABLE 2 7 VF
C Clamp
RFC 3 Buffer 6
VOUT
VCC 4 5
GND
*SM8707FV
D VDD1 1 16 NC2
Reference Phase Charge

VSS1 2 LPF 0 VCO 0 15 SO2
Divider 0 Detector 0 Pump 0
MO1 3 14 FSEL
Loop
NC1 4 Divider 0 13 SO1
Control
VDD2 5 Logic 12 VDD3
E
Reference Phase Charge
LPF 1 VCO 1
VSS2 6 Divider 1 Detector 1 Pump 1 11 VSS3
XTI 7 10 AO2
X'tal
OSC Loop
Divider 1
XTO 8 9 AO1
88 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*TC74LCX541FT *TC74VCX00FT
A
OE1 1 20 VCC 1A 1 14 VCC

A1 2 19 OE2
1B 2 13 4B
A2 3 18 Y1
1Y 3 12 4A
A3 4 17 Y2
2A 4 11 4Y
A4 5 16 Y3 B
2B 5 10 3B
A5 6 15 Y4
2Y 6 9 3A
A6 7 14 Y5
A7 8 13 Y6 GND 7 8 3Y
A8 9 12 Y7
GND 10 11 Y8
C
*TC74VCX02FT *TC74VCX32FT
1Y 1 14 VCC 1A 1 14 VCC
1A 2 13 4Y 1B 2 13 4B
D
1B 3 12 4B 1Y 3 12 4A
2Y 4 11 4A 2A 4 11 4Y
2A 5 10 3Y 2B 5 10 3B
2B 6 9 3B 2Y 6 9 3A
GND 7 8 3A GND 7 8 3Y
E
AVH-P7500DVD/UC 89
5 6 7 8
1 2 3 4
*TC7MB3257FK *TC7PA04FU
A
1A 1Y
S 1 16 VCC
1B1 2 15 OE
GND Vcc
1B2 3 14 4B1
B
1A 4 13 4B2 2A 2Y
2B1 5 12 4A
2B2 6 11 3B1
*TC7SZ02FU
2A 7 10 3B2
C
GND 8 9 3A
Input1
1 VCC
5 Output
Input2
2
4
3 GND
D
*TC7SZ04FU *TC7SZ32FU
VCC OUT Y
5 4
E Input1
1 VCC
5 Output
Input2
2
4
3 GND
1 2 3
F NC IN A GND
90 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
*TC7WB126FK *TC7WHU04FU
A
1A VCC
OE 1 8 VDD
3Y 1Y
AI 2 7 OE2
2A 3A
B
B2 3 6 B1
GND 2Y
GND 4 5 A2
*MSM51V4265EP-70TS
*TC7WU04FU C
VCC 1 44 VSS
Vcc 1Y 3A 2Y
DQ1 2 43 DQ16
8 7 6 5 DQ2 3 42 DQ15
DQ3 4 41 DQ14
DQ4 5 40 DQ13
VCC 6 39 VSS
DQ5 7 A0-A8 :Address input 38 DQ12
ras : Row address strobe
DQ6 8 37 DQ11
lcas : Lower column address strobe
DQ7 ucas : Upper column address strobe D
9 36 DQ10
DQ1-DQ16 : Data input/data output
DQ8 10 oe : Output enable 35 DQ9
we : Write enable
VCC : Power supply
1 2 3 4 VSS : GND
NC : No connection
NC 13 32 NC
1A 3Y 2A GND
NC 14 31 lcas
we 15 30 hcas
ras 16 29 oe
NC 17 28 A8
A0 18 27 A7 E
A1 19 26 A6
A2 20 25 A5
A3 21 24 A4
VCC 22 23 VSS
AVH-P7500DVD/UC 91
5 6 7 8
1 2 3 4
*TC90A64AF-P
DVDD-134
BVDD-119
DVSS-136
BVSS-117
A
144
143
142
141
140
139
138
137
135
133
132
131
130
129
128
127
126
125
124
123
122
121
120
118
116
115
114
113
112
111
110
109
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
Vss VDD VDD Vss
RAMVSS-1 1 Vss Vss 108 RAMVSS

STV1 2 NGOE 107 107
STV2 3 STV1 106 106
CPV 4 STV2 105 MUTE
NGOE 5 CPV 104 RESET
RAMVDD-6 6 VDD Control ACK VDD 103 RAMVDD-103
POLS 7 POLS NDSV 102 NDSH
CPH 8 CPH SCKE 101 SCKE
B CLMPO 9 CLMPO NDSH 100 NDSV
DVSS-10 10 Vss 99 IICDA
VCO Monitor Bus
VCOM 11 VCOM VDD 98 DVDD-98
Inter
DVDD-12 12 VDD STH1 Face 97 97
CX 13 STH2 96 IICCK
2M
STH1 14 CX Memory 95 95
FNAVI
STH2 15 Vss 94 DVSS-94
R
DVSS-16 16 Vss OSD
Side
93 FNAVI
Output RGB PIP
17 17 G 92 BLNK
HD1
OSD OSD
HDIN 18 Switch Matrix Process 91 OSDB
VD1 B Color
VDIN 19 Inter 90 OSDG
C.Sync1 Palette Face
SYNC1 20 C.Video 89 OSDR
Cont./Bright
CKP 21 CKP 88 SYNC2
C.Sync2
HREF
HREFOUT 22 Y U V 87 CLMP1
C CKPSEL 23 CKPSEL Cont./Bright 86 CLMP2
γ Process Color
BVDD-24 24 VDD Decode VDD 85 DVDD-85
BVSS-25 25 Vss Signal C.Video C VDD 84 BVDD-84
Polarity Side XO
AVSS-26 26 Vss Sub Timing 42 M 83 XI
NTSC:2line Pulse Gene
POLC Y/C Sep
BIAS1 27 RGB 82 XO
Side PAL:LPF/BPF
POLC 28 D/A HD2 8bit
HD2
Digtal Vss 81 BVSS-81
AVDD-29 29 VDD VD2 Main Timing A/D A/D A/D
VD2 PLL Vss 80 PLLDVSS2
Pulse Gene H/V Sep
REFO 30 D/A A/D 8bit Vss 79 PLLAVSS2
Ped.Clamp(63.5LSB) 1/ 2 D/A
BIAS2-31 31 REFO 1 / 3050 R G B AGS 78 AGS2
Mute 13. 5 M
H/V Sep 1 / 3048 VCO
AVSS-32 32 Vss 1/ 2 77 FILIN2
27M 54M
10bit 1/ 2 4. 8 M
AVDD-33 33 VDD VDD 76 PLLAVDD2
D/A 1/ 4 PC1,CP1
Red PD1/PD2 1/ 5 9. 6 M Ped.Clamp(8LSB)
ROUT 34 VDD 75 PLLDVDD2
CP1/CP2 Ped.Clamp(8LSB)
Green 1/ 6 8. 0 M
BIAS2-35 35 D/A x 4 Li m 74 CKIN
Analog Analog
GOUT 36 PLL VCO PLL VDD 73 73
D D/A 48M
Blue
VDD Vss VDD VDD AGS1 Vss VDD Vss VDD VDD Vss Vss
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
BIAS2-37
BOUT
VREFO
AVDD-40
AVSS-41
PLLVDDI
PLLAVDDI
FILOUT
FILIN1
AGS1
PLLAVSS1
PLLDVSS1
AVSS-49
AVDD-50
REFL1
RIN1
GIN1
BIN1
AVSS-55
AVDD-56
RIN2
GIN2
BIN2
REFH1
BIASS
AVDD-62
REFL2
BIAS6
CVI1
AVSS-66
CVI2
REFH2
69
BIASC
VREFC
CDAO
*TK15405MI : UC model *XC25BS5118MR

INPUT
GND
VCC
TK15405MI CLKIN VDD Q1

6 5 4
6 5 4
E 75Ω
DRIVER
I/M
CLAMP Counter
1
_
2
Fuse 11bit Pll

Select (XN)
1 2 3
STANDBY
OUTPUT
SAG
F
1 2 3
CE VSS Q0
92 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- Block diagram
SYNC/U
FS128/C
ERR/BS
A
DIRINT
DDIN3
DDIN2
DDIN1
DDIN0
DBL/V
7 6 5
IPORT5-7
VMOD BSMOD DDINSEL UMOD CMOD

DBL
FS128
SYNC
BS
C
ERR
V
DIRPCO
PLL DIR
DIR Clock DIRMCK B

(25MHz)
DIRO Interface
DIRBCK
DIRWCK
DIRSDO SDBCKI0
SDIA SDWCKI0
SDIASEL SDIACKSEL
SURENC SDIA Interface /SDBCKO

KARAOKE
MUTE
CRC
AC3DATA CRC
DTSDATA C
NONPCM
ZEROFLG MainDSP IPORT0-4
(AC-3/ProLogicII/
Microcomputer Interface
XI DTS Decoder)
XO PLL
Control Resistor
CPO /CS
SO
DSP Clock
(30MHz) SDOA Interface
SI
L,R
SCK
SDOA0 LS,RS
SDOA1 C,LFE
SDOA2
SDIB0
SDIB1 OPORT0-7 D
SDIB2
SDIB3
SDIBSEL
MPLOAD
SDIBCKSEL
SDIB Interface
RAMD0-15
CASN
Interface
Memory
RASN
RAMWEN
RAMOEN
RAMA0-17 Coefficient.
Program
SubDSP E
RAM
OVFSEL
OVFB/END
SDOBCKSEL
SDOB Interface
SDWCKI1
SDBCKI1
SDOB3
SDOB2
SDOB1
SDOB0
AVH-P7500DVD/UC 93
5 6 7 8
1 2 3 4
*YSS932-S
OVFB/END
KARAOKE
DTSDATA
AC3DATA
ZEROFLG
NONPCM
RAMA17
RAMA16
RAMA15
RAMA14
RAMA13
RAMA12
SURENC
DIRINT
/LOCK
MUTE
VDD1
VDD2
SCK
CRC
VSS
VSS
/CS
SO
/IC
SI
A
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
TESTXI 1 102 VSS
TESTXO 2 101 RAMA11
VDD2 3 100 RAMA10
XO 4 99 RAMA9
XI 5 98 RAMA3
TESTMS 6 97 RAMA4
TESTXEN 7 96 RAMA2
IPORT0 8 95 RAMA5
IPORT1 9 94 RAMA1
B IPORT2 10 93 RAMA6
IPORT3 11 92 RAMA0
IPORT4 12 91 RAMA7
DDIN0 13 90 RAMA8
DDIN1 14 89 VDD1
DDIN2 15 88 VSS
DDIN3 16 87 RASN
VSS 17 86 RAMOEN
CPO 18 85 RAMWEN
AVDD 19 84 CASN
DIRPCO 20 83 RAMD15
DIRPRO 21 82 RAMD14
AVSS 22 81 RAMD13
C
TESTBRK 23 80 RAMD12
TESTR1 24 79 RAMD11
TESTR2 25 78 RAMD10
VDD1 26 77 RAMD9
SDWCKI0 27 76 RAMD8
SDBCKI0 28 75 VDD1
/SDBCKO 29 74 VSS
SDIA 30 73 RAMD7
SDOA2 31 72 RAMD6
SDOA1 32 71 RAMD5
SDOA0 33 70 RAMD4
SDIB3 34 69 RAMD3
D SDIB2 35 68 RAMD2
SDIB1 36 67 RAMD1
SDIB0 37 66 RAMD0
VSS 38 65 VDD2
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
FS128/C
VSS
VSS
ERR/BS
DIRSDO
SYNC/U
VDD2
VDD1
SDWCKI1
SDOB3
SDOB2
SDOB1
SDOB0
OPORT0
OPORT1
OPORT2
OPORT3
OPORT4
OPORT5
OPORT6
OPORT7
DIRMCK
DIRWCK
SDBCKI1
DBL/V
DIRBCK
PE5365A:UC
*PE5366A model,PE5363A:EW model
E
109
144
1 108
F
36 73
37
72
94 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- Pin Function(PE5365A:UC model,PE5363A:EW model)

Pin No. Pin Name I/O Format Function and operation
1 STEST1 I C Hideaway operation test mode input
2,3 MODEL0,1 I C Model sense(UC model)
4 NC Not used
A
5 PORTGND0 Port GND
6 ROMCS O C ROM chip select output
7 ROMCLK O C ROM clock output
8 ROMDATA I/O C ROM data output
9 ILMPWR O C Key illumination output
10 R_INDPWR O C REAR key illumination output
11 R_IND O C REAR illumination color output
12-19 NC Not used
20 SELPWR O C AV selector power supply control output
21 TUNPWR O C Tuner unit power supply control output
22 PORTVDD0 Port power supply
23 RDT I C RDS data intput(EW model) B
24 /RDS57K I C RDS 57KHz pulse count input(EW model)
25 /RDSLK O C RDS lock signal input(EW model)
26 RECIVE O C RDS recive output(EW model)
27 REMSEL O C Remote control input select for navigation
28 REMCODE O C Remote control pulse output for navigation
29 DALMON O C Current consumption down output
30 SYSPW O C System power output
31 ANTPW O C Auto antenna output
32,33 SELCTL0,1 O C Selector control output
34 DDCCTL O C DD converter control output
C
35 SECID O C LED light output
36 CLKOUT O System clock output
37 GND0 GND
38 CPUREG CPU regulator output
40 /RESET System reset input
41 VPP Vpp
42 TSI I C Test data input
43 TSO O C Test data output
44 TCK I C Test data clock input
45 /LDET I C RDS PLL lock signal input
46 TUNPDI I C Tuner PLL data input D
47 TUNPDO I/O C Tuner PLL data input output
48 TUNPCK I/O C Tuner PLL clock input output
49 /BSRQ I C PBUS request input
50 /BRST O C PBUS reset output
51 /BRXEN I/O C PBUS reception input output
52 MUTERQ O C DSP microcomputer mute output
56 TESTIN I C Test mode input
57 NC O C Not used
58 PRGON I C Programming mode input
59 VPPON O C VPP ON/OFF E
65 BEEP O C PEE output
69 /BSENS I Bup sense input
70,71 XT2,1 Sub clock oscillator connect
72 GND2 GND
73,74 X1,2 Main clock oscillator connect
75 NC I C Not used
76 MTRPWR O C FLAP motor control power supply output
77 MTRSEL O C FLAP motor control output F
78 MTRS O C FLAP motor speed control output
AVH-P7500DVD/UC 95
5 6 7 8
1 2 3 4
Pin No. Pin Name I/O Format Function and operation

79 MTR1 O C FLAP angle motor control signal output
80 MTR2 O C FLAP position motor control signal output
A 81 SENS5 O C Pulse power supply control output
82 /DEG0SW I C Angle 0 sense input
83 /LFTSW I C Lift pulse input
84 SDA I/O N AV selector data output
85 SELMUTE O C AV selector sound mute output
86 SCL O N AV selector clock output
87 ASENBO O C ASENS output
88 IPPW O C IPBUS driver power supply output
89 LFTPUL I C Lift sense input
90 /IERX I C IPBUS data input
91 /IETX O C IPBUS data output
B 92 PORTGND1 Port GND
93 BSCK I/O C PBUS clock input output
94 BSI I C PBUS data input
95 BSO I/O C PBUS data output
96 /ASENS I C Acc sense input
97-99 NC Not used
100 TUNPCE O C Tuner PLL chip enable output
101 /TUNPCE2 O C Tuner PLL chip enable output
103 CONTVDD O C MS3 digital power supply control output
104 CONTVD8 O C MS3 motor power supply output
C 105,106 NC Not used
107 RXMON I C Display microcomputer data input
108 TXMON O C Display microcomputer data output
109 SWVDD O C Display microcomputer power supply output
110 NC Not used
111 RXMS3 I C MS3 data input
112 TXMS3 O C MS3 data output
113 IRQPWR O C MS3 backup power output
114 /XRESET O C MS3 mechanism CPU reset
115 AMUTE I C MS3 mute input
116 CONTB I C MS3 power OFF signal input
D
117 RXNAV I C Navigation data input
118 TXNAV O C Navigation command output
119 /RGBSENS I C RGB navigation sense input
120 NC Not used
121 NAVMUTE O C Navigation mute output
122 AMPMUTE O C Sound mute output
123 REARMUTE O C Rear sound mute output
124 NC Not used
125 /DSENS I C Detach sense input
126 /ISENS I C Illumination sense input
127 TELIN I C TEL mute input
E
129 PBSENS I C Parking brake sense input
130 BGSENS I C Back gear sense input
131 GND1 GND
132-134 NC Not used
135 TUNSL I Tuner signal level input
136 VD8SENS I MS3 VD8 power supply sense input
137 ANGLE I FLAP angle sense input
138-142 NC Not used
143 ADCVDD A/D power supply
144 ADCGND A/D GND
F
Format Meaning
C C MOS
N N channel open drain
96 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
TA1290FN : UC model
A
(NOISE INVERTER : OFF)

(NOISE INVERTER : ON)
VIDEO OUTPUT
VIDEO OUTPUT
RF AGC DELAY
AFT OUTPUT
VIDEO COIL
PIF INPUT
RF AGC
GND
16 15 14 13 12 11 10 9
DC
AMPLIFIER B
NOISE
INVERTER PRE- RF AGC
AMPLIFIER
AGC
DETECTION VIDEO
DETECTION
3rd IF 2nd IF 1st IF
LIMITER
AMPLIFIER
C
AFT
IF AGC
DETECTION
1 2 3 4 5 6 7 8
VIDEO COIL
AFT COIL
N.C.
VCC
2nd AGC FILTER
1st AGC FILTER
N.C.
PIF INPUT
- Front End(FE2201:CWB1093) : UC model
E
OSCILLATOR,
MIXER
PLL
32V
6V
5V
9V
1 2 3 4 5 6 7 8 9 10 11
ANT
AGC
TU1
TU2
NC
PB
MB
IF OUT
SDA
SCL
NC
AVH-P7500DVD/UC 97
5 6 7 8
1 2 3 4
- UC model
A - FM/AM Tuner Unit

7 6 13 5 10 9 8 11 14 18 19 20 21
WC
CE2
ROM_VDD
SL
DI
CK
CE1
DO
NC
NC
NC
NC
NC
IC 3 EEPROM IC 5
←
5.0V 5V 3.3V
OSC LPF
AM ANT FMRF
1 ATT
Rch
24
B IC 2
IC 1 2.5V
FM ANT
3 3.3V
ATT Lch
23
FMRF MIXER, IF AMP DET, FM MPX
RF adj
ANT adj
T51 CF52
CF51
AUDIOGND
IC 4
OSCGND
VDD_3.3
←
RFGND
3.3V 3.3V 2.5V 2.5V

DGND
VCC
NC
C 2 12 15 22 16 4 17
No. Symbol I/O Explain

1 AMANT I AM antenna input AM antenna input high impedance AMANT pin is connected with
an all antenna by way of 4.7µH. (LAU type inductor) A series circuit
including an inductor and a resistor is connected with RF ground for
the countermeasure against the ham of power transmission line.
2 RFGND RF ground Ground of antenna block
3 FMANT I FM antenna input Input of FM antenna 75Ω Surge absorber(DSP-201M-S00B) is necessary.
4 VCC power supply The power supply for analog block. D.C 8.4V ± 0.3V
5 SL O signal level Output of FM/AM signals level
6 CE2 I chip enable-2 Chip enable for EEPROM ”Low” active
D
7 WC I write control You can write EEPROM, when EEPROM write control is “ Low” .
Ordinary non connection
8 CE1 I chip enable-1 Chip enable for AF•RF ” High” active
9 CK I clock Clock
10 DI I data in Data input
11 NC non connection Not used
12 OSCGND osc ground Ground of oscillator block
13 ROM_VDD power supply Power supply for EEPROM pin 13 is connected with a power supply of
micro computer.
14 DO O data out Data output
15 DGND digital ground Ground of digital block
E 16 NC non connection Not used
17 VDD_3.3 power supply The power supply for digital block. 3.3V ± 0.2V
22 AUDIOGND audio ground Ground of audio block
23 L ch O L channel output FM stereo “ L-ch” signal output or AM audio output
24 R ch O R channel output FM stereo “ R-ch” signal output or AM audio output
98 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
- EW model
A
- FM/AM Tuner Unit
7 6 13 5 10 9 8 11 14 18 19 20 21
WC
CE2
ROM_VDD
SL
DI
CK
CE1
LDET
DO
RDS_CK
RDS_DATA
RDS_LOCK
RDS_HSLK
IC 3 EEPROM IC 5
←
5.0V 5V 3.3V
OSC LPF
AM ANT FMRF
1 ATT B
Rch
24
IC 2
IC 1 2.5V
FM ANT
3 3.3V
ATT Lch
23
FMRF MIXER, IF AMP DET, FM MPX,
RDS DECODER
RF adj
ANT adj
T51 CF52
CF51
AUDIOGND
IC 4
OSCGND
VDD_3.3
←
C
RFGND
3.3V 3.3V 2.5V 2.5V

DGND
VCC
NC
2 12 15 22 16 4 17
No. Symbol I/O Explain

1 AMANT I AM antenna input AM antenna input high impedance AMANT pin is connected with
an all antenna by way of 4.7µH. (LAU type inductor) A series circuit
including an inductor and a resistor is connected with RF ground for
the countermeasure against the ham of power transmission line.
2 RFGND RF ground Ground of antenna block
3 FMANT I FM antenna input Input of FM antenna 75Ω Surge absorber(DSP-201M-S00B) is necessary.
4 VCC power supply The power supply for analog block. D.C 8.4V ± 0.3V
5 SL O signal level Output of FM/AM signals level D
6 CE2 I chip enable-2 Chip enable for EEPROM ” Low” active
7 WC I write control You can write EEPROM, when EEPROM write control is “ Low” .
Ordinary non connection
8 CE1 I chip enable-1 Chip enable for AF•RF ” High” active
9 CK I clock Clock
10 DI I data in Data input
11 LDET O lock detector “ Low” active
12 OSCGND osc ground Ground of oscillator block
13 ROM_VDD power supply Power supply for EEPROM pin 13 is connected with a power supply of
micro computer.
14 DO O data out Data output E
15 DGND digital ground Ground of digital block
17 VDD_3.3 power supply The power supply for digital block. 3.3V ± 0.2V
18 RDS_CK O RDS clock Output of RDS clock(2.5V)
19 RDS_DATA O RDS data Output of RDS data(2.5V)
20 RDS_LOCK O RDS lock Output unit “ High” active(2.5V) (RDS_LOCK turns over by the
external transistor. “ Low” active)
21 RDS_HSLK O RDS high speed Output unit “ High” active(2.5V)(RDS_HSLK turns over by the
lock external transistor. “ Low” active)
22 AUDIOGND audio ground Ground of audio block
23 L ch O L channel output FM stereo “ L-ch” signal output or AM audio output
24 R ch O R channel output FM stereo “ R-ch” signal output or AM audio output F
AVH-P7500DVD/UC 99
5 6 7 8
4 3 2 1
AVH-P7500DVD/UC 100
F
COMMON
SEGMENT
NC
COM1 COM1
COM2 COM2
COM3 COM3
COM4 COM4
SEG1
SEG2
SEG3
SEG4 E
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18 D
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33 C
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
NC
B
A
- LCD (CAW1805)
7.2.2 DISPLAY
4 3 2 1
5 6 7 8
7.3 OPERATIONAL FLOW CHART A
RESET
VDD0=5V
Pin 39
bsens
Pin 69
bsens=L
asens
Pin 96
asens=L
C
dsens
Pin 125
dsens=L
ASENBO←H
Standby
Pin 87
SWVDD←H
Pin 109
D
Starts
Communication
with Display microcomputer
Source keys operartive

↓
Source ON
SYSPW←H
Pin 30
Completes power-on operation.

(After that, proceed to each source operation)
AVH-P7500DVD/UC 101
5 6 7 8
1 2 3 4
A 7.4 CLEANING
Before shipping out the product, be sure to clean the following portions by using the prescribed cleaning tools:
Portions to be cleaned Cleaning tools
DVD pickup lenses Cleaning liquid : GEM1004
Cleaning paper : GED-008
Portions to be cleaned Cleaning tools

Fans Cleaning paper : GED-008
B
102 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
8. OPERATIONS A
AVH-P7500DVD/UC 103
5 6 7 8
1 2 3 4
104 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
AVH-P7500DVD/UC 105
5 6 7 8
1 2 3 4
106 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
AVH-P7500DVD/UC 107
5 6 7 8
1 2 3 4
108 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
AVH-P7500DVD/UC 109
5 6 7 8
1 2 3 4
110 AVH-P7500DVD/UC
1 2 3 4
5 6 7 8
AVH-P7500DVD/UC 111
5 6 7 8
F
E
B
A
D
C
112
1
1
Yellow 40 cm 15 cm
(1 ft. 4 in.) (5-7/8 in.)
26 pin cable
Black Hide-away unit
Navigation unit
(e.g. AVIC-80DVD)
(sold separately) Violet
This product
30 pin cable (supplied)
IP-BUS cable 3m
2
2
3m (9 ft. 10 in.)
Blue (9 ft. 10 in.)
Antenna cable (supplied)

IP-BUS input Fuse holder
Violet
(Blue)
3m Yellow
(9 ft. 10 in.) To terminal always supplied
with power regardless of
Hide-away unit ignition switch position.
(supplied)
AVH-P7500DVD/UC
Antenna jack
3
3
10 cm 21 pin cable (supplied) Black (ground)

(3-7/8 in.) Black To vehicle (metal) body.
Auto-EQ&TA mic jack.
15 cm
AV-BUS input (Blue) (5-7/8 in.)
Not used. Black ≠
Center speaker
Black/white +
Multi-CD player
(sold separately)
4
4
See the section “When connecting
Violet/white with a back-up camera”.
5
5
Blue
When the source is selected the tuner, a control signal is
output.
This product
To Auto-antenna relay control terminal.
If the car features a glass antenna, connect to the antenna
booster power supply terminal (max. 300 mA 12 V DC).
Yellow/black Connection method

If you use a cellular telephone, connect it via the
Audio Mute lead on the cellular telephone. If not, 1. Clamp the lead. 2. Clamp firmly with
keep the Audio Mute lead free of any connections. needle-nosed
pliers.
6
6
Note:
Red • The position of the parking brake switch depends
Fuse resistor on the vehicle model. For details, consult the
To electric terminal controlled
by ignition switch (12 V DC) vehicle Owner’s Manual or dealer.
ON/OFF.
Light green
Used to detect the ON/OFF status of the parking brake.
Orange/white Fuse resistor This lead must be connected to the power supply side of the parking
To lighting switch terminal.
brake switch.
AVH-P7500DVD/UC
Yellow Fuse holder
To terminal always supplied
with power regardless of Power supply side Parking brake
7
7
ignition switch position. switch

Ground side
Black (ground)
To vehicle (metal) body.
Blue/white
When the source is switched ON, a control
Gray signal is output.
White
+ + To system control terminal of the power amp
Front speaker Front speaker (max. 300 mA 12 V DC).
≠ ≠
White/black Gray/black
Left Right
Green Violet
+ + With a 2 speaker system, do not connect anything
8
Rear speaker
8
Rear speaker
≠ ≠ to the speaker leads that are not connected to speakers.
Green/black Violet/black
113
F
E
B
A
D
C

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Service

For details, refer to "Important symbols for good services".

PIONEER CORPORATION 4-1, Meguro 1-Chome, Meguro-ku, Tokyo 153-8654, Japan

C PIONEER CORPORATION 2003 K-ZZU. JUNE 2003 Printed in Japan

A [ Important symbols for good services ]

4. Shipping mode and shipping screws

5. Lubricants, glues, and replacement parts

- DVD Player Service Precautions

DVD Mechanism Module(MS3)

After connecting a tuner selector unit , please perform adjustment.

Function Name Jig No.

6.2 DVD ADJUSTMENT A

If the reference voltage is connected to GND by mis-

A - Front-End test mode flow chart

Start test mode

AS normalization adjustment feature

Layer0:10** **** Layer0:10** ****

F-close and F-search cannot be executed, unless LD-ON is set.

Method for designating an ID address:

Error code of read error(Part of XX)

Error Code Contents Display

Measurement device and tools : Oscilloscope

Disk used : GGV1018

Skew adjustment connection diagram

Skew adj. screw Skew adj. screw

- Back end section check flow chart

Check 1: Are all power supply voltages normal? A

NO. Verification location Rated value Unit

GND Rated value 2

Clock rated values

System Computer I/F

Streaming I/F rated value

System Computer I/F E

Check 4: Is the audio circuit operating normally?

NO. Verification Verification Rated Rated Reference

2 SRCK IC1605 1pin 2.0V 0.8V Waveform 3

3 LRCK IC1605 3pin 2.0V 0.8V Waveform 3

GND Rated value 2

Checks are conducted with the measurement circuit below.

NO. Verification Verification Rated value Reference

Analog audio outputs (LO and RO) rated values

22kΩ These resistors are inserted.

LO and RO output measurement circuit

System Computer I/F

A Check 5: Is the video circuit operated normally?

NO. Verification location Rated value Reference

COMPO signal Rated When the result is not satisfactory,

Composite signal 100% output waveform

System Computer I/F

A Check 6: Is SDRAM I/F operating normally?

NO. Signal name Verification location 1 Verification location 2 Rated value

A Check 7: Is the microprocessor operating normally?

NO. Signal name Verification Verification Verification Rated value Others

! CH1: STD1 % CH1: AVRTM % CH1: AVRTM

Wave 1 Wave 2(1) Wave 2(2)

* CH1: AOUT0 ¤ CH1: LO › CH1: COMPO 200mV/div. 10µs/div.

Wave 3 Wave 4 Wave 5

6.3 MAIN VIDEO LEVEL ADJUSTMENT

Mother PCB (Side B)

Input test pin :

(1) The Video level (Vlevel) is out of spec.

6.4 MONITOR PCB ADJUSTMENT A

Layer0:10 Layer0:10 ****