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Published in IET Power Electronics
Received on 29th June 2012
Revised on 18th October 2012
Accepted on 1st November 2012
doi: 10.1049/iet-pel.2012.0318

ISSN 1755-4535

Performance evaluation of a simple and general space

vector pulse-width modulation-based M-level inverter
including over-modulation operation
Kartick Chandra Jana1, Sujit K. Biswas2, Suparna Kar Chowdhury2
1
Department of Electrical Engineering, Indian School of Mines, Dhanbad 826004, Jharkhand, India
2
Department of Electrical Engineering, Jadavpur University, Kolkata 700032, India
E-mail: kartick_jana@yahoo.com

Abstract: This study presents a simple and a generalised space vector pulse-width modulation scheme for a neutral point clamped
multi-level inverter as well as cascaded inverter of any level. This modulation algorithm implements the online generation of
desired switching states and their sequences through generalised expressions without any predetermined stored data in a
memory look-up table. The proposed algorithm also incorporates the concept of reference vector and on-time modification
combined during the over-modulation region for any level of inverter. Performance of the proposed modulation algorithm is
tested experimentally through a digital signal processor-based controller for a five-level cascaded inverter with very low
execution time that does not depend much on the level of inverter. The simulation waveform and the harmonic analysis of the
voltage at different modulation index are presented and these are verified with the experimental results.

1 Introduction techniques have been implemented for multi-level inverter

Recently, multi-level inverter finds tremendous applications
[1, 2] in standard drives for medium-voltage industrial
motor control [3] in chemical industry, oil industry and
traction system [4]. Multi-level inverter also finds
application in power quality improvement, including static
compensator [5], renewable energy sources [6] etc. Among
the popular multi-level topologies, cascaded multi-level
inverter achieves the highest voltage with the help of
smaller voltage sources.
Numerous modulation techniques have been studied for
three-level inverter and can be extended to multi-level
inverter [7–23], based on carrier-level shifting [7] and phase
shifting [8] methods. Selective harmonic elimination
pulse-width modulation (SHE-PWM) [9] and space vector
PWM (SVPWM) techniques [10–22] are the other popular
PWM techniques. SHE method is the fundamental
frequency modulation technique where offline calculation is
necessary [9], making dynamic operation and closed-loop
control difficult. Among these PWM techniques, SVPWM
is the most promising PWM techniques with great
flexibility in switching sequence design for capacitor
voltage balancing using two-dimensional (2D) [10, 11] and
3D coordinating systems [12, 13]. The large number of
output voltage levels in a high-level inverter is a real
constraint for implementing complex control hardware
system using several triangular carriers (in carrier-based
techniques) and a high computational burden (in SVPWM
techniques) because of large number of voltage space
vector including redundant states. Several SVPWM
which mainly stressed on their generalisation for
implementing in any level of inverter and extension of
modulation region.
Most of the earlier researchers have considered the
complex Cartesian coordinate system [14], which results in
complicated expressions and becomes difficult to
implement for higher level of inverter. Further, the
modulation technique for over-modulation mode is either
excluded or it may be computed offline. Some researchers
reported [15] that the switching states as well as the
switching times for multi-level inverter are calculated
offline and stored in a look-up table. Moreover, the
expressions of dwell time for various triangles are also
different, therefore difficult to extend to higher than
three-level inverter. The scheme in [16] has proposed a
SVPWM-based algorithm based on 3D Euclidean vector,
where the dwell time calculation is very complex because
of the use of this Euclidean space vector. Gupta and
Khambadkone [17] proposed a general approach for
calculation of on-time for any space vector including
over-modulation region, but the switching states and their
sequences are stored in look-up tables. Wei et al. [18]
proposed a general scheme for a multi-level inverter for
linear modulation region only.
Recently, a generalised method for multi-level inverter
using principle of mapping and reverse mapping for
calculation of switching vector was proposed [19]. This
involves lengthy calculations and is difficult to implement
for higher level of inverter. In [20], a space vector-based
hybrid technique has been developed for minimising current

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ripples using different switching sequences. A significantly
different approach for the generation of different switching
states and sequence using online technique was presented in
[21] where all the switching states and their sequences have
been calculated for a cascaded multi-level inverter in linear
modulation regions only.
This paper presents a modified version of [21], for a general
M-level inverter of cascaded or neutral clamped converter
(NPC) configuration and also provides a general solution
for over-modulation mode. A three-phase structure of a
generalised cascaded inverter can be obtained by using a
number of H-bridge inverters called cells in each phase of
the circuit as shown in Fig. 1. Separate identical dc sources
are connected to individual H-bridge cell. The output
voltage corresponding to switching states of the cascaded
inverter are similar to [23].
The proposed SVPWM is based on the 60° coordinate
system and the space vectors are represented in integer
scale [22] rather than complex Cartesian coordinates system
[14]. Moreover, the entire computational work is carried out
online and does not require any additional memory storage
devices. The salient features of the proposed algorithm are
given below.
† As reference space vector (Vr) are decomposed in m–n axis
in integer scale, which makes an angle of π/3, it is easy to find
out coordinates in simple integer form for any reference space
vectors (vertex) of the triangle where Vr lies. There is no need
to calculate switching states and their switching sequence
offline and to store them in lookup table, as they are
generated online.
† It is not required to calculate all the switching states and
sequence for each triangle for a reference voltage of a
multi-level inverter, as only the space vector (m, n) is
sufficient to obtain the desired switching state, their
dwelling time as well as the proper switching sequences.
Therefore it has lower execution time, faster processing
speed and moreover, the execution time does not depend
much on the level of inverter.
† The modulation algorithm is very simple and generalised,
which can be applied to cascaded as well as neutral point
clamped inverter of any level without any change in the
modulation algorithm.
† The proposed algorithm is extended to over-modulation
region without modifying the equations or without using
any look-up tables. There are a large number of
Fig. 1 General structure of a cascaded multi-level inverter with
equal DC voltage
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redundancies existing in a cascaded multi-level inverter that
can be utilised for minimisation of harmonics, reduction of
switching frequency and balanced ac voltage generation by
each H-bridge cell.
An integer coordinate system namely m–n coordinates,
which is at 60° to each other, can be established for a
three-level inverter, is illustrated in Fig. 2, showing the
operation in first sector only.
1.1 Decomposition of reference voltage in linear
modulation region (0 ≤ Mi ≤ 0.907)
In this mode, the reference vector with magnitude Vr moves
on a circular trajectory as shown in Fig. 2. Since the
trajectory is within the hexagon, the modulation index can
be controlled linearly.
The decomposition vector (Vrm, Vrn) of the reference
voltage into m–n axis, for a M-level inverter can be
determined as
⎫
2(M − 1)Vr ⎪
Vrn = √

sin a ⎪
⎬
3Vdc
2(M − 1)Vr p  ⎪
(1)
Vrm = √

sin − a ⎪ ⎭
3Vdc 3
The modulation index (Mi) can be controlled by controlling
the magnitude of reference voltage Vr. The ideal
relationship between modulation index, Mi and Vr is
considered here as
Mi = 0.907Vr /0.866Vdc (2)
1.2 Determination of coordinates of reference
voltage and their dwelling time
The generalised coordinate (m, n) of the reference vector is
the lower rounded integer value of decomposition vector
(Vrm, Vrn) of reference voltage (Vr) along an axis which
makes 60° to each other termed as m–n axis, as shown in
Fig. 2. Based on the coordinates (m, n), the coordinates of
the three apex of the triangle (m1, n1), (m2, n2) and (m3, n3)
are calculated as per the logic given in Table 1 to obtain the
dwelling time of each voltage vector.
The dwelling time [T1, T2, T3] corresponding to three
nearest voltage vector of Vr as shown in Fig. 2 with
coordinates (m1, n1), (m2, n2) and (m3, n3) can be
Fig. 2 Coordinates of three nearest voltage vectors of reference Vr
in sector-I of three-level inverter
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Table 1 Determination of coordinates for corresponding space compensate for the total loss in volt–seconds as shown by
vectors where Vr lies two hatched area in each sector.
(Vrm + Vrn) > (m + n + 1) (Vrm + Vrn) ≤ (m + n + 1)
1.3.1 Hexagonal track region: The condition where the
upper triangle (EFG) in given lower triangle (DEF) in given reference vector crosses the hexagonal track can be
rectangle rectangle determined as follows:
m1 = (m + 1), n1 = (n + 1) m1 = m, n1 = n If (Vrm + Vrn) ≥ M−1, Vr crosses the hexagon and therefore
m2 = (m + 1), n2 = n m2 = (m + 1), n2 = n must be reduced to follow the hexagonal track PQ, as depicted
m3 = m, n3 = (n + 1) m3 = m, n3 = (n + 1)
in Fig. 3. This can be implemented through multiplication of
the decomposition vector Vrm and Vrn by a voltage reduction
factor λr = (M−1)(Vrm +′ Vrn)′
to obtain the modified
decomposition vector Vrm , Vrn as follows
determined from the voltage time balance equation given as ′

Vrm = lr Vrm
(4)
⎫ Vrn′ = lr Vrn
n1 T1 + n2 T2 + n3 T3 = Tpwm Vrn ⎬
m1 T1 + m2 T2 + m3 T3 = Tpwm Vrm (3)
T1 + T2 + T3 = Tpwm ⎭
Therefore for a given modulation index Mi in
over-modulation mode I with hexagonal track, the reference
vector must be modified (reduced) and the corresponding
loss in volt–seconds can be compensated in the circular
The values of dwell time [T1, T2, T3] are valid for linear
track region explained in the following section.
modulation region only, where the modulation index Mi is
< 0.907. Therefore to apply the above SVPWM algorithm 1.3.2 Circular track region: For the reference voltage
with higher Mi, the reference voltage must be modified as with magnitude Vr located in such a way, that (Vrm + Vrn) <
discussed in the following sections. M−1, then the reference voltage can be modified based on
the modification of on-time [17] to balance the loss in volt–
seconds during the hexagonal track region PQ in Fig. 3,
1.3 Over-modulation mode I (0.907 ≤ Mi ≤ 0.953)
which is equal to the gain in volt–seconds during circular
This over-modulation mode is determined by the inequality as
and QR and corresponding modified on-times
(Vrm + Vrn) > M−1 (for a M-level inverter) and is indicated by
a non-linear curve, which is determined by the approximation
techniques explained in this section. The thick dotted circle is
the actual trajectory of reference voltage Vr, whereas the thick
continuous line shows the modified trajectory of the reference
vector.
Traditionally, for Mi, the circular trajectory of the reference
vector is only modified if it crosses the hexagonal region. The
modified trajectory of reference vector moves along OPQR
shown in the thick solid line in Fig. 3. Thus, it first moves
along a circular track OP with increased radius and then
follows a linear hexagonal track PQ with reduced
magnitude and finally along the circular tracks QR in each
sector. This modification of trajectory is intended to
Fig. 3 Modified references voltage and its projection on m–n axis
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track OP
T1′ , T2′ , T3′ of each reference can be obtained.
The maximum compensation of on-time is reached at the
modulation index of 0.953, which corresponds to complete
movement of the reference along the hexagonal track.
Therefore to increase the modulation index further, the
following modifications are needed as discussed in the
following section.
1.4 Over-modulation mode II (0.935 ≤ Mi ≤ 1.0)
1.4.1 Hexagonal track region [αh < α < (π/3–αh)]:
Switching in over-modulation mode II is characterised by a
hold angle αh, shown by two thick dotted arrows as
depicted in Fig. 4. For an over-modulation mode II, if the
operating angle α > αh and α < (π/3 – αh), the tip of the
reference vector crosses the hexagon (where Vrm + Vrn > M−1)
Fig. 4 Modified reference voltage in over-modulation mode II
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Table 2 Switching states [Sa, Sb, Sc] in various sectors
Sector I Sector II Sector III Sector IV Sector V Sector VI
Sa −Sb Sc −Sa Sb −Sc
Sb −Sc Sa −Sb Sc −Sa
Sc −Sa Sb −Sc Sa −Sb
and the reference must be modified similar to mode I
hexagonal track region as already discussed. The thick line
along hexagonal track is the modified reference Vr′ and the
corresponding loss in volt–seconds is indicated by the
hatched area in Fig. 4. To increase the fundamental output
voltage linearly, this loss in volt–seconds can be
compensated by operating it under six-step mode of
operation, where the angle of reference is beyond this value
as discussed in the following sections.
1.4.2 Six-step modes [α < αh and α > (π/3–αh)]: For the
region where α < αh and α > (π/3–αh), to compensate the loss
in volt–seconds in hexagonal track, the reference voltage must
be held at the large voltage vectors at points A and B for the
time duration equal to time required by the reference vector to
traverse the hold angle αh for a given modulation index Mi.
Normally, αh is a non-linear function of modulation index
and obtained by look-up tables. In this work, this angle can be
obtained using a strategy similar to Gupta and Khambadkone
[17] which is suitable for ac drives, where constant flux is
maintained and the angular velocity is proportional to
modulation index (Mi).
Therefore for a particular value of Mi in the range of
(0.935 ≤ Mi ≤ 1.0) the reference vector has a specific hold
angle and the reference must be modified to compensate the
loss of volt–seconds. At Mi = 1.0, the hexagonal track
completely vanishes and reference vector is held only at the
six large vectors sequentially over a complete rotation. This
is a six-step operation similar to two-level inverter, where
maximum dc utilisation is achieved.
2 Proposed generalised SVPWM techniques
for multi-level inverter
2.1 General relationship between space vector and
switching states
In a multi-level inverter, a voltage space vector of coordinates
say (m, n) can be represented by more than one switching
state. Therefore it is desirable to find a general expression
which describes the relationship between the voltage space
vectors with coordinates (m, n) and their corresponding
switching states (Sa, Sb, Sc) for any level of inverter. Space
vectors in the 60° coordinate system, shown in Fig. 5, can
be generally expressed by (m, n), where m = 1, 2, …, 2p,
Table 3 Desired switching states for M-level inverter
Type-I space vector Type-II space vector
If (m + n) is even If m is odd but n is even integer
Desired switching states for a reference space vector with coordinate (m, n)
Sam = (m + n)/2 Sal = (m + n + 1)/2
Sbm = (n − m)/2 Sbl = (n − m + 1)/2
Scm = −(m + n)/2 Scl = −(m + n − 1)/2
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and n = 1, 2, … ,2p, where p = (M − 1)/2 is an integer
number, as M is the number of phase voltage levels of the
inverter, which is always an odd number for the cascaded
H-bridge inverter. The general relationship between a space
vector (m, n) and its possible switching states for three
phases [Sa, Sb, Sc] are obtained using (5) for all space
vectors of a multi-level inverter in sector-I [18] and can be
expressed as
⎫
Sa = (m + n − p), (m + n − p + 1), . . . , p ⎬
Sb = (n − p), (n − p + 1), . . . , (p − m) (5)
⎭
Sc = (−p), (−p + 1), . . . , (p − m − n)
In a three-level inverter, the space vector (0, 0) has three
redundant switching states as [0 0 0], [ −1 –1 −1] and [1 1
1] as determined by (5). The switching states for other
sectors can be arranged as per the Table 2.
2.2 Selection of proper switching states
In a multi-level inverter, the number of redundant switching
states is increased drastically with the voltage level as
calculated by (5). In a diode clamped, flying capacitor and
cascaded multi-level inverter with capacitor-based floating
dc sources for reactive power exchange, the capacitor
voltage unbalancing problems can be minimised with the
help of redundant switching states. In this case, as the
cascaded inverter is powered by isolated dc sources, it is
not necessary to calculate all the switching states, instead it
is formulated by a general expression for the desired
switching states, which results in lower switching frequency
and harmonics based on the space vectors (m, n)
corresponding to reference voltage (Vr) as summarised in
Table 3.
2.3 Switching sequence design
In cascaded multi-level inverters, there are no capacitor
unbalancing problems in the input of each H-bridge cell,
where dc voltage is obtained from transformer rectification.
Therefore the switching sequence is utilised for minimum
number of switching per switching period as there is only
one voltage level change per commutations of switching
devices and lower output voltage’s total weighted harmonic
distortion (WTHD).
To analyse the switching sequence in detail, it is assumed
that the reference voltage (Vr) lies in a triangle GEF with
coordinates of the vertex as (m1, n1), (m2, n2) and (m3, n3)
as shown in Fig. 5. Based on the value of coordinate (m1,
n1), a unique and generalised switching sequence is
determined for a reference Vr as follows:
Type-III space vector
If m is even but n is odd integer
Sas = (m + n − 1)/2
Sbs = (n − m − 1)/2
Scs = −(m + n + 1)/2
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Fig. 5 Switching sequence in terms of voltage vectors where
reference voltage Vr lies
Fig. 6 Simulation result for a five-level inverter (line voltages at Mi = 0.905 at fo = 45.3 Hz with VDC(HB) = 100 V)
Fig. 7 Simulation result of Vab for a 15-level inverter at Mi = 0.905 at Fo = 45.25 Hz with VDC(HB) = 30 V
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Case I: If the reference space vector (Vr) with coordinate (m,
n) or (m1, n1) is a type-I space vector as specified by the
triangle FGE in Fig. 5, the switching sequence
corresponding to that reference Vr can be followed by a
generalised sequence of (m3, n3) → (m1, n1) → (m2, n2) →
(m1, n1) → (m3, n3).
Case II: If the corresponding space vector with coordinate (m,
n) or (m1, n1) is in type-II as in triangle PRQ in Fig. 5, the
switching sequence can be of (m1, n1) → (m3, n3) → (m2,
n2) → (m3, n3) → (m1, n1).
Case III: Otherwise (for the type-III space vector), where Vr
lies within the triangle STU in Fig. 5, the switching sequence
can be arranged as (m1, n1) → (m2, n2) → (m3, n3) → (m2,
n2) → (m1, n1).
Therefore it is very easy to generate the switching patterns
(or sequence) of any reference voltage Vr for any level of
inverter based on (m1, n1) or (m, n) of reference vector.
This generalised expression for proper switching states and
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switching sequences makes the operation online. The
flowchart for the implementation of above algorithm for any
level of inverter is given in Appendix 1.
3 Simulations results for a M-level inverter
The simulation results of line voltage Vab and its harmonic
spectra have been presented for the performance evaluation
of a cascaded five-level inverter by the proposed general
SVPWM algorithm at the modulation index of 0.905 and
the result is shown in Fig. 6. From this, it is observed that
the %THD in line voltage Vab becomes very less, being
∼5.74%, where all the harmonic components are very small
( < 1%) except harmonic components around the switching
frequency, as depicted in Fig. 6.
To further test the performance of the proposed algorithm,
for a general M-level inverter the proposed SVPWM
algorithm has been extended to a 15-level cascaded inverter
without any modification in the control algorithm. Fig. 7
shows the simulation results of line voltage and its
harmonic spectra, which illustrates that line voltage has
Fig. 8 Simulation result of IABC for a 15-level inverter-based IM at different Mi during transient condition
Table 4 Time required to generate sampled data corresponding to a switching state for a simulation time of 1.0 s interval at a fixed
step size of Ts = 20 µs
Conventional SVPWM Proposed SVPWM for cascaded multi-level inverters
Three-level NPC inverter Three-level
8.23 s 6.45 s
Fig. 9
a Five-level cascaded inverter
b Complete experimental setup
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negligible individual harmonic components ( < 0.5%).
Three-phase stator currents IABC during transient condition
at different modulation index (Mi) is also presented here, as
shown in Fig. 8.
Calculation is also made for the execution time for
generating switching sequences of different multi-level
inverters using proposed algorithm as well as conventional
SVPWM techniques for the completion of 1 s simulation to
study the performance evaluation and the results are shown
in Table 4. From these results, it is observed that the
proposed generalised SVPWM technique requires lesser
time and moreover the execution time does not increase
with the level of inverter.
4 Experimental results for five-level
cascaded inverter
To test the overall performance of the system, a 5 kW
experimental prototype for a five-level cascaded inverter
was assembled, as shown in Fig. 9. A three-phase induction
SPWM
Five-level Fifteen-level Fifteen-level
6.52 s 6.64 s 9.17 s
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Fig. 10 Experimental results

a Line voltage Vab
b Its harmonic spectra at modulation index Mi = 0.906 at output frequency of 45.3 Hz

motor (IM) of rating 1.1 kW, 220 V and 50 Hz was coupled The dc-link voltage across each H-bridge inverter was
with DC generator and arranged with the electrical load box selected as Vdc(HB) = 60 V, as obtained from multi-winding
for performance verification under different load conditions. transformer and rectifier arrangements. The IM was

Fig. 11 Experimental results

a Line voltage Vab
b Its harmonic spectra during over-modulation at modulation index Mi = 0.982 and output frequency of 49.1 Hz

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operated at different fundamental frequency in constant flux
mode. The proposed SVPWM technique has been
implemented at a very high sampling frequency of 20 kHz
and a switching frequency of 2.5 kHz.
The proposed algorithm was implemented on this
experimental set-up using a DS1104-based digital
controller, because of its availability in laboratory. Owing
to its simplicity and generalisation, the algorithm can also
be implemented in fixed point processor as well. The
experimental results for the cascaded five-level inverter is
presented and verified with their simulation results.
Figs. 10 and 11 show the experimental results for output
voltages, currents and their WTHD for different
fundamental output frequency ( fo) at modulation index (Mi)
of 0.906 and 0.98 corresponding to linear, over-modulation
mode II, respectively. From the harmonic spectra of
Fig. 10b, it is observed that the individual harmonic
components are < 3% and overall %THD and %WTHD are
5.5% and 0.47%, respectively. Fig. 11 shows the output
voltage waveform and its harmonic spectra at very high
modulation index Mi = 0.982. The stator current waveform
of the induction machine has some ripples as the output
voltage waveform is modulated at low switching frequency.
The corresponding %THD and %WTHD are increased due
to the operation at higher modulation index of Mi = 0.98
where switching frequency becomes nearly fundamental
frequency.
5 Conclusions
In most of the conventional SVPWM techniques, the
complexity of control algorithm and execution time
increases with the level of inverter. Hence, to minimise the
drawbacks of conventional SVPWM algorithm, a new
generalised algorithm based on integer coordinates has been
proposed for the generation of SVPWM for M-level
inverters and applied to a cascaded five-level inverters. The
selection of the proper switching states from a large number
of redundant states and their sequences are done by a novel
method. The expressions of switching states and their dwell
time do not change with the triangle or level of inverter and
only depend on the coordinates of the space vector which is
in integer scales and simplifies their calculations. Moreover,
the proposed SVPWM technique can also handle
over-modulation situation by modifying the reference
voltage and on-time combination in such a way that does
not vary the computational burden with the increase of
level. Furthermore, as the calculations are done based on all
generalised expressions online, it does not require a look-up
table. The experimental results are provided at different
frequency and wide modulation range. The simulation
results for a 15-level cascaded inverter are given at Mi =
0.905 without any modification of the proposed modulation
strategy.
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7 Appendix 1: flow chart of the proposed
SVPWM
The flowchart of the proposed algorithm is given in Fig. 12.
IET Power Electron., 2013, Vol. 6, Iss. 4, pp. 809–817
doi: 10.1049/iet-pel.2012.0318
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Fig. 12 Flowchart of the proposed modulation algorithm

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