IET Power Electronics

Research Article

ISSN 1755-4535
Modulation and control of multilevel inverter Received on 10th February 2016
Revised on 7th September 2016
for an open-end winding induction motor Accepted on 19th September 2016
doi: 10.1049/iet-pel.2016.0105
with constant voltage levels and harmonics www.ietdl.org

Bidyut Mahato ✉, Ravi Raushan, Kartick Chandra Jana

Department of Electrical Engineering, Indian School of Mines, Dhanbad, Jharkhand, India
✉ E-mail: bidyut1990@gmail.com

Abstract: A multilevel inverter (MLI) with staircase waveform having maximum number of voltage levels at any desired
voltage (or frequency) of a variable voltage, variable frequency application can play an important role in the modern
power conversion system. In most of the control and modulation techniques of MLI, the number of voltage level
reduces with the reduction of modulation index that increases the harmonic and total harmonic distortions (THDs).
The variable voltage application of MLI using a single DC source of variable magnitude is the elementary concept of
the proposed control technique. A cascaded MLI having unequal voltage sources with controlled magnitude can be
used to increase the number of voltage levels. The closed-loop voltage control technique and a multi-winding
transformer-rectifier based AC-link system is used to obtain the multiple variable voltage DC sources for the cascaded
MLI. A nearest level modulation based control technique has been implemented for the MLI to obtain the fixed level
voltage waveforms with constant THD and reduced switching losses. The whole control algorithm for a nine-level
inverter is simulated and results are experimentally verified on a laboratory prototype of the three-phase induction
motor drives.

1 Introduction
DC-link voltage regulation in a multilevel inverter (MLI) can play a
key role in the modern power conversion system for a variable
voltage, variable frequency application like industrial AC motor
drives, electric traction system, electric and hybrid electric vehicle
(EVs) [1–3] and so on. Various industrial applications have begun
to require high power apparatus in recent years with medium
voltage and megawatt power level [4]. For high power
applications, multilevel converter appears to be appropriate
solution due to the fact that the multilevel converter generates
better quality of output voltages with the increase in the number of
levels using medium power semiconductor switches when
compared with two level converters [5, 6].
Now-a-days, multilevel voltage source inverters have emerged as
a viable solution for high power DC-to-AC conversion applications.
The elementary concept of MLI is to generate a stepped voltage
waveform by using multiple input DC levels and an appropriate
arrangement of power semiconductor based devices. MLI offers
improved quality output waveforms with a lower total harmonic
distortion (THD) and better harmonic spectrum that further leads
to a reduction in filter’s size. These converters have been widely
applied to power conversion, electrical drives, power quality
devices, marine propulsion system, energy transmission and
industries related to oil, chemical and liquefied natural gas [4, 7].
Among the various classic MLI configurations like neutral point
clamped (NPC), flying capacitors (FCs), cascaded H-bridge cells
with separated DC sources and so on. Cascaded H-bridge MLI are
reported with the highest output voltage (31 MVA) levels [7] until
2008. This structure is based on a series connection of several
single-phase inverters and is capable of obtaining medium output
voltage levels using only standard low voltage components.
However, cascading several single-phase modular inverters
(half-bridge) called as modular multilevel converters (MMCs) have
been used for the HVDC application up to 400 MW system and
have been commercialised up to 1 GW system [8, 9] until 2013.
Cascaded multilevel converters have gained popularity [10] due to
the ability to generate voltage waveforms with negligible
distortions and its modular structure [11] as compared with the
other inverter configuration.
The number of voltage levels in cascaded MLI can be further
increased by selecting the appropriate ratio of DC-link voltages
[12, 13]. Thus, more number of output voltage levels can be
generated in comparison with the traditional cascaded multilevel
converters with the same number of components [14], which may
reduce the common mode voltages, the filter requirements and the
output THD. Analysis of an asymmetric modulation method for
H-bridge [15] and asymmetrical MLI topology with reduced
number of switches [16] has been studied thereby reducing the
total cost and installation space of an asymmetric cascaded MLI.
EVs and hybrid EVs (HEVs) are gaining attention due to their
lower greenhouse emissions and higher efficiencies with
development of improved motor technologies [2, 17, 18] using
power electronic devices and cascaded H-bridge has been
successfully commercialised for EVs and HEVs [1, 3]. The use of
an asymmetrical MLI with one DC supply system is especially
suitable for EVs, HEVs and industrial machine drives [19]. In
cascaded MLI, the faulty module can be bypassed without
hampering the load with an appropriate control strategy [20].
Thus, easier and quicker replacement is possible in case of a fault
in one of the modules. In spite of these advantages of the
asymmetrical multilevel converters, there are a few drawbacks of
the above topology are the large number of floating DC sources
[7] and the loss of modularity (with unequal voltages).
In the literature, there are different pulse-width modulation
(PWM) techniques for multilevel converters as the level shifted
carrier PWM [21], phase shifted carrier PWM [22] and generalised
switching scheme for a space vector PWM-based N-level inverter
with reduced switching frequency and harmonics along with the
performance evaluation, including over-modulation operation is
reported in [23], dual reference phase shifted PWM technique for
a N-level inverter based grid connected solar photovoltaic system
is reported in [24] and so on. For high power MLI, several low
frequency modulation techniques like selective harmonic
elimination (SHE) has been reviewed in [25] and the synchronous
optimal PWM (SOPWM) for nine-level cascade inverter [26] are

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Fig. 1 Block diagram of a nine-level asymmetrical MLI power circuit
reported by the researcher. For an asymmetrical MLI, a hybrid
modulation technique has been used that generates the low
frequency pulses for high power inverter switches and of high
frequency pulses of low power switching device [27].
Although, MLIs have numerous advantages stated earlier, one of
the major drawbacks of most of the control and modulation
techniques for any MLI for a variable speed application is the loss
of voltage levels with the decrease in reference voltage or
modulation index (Mi). The decrease in voltage level with the
reference not only hampers the quality of the output voltage
waveform, but also increases the individual harmonic components
and the THD. To solve the above problems, the DC-link voltage
magnitude of the inverter may be adjusted to control the
magnitude of AC voltage.
In [27], a single-DC voltage source and high frequency AC-link
system based asymmetrical MLI is presented for motor drive
system with DC-link voltage control. A single-DC source based
MLI has been used for open-end winding IM using space vector
PWM (SVPWM) technique [28] to eliminate fifth and seventh
harmonics voltage over entire modulation range. In [29], a
27-level asymmetric inverter based on four DC power supply is
used along with independent input transformers and isolated
windings for each phase of the motor.
In this proposed work, an asymmetrical cascaded MLI inverter
with a single DC source is used. Several low voltage DC-link
voltages for the above inverter can be obtained from a single DC
source by using an inverter and multi-winding transformer-rectifier
based AC-link system. A DC-link voltage control algorithm is
proposed for the control of inverter voltage using an input side
DC–DC converter. The modulation of the inverter is done in such
a way that the DC-link voltage can be adjusted to control the
inverter voltage for the variable voltage variable frequency
application. Moreover, the modulation technique should ensure
that, the high power MAIN-inverter will carry 80% of the required
power at fundamental switching frequency, incurred less switching
losses. The nearest level controls (NLC) are widely used
modulation technique for higher power, high level inverter
applications [30–32]. NLCs have advantages over SHE (selective
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harmonic elimination) as it does not require calculating the
triggering angles thereby making calculations simpler. The
determination of all redundant switching states and appropriate
switching sequences are the most difficult tasks for SVPWM
technique rather than that of NLC being analysed and
demonstrated in [33]. In this paper, a novel control strategy using
NLC is proposed to realise a nine-level asymmetrical converter
structure with a single DC supply.
2 Asymmetrical MLI
In this proposed work, a nine-level asymmetrical MLI is considered
for a three-phase induction motor (IM) drive. Two H-bridge inverters
with unequal voltages (3VDC: VDC) are connected in a cascaded
manner to obtain the nine voltage levels per phase. The details of
the circuit of the asymmetrical cascaded nine-level inverter are
discussed in the following section.
2.1 Proposed converter configuration
The proposed MLI can be comprised of different semiconductor
switches as they are carrying different amount of power. In
addition to this, the switching frequency for the MAIN inverter
switches that carrying more power can be kept lower than the
switches of the AUX inverter which carries very low power to
achieve lower switching losses and devices cost. Therefore, the
DC–DC converter, MAIN inverters and the inverter in an AC-link
system that are supported to carry more power can be made of
insulated-gate bipolar transistors (IGBTs), whereas the auxiliary
inverters can be designed with metal–oxide–semiconductor
field-effect transistors (MOSFETs) for low cost and effective
utilisation of their capacity. Similar to the DC–DC converter used
in for a 20 kW plug-in HEV, a low power DC–DC converter is
used to control the DC-link voltages of the inverters for variable
speed application of IM drives [34]. An IGBT switch (TD) may be
employed along with LC filter in the DC–DC buck converter to
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Fig. 2 Propose control technique for the MLI based IM (isolated winding) with a constant voltage level of operation
carry the whole power. The duty cycle of the converter can be
adjusted to obtain the variable DC voltage using a close-loop
voltage controller as per the speed of the motor required.
The voltage of the three MAIN inverters for all three phases are
equal to the DC-link voltage (VDC = 3VDC) and of AUX inverters
is equal to the VDC. The DC-link voltage for all three-phase AUX
inverters can be obtained by using a single-phase bridge inverter
and a multi-winding transformer combination as described as an
AC-link system. Therefore, the buck converter output is fed to the
three MAIN H-bridge inverters directly and to the auxiliary
inverters (AUX) through an AC-link system.
2.2 AC-link system
The AC-link system consist of a single-phase bridge inverter using
IGBT switches, one multi-winding transformer and a low power
bridge rectifier that made of simple fast recovery diodes for each
phase as shown in Fig. 1. The bridge inverter generates a PWM
output at the fundamental frequency and supplied the power to the
auxiliary inverters through a multi-winding transformer. The
fundamental frequency of the bridge inverter and multi-winding
transformer is kept at 50 Hz for the sake of simplification in the
hardware design. However, the frequency of the AC-link system
can be made to a considerably higher value for the reduction in
Fig. 3 Modulation strategy using the NLC
a Block diagram representation of NLC for a N-level asymmetrical inverter
b Reference signal for MAIN and AUX bridge inverters and the corresponding switching states of a nine-level inverter
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size and weight of the components. The multi-winding transformer
is used in the proposed system to feed the power to three AUX
inverters (for three phases) through an individual rectifier and filter
system for a three-phase configuration. The turn’s ratio of the
multi-winding transformer is chosen 3:1 for the trinary
asymmetrical MLI configuration.
3 Proposed modulation and control of MLI for
constant voltage levels
A novel control technique is proposed in this work, to control the
DC-link voltage that keeps the number of voltage levels of any
MLI constant irrespective of the reference voltage or the frequency
of the inverter. The DC-link voltage proportional to the rms
magnitude of the output voltage (or frequency to keep flux
constant) can be controlled using a close-loop voltage controller.
For a variable speed IM drives like traction drives, the
fundamental stator voltage can be controlled indirectly by
controlling the magnitude of DC-link voltages at the converter
stage (output of the DC–DC converter) rather than the inverter
stage in a conventional V/f control techniques However, the
fundamental frequency of the inverter can be controlled by the
suitable modulation at the inverter stage [35–37]. In [35], a
multilevel converter using V/f operation of IM for open-end
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Fig. 4 Simulation and their corresponding experimental results of
a MAIN inverter switching states, S1
b AUX inverter switching states, S2
c Inverter phase voltage at (Vs = 200 V, 3VDC = 189 V, VDC = 63 V)
winding motor drive has been done. The %THD for current reduced
to great extent using modification of pulses but more or less %THD
of voltage is constant. Floating capacitor bank (half the DC-link
voltage) using redundant switching states is used to achieve
multilevel output voltage. Dynamic performance of the system is
also evaluated using a close-loop field oriented controlled motor
drive. The magnitude of DC-link voltage (VDC) proportional to the
rms magnitude of inverter AC output voltage (VLL,rms) (for
constant v/f operation) can be derived as
p error is processed through a proportional and integral (PI) controller.
VDC-T = √

VLL , rms
6
To control the stator voltage (VLL,rms) of the IM for a variable speed
application, an appropriate value of the total DC-link voltage (VDC-T)
per phase is to be generated for the whole inverter to keep the stator
flux constant using (1). For an asymmetrical nine-level inverter, the
two DC-link voltages are used in each phase with the magnitude of
3VDC and VDC, whose sum is equal to the total DC-link voltage
(VDC-T). However, to adjust the total DC-link voltage magnitude
(VDC-T), only one voltage controller is used, that controls the
DC-link voltage of the MAIN inverter (VDC=3VDC) through a
common DC–DC converter. However, the DC-link voltages of the
auxiliary inverters (VDC = VDC/3) can be obtained from the output
of the above DC–DC converter (VDC=3VDC) through a
multi-winding step-down transformer (turns ratio, 3:1) based
AC-link system as shown in Fig. 1. Thus, the DC-link voltage of
MAIN and auxiliary inverters can be controlled simultaneously
through a single close-loop voltage controller as shown in
Fig. 2. For trinary (3VDC:VDC) asymmetrical cascaded multilevel
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configuration, the reference DC-link voltage of the MAIN inverter
∗
(Vdc ) can be equal to the 75% (3/4 of VDC-T) of the total DC-link
voltage calculated for the stator voltage required. To control the
speed of the IM, a reference speed can be converted to the frequency
( f ) to obtain the corresponding AC voltage (V = VLL,rms) using a flux
controller up to the rated speed of operation [38].
The combination of the stator flux controller block and the relation
(1) can be termed as VDC/f controller as depicted in Fig. 2. To control
the DC-link voltage of the MAIN inverter (VDC) the reference DC-link
∗
voltage (VDC ) and the actual DC voltage (VDC) are compared and the
(1) The gain of the voltage controller is so selected that, the output
value of the controller (duty ratio) will be within the range 0 to
1. Thus the actual DC-link voltage of the MAIN inverter (as well as
the auxiliary inverter) follows the change of reference DC voltage
(or the reference speed) for the variable speed IM drive application.
In addition, a low frequency modulation technique was used to
control the fundamental frequency ( f ) of the produced voltage by
the asymmetrical MLI, considering a high power IM drive with
low switching losses. Therefore, the proposed modulation and
control techniques can control the voltage and frequency of the IM
simultaneously without losing the level of the inverter even at the
low speed operation.
The modulation index (Mi) of the proposed modulation and
control of the inverter for controlling the voltage magnitude (or the
average duty ratio of the DC–DC converter, di) can be derived as
 
V 
ref -MAIN
Mi = di = (2)
Vc
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Fig. 5 Simulation results of phase voltage of an asymmetrical nine-level inverter under variable voltage and frequency control of IM at a speed of
a 3000 RPM
b 1500 RPM
c 1000 RPM
d 800 RPM
e 500 RPM
f 100 RPM
where Vref_MAIN is the magnitude of the reference for the MAIN
inverter that is required to control its DC-link voltage and Vc is the
peak magnitude of the carrier signal for implementing the PWM
of the DC–DC converter as shown in Fig. 2.
For an asymmetrical cascaded MLI, as the power rating of the
MAIN inverter is several times higher than the auxiliary inverters.
Therefore, the switching frequency of the MAIN inverters can be
maintained at a lower value than the AUX inverters. The NLC
technique can be considered as a hybrid modulation technique
[39], that generates the switching pulses of fundamental frequency
for MAIN inverter and several times higher switching frequency
for the AUX inverter separately. In [40, 41], an another NLC
method is reported using the round based technique where the
nearest voltage levels can be generated by converting to the
desired output voltage reference. In this paper, the switching state
of whole inverter is also generated together.
However, in the proposed paper the author demonstrated a nearest
level modulation strategy (NLC) using comparison based algorithm
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[39] to realise a nine-level asymmetrical converter topology with a
single DC supply. In this paper, the output voltage step is
generated by synthesising the voltages of each bridge, i.e. MAIN
H-bridge and the auxiliary H-bridge where switching states are
separately generated for MAIN H-bridge and the auxiliary H-bridge.
Fig. 3a shows the block diagram of a generalised NLC technique
for one phase of the three-phase cascaded n-level inverter. For a
variable voltage and frequency operation of IM drive, the
frequency of the sinusoidal reference signal of main inverter
(Vref-MAIN) can be controlled keeping the peak magnitude constant
at unity value as shown in Fig 3a. This leads to the control the
frequency of the reference signal for the MAIN and AUX inverters
(Vref-MAIN, Vref-AUXi) simultaneously. The control of the above
MLI using NLC, the switching states of the MAIN inverter (S1)
and AUX inverter (Si) can be obtained by comparing the reference
signals with unity magnitude corresponding to MAIN inverter
(Vref-MAIN) and AUX inverter (Vref-AUXi) with a constant Ki (i = 1
for MAIN inverter and i = 2,3… for several AUX inverters) for a
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Fig. 6 Experimental results of phase voltage of an asymmetrical nine-level Inverter under variable voltage and frequency control of IM at a speed of
a 3000 RPM
b 1500 RPM
c 1000 RPM
d 800 RPM
e 500 RPM
f100 RPM

generalised n-level inverter. For any H-bridge modules, the value of in terms of their asymmetry factors (Ai) as
Ki depends on the number of inverter modules in a phase (or the
number of voltage levels) and the asymmetry factor Ai as
discussed in the following. 
L
N= Ai = A1 + A2 + · · · + AL (3)
For a DC-link voltage of magnitude 3VDC across the MAIN i=1
inverter, the DC-link voltage of the ith AUX inverter bridge
(VDCi ) can be determined as Ai VDC ( VDCi = Ai VDC ). For a
generalised asymmetrical cascaded MLI of trinary asymmetry with Therefore, the total number of voltage levels (n) in a phase is (2N + 1).
any number of H-bridge in each phase, the DC-link voltage ratio The value of the constant, Ki for the ith H-bridge inverter can be
between the successive H-bridge (the asymmetry factor of expressed as
successive H-bridge) can be assumed as 3 (Ai−1/Ai = 3).
Hence the asymmetrical cascaded inverter with two H-bridge, the Ai
asymmetry factor in the second H-bridge (auxiliary inverter) can be Ki = (4)
calculated as unity (A2 = 1), by assuming the asymmetry factor for 2N
first H-bridge as 3 (A1 = 3). Hence, the DC-link voltage of the
second H-bridge (VDC2) is VDC corresponding to the MAIN For an MLI with two H-bridges in cascaded manner, having DC-link
inverter voltage (VDC) of magnitude 3VDC. voltage ratio of 3:1 (trinary configuration) as shown in Fig. 2, the
The number of positive voltage levels (N ) of general asymmetrical value of N for A1 = 3 and A2 = 1 can be determined as
cascaded MLI with L number of H-bridge in a phase can be derived 4. Therefore, the values of constants K1 and K2 for implementing

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Fig. 7 Experimental results of three-phase asymmetrical nine-level Inverter current under load condition at a motor speed of 800 RPM (25.5 Hz)

the NLC can be obtained as 0.375 (K1 = A1/2N) and 0.125 (K2 = A2/2N),
respectively.
The reference signal for the MAIN inverter (Vref MAIN ) is
sinusoidal in nature with unity magnitude and the frequency is
equal to the inverter fundamental frequency as specified in the
following equation
Vref -MAIN = sin (ve t)
(S1 ) as
 
S1 = Vref -MAIN . K1 and (Vref -MAIN , −K1 ) (6)
On the other hand, the nature of the reference signal for the second
H-bridge in that phase or the first AUX inverter (Vref AUX1 ) is a
mixed of sinusoidal and alternating rectangular signal (switching
(5) states of MAIN inverter, S1) as given in the following equation

The reference Vref MAIN is compared with the constant K1 in the Vref -AUX1 = (Vref -MAIN − 2K1 S1 ) (7)
positive half cycle and −K1 in the negative half cycle as depicted
in Fig. 3b to generate the switching states of the MAIN inverter The reference signal Vref -AUX1 as given in (7) should compare with

Fig. 8 Simulation results during transient condition (at different modulation index) for
a DC-link voltage of the MAIN inverter (VDC)
b DC-link voltage of the AUX inverter (VDC)
c Inverter phase voltages

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Fig. 9 THD by the proposed modulation and control technique and the
conventional carrier based modulation (LS-PWM with fs = 3 kHz) and
control technique at various modulation index (Mi) or the reference
voltage with the achieved output voltage levels (L) of the inverter
constant K2 in the positive half cycle and with −K2 in the negative
half cycle as shown in Fig. 3b to obtain the switching states (S2 ) for
AUX-1 inverter as
 
S2 = Vref -MAIN . K2 and (Vref -MAIN , −K2 ) (8)
Similarly, the switching states (Si ) of the ith AUX inverter can be
expressed as
 
Si = Vref -AUX(i−1) . Ki and (Vref -AUX(i−1) , −Ki ) (9)
Fig. 3a shows the block diagram representation of the modulation
technique of a general asymmetrical cascaded MLI using NLC
technique. The switching states for the MAIN inverter bridges (S1),
is a rectangular signal as shown in Fig. 3b, with a frequency equal
to the fundamental frequency of the inverter which can be decoded
to obtain the gate pulses of the switches of the MAIN inverter
bridge. On the other hand, the switching states for the AUX inverter
(Si) are a high frequency rectangular pulse as shown in Fig. 3b. The
magnitude of reference signals for MAIN and AUX inverters
specified above does not change with the frequency at modulation
stage unlike in a conventional modulation and control of the inverter
for variable speed drives. However, to control the magnitude of
fundamental with the constant V/f operation of the IM, their DC-link
voltage is controlled though the DC–DC converter.
4 Simulation and experimental results
The detailed simulation of the proposed modulation and control
techniques of the nine-level asymmetrical cascaded inverter is
done in MATLAB/Simulink platform along with PSIM for the
modeling of open end winding IM. For the simulation as well as
experimental purposes, the input supply to the DC–DC converter
(Vs) is considered as 200 V and the carrier frequency for the DC–
DC converter is 12 kHz. The DC supply voltage (Vs) is adjusted
through the DC–DC converter to obtain the variable DC-link
voltages of magnitude 3VDC and VDC for MAIN and AUX
inverters to drive an IM of rating, 1HP (three-phase), 200 V, 50 Hz.
A laboratory prototype of nine-level asymmetrical MLI
experimental set up of 5 kW is designed and the proposed control
algorithm is tested for a three-phase 1HP, 200 V, 50 Hz open-end
winding IM drives. The detail simulation and experimental
parameters and the component specifications are given in Appendix.
The whole control algorithm is implemented in real time using
OPAL-RT platform with the same parameters as considered for
the simulation purposes. The simulation and experimental results
of the switching states for the MAIN and AUX inverter bridges
(MAIN and auxiliary signals) and the whole inverter phase voltage
are shown in Fig. 4. It has been observed that, the switching
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frequency for the MAIN inverter is equal to the fundamental
frequency, whereas, the switching frequency of the AUX inverter
is higher than the MAIN inverter.
Fig. 5 shows the simulation results of inverter phase voltage and its
harmonic spectrum for various inverter frequencies (or speed of the IM)
below and above the rated speed. From the harmonic spectrum, it is
observed that the percentage THD (%THD) for different fundamental
frequency (or speed of the IM), changes only marginally. It is also
observed that the number of voltage levels has remained same
irrespective of the reference magnitude of the voltage or the speed.
However, due to variable voltage and frequency controls, the position
of dominant harmonic components is shifted proportionally to the
value of the fundamental frequency of the inverter.
Fig. 6 shows the experimental results of phase voltage of the
nine-level inverter for different frequency (or speed of the IM)
below and above the rated speed similar to the simulation results
presented in Fig. 5. It is observed from Fig. 6, that the number of
phase voltage levels is always nine irrespective of the magnitude
of the reference voltage or speed variations. It is also observed
that, the voltage and the frequency of the open-end winding IM is
varied linearly up to the rated speed of operation (frequency) and
only the frequency is increased above the rated frequency.
For further verification of the performance of the three-phase nine
level inverter, the three-phase stator current at 800 RPM (frequency
is 25.5 Hz) is measured for two cycles by the Fluke 434, the
three-phase power quality analyser and the result is presented here
as shown in Fig. 7. It is observed from the figure that, the stator
currents present low harmonic distortion and are balanced.
The gain of the PI controller is so adjusted, that the actual DC-link
∗
voltage (VDC) equal to the DC-link command voltage (VDC ) and hence
the desired stator voltage can be achieved. The command voltage of
∗
the DC-DC converter (VDC ) proportional to the stator frequency ( f )
can be used for the closed-loop voltage control. Figs. 8a and b
show the simulation results of DC-link voltages of MAIN and AUX
inverters for different reference voltage (frequency) or speed of the
IM, respectively. It is clearly observed from Figs. 8a and b that, the
DC-link voltages of the MAIN and AUX inverters are properly
tracking the DC-link reference voltage (or the inverter desired AC
output voltage). Fig. 8c shows simulation results of the inverter
phase voltage using the proposed V/f control that depicts the
variation of voltage as well as frequency with the constant voltage
levels and acceptable dynamic behaviour.
To determine the key performance parameters of the MLI like the
number of output voltage levels, THDs and so on, and an exhaustive
simulation is carried out using the proposed control technique as well
as the classic control technique with PWM at a switching frequency
of 3 kHz for different reference voltages (or frequency). The results
corresponding to the proposed and conventional (or classic) control
methods are plotted with respect to the different modulation index
(Mi) in the range of 0.2–0.9 as depicted in Fig. 9. It is observed
that, by the proposed control technique, the levels of the inverter
output voltage (L) as well as the THD remained constant even at
the lower inverter frequency. This is due to the variations of
DC-link voltage with the variations of Mi (up to Mi = 1) keeping
the magnitude of the reference of the NLC constant.
On the other hand, in conventional control and modulation
techniques the output voltage levels and %THD depends on the
value of the modulation index. The number of voltage levels
always decreased with the decrease in the modulation index as
depicted in Fig. 9. Thus, by the conventional techniques, the %
THD of the inverter phase voltage also increases with the decrease
in Mi as observed in Fig. 9. This graph shows the variation of %
THD with modulation index for the proposed technique indicating
output voltage levels at each (Mi). It is observed that, the inverter
voltage levels (L) are remaining same at each modulation index
with nearly same %THD values, whereas the graph corresponding
to the conventional control technique shows that, the output
voltage levels reduces with the reduction of modulation index of
the PWM inverter (Mi) and the respective %THD values also
increased. However, the voltage levels of the inverter and the %
THD of voltage is always better, when their modulation index is
approaching to unity.
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5 Conclusion
A novel control scheme for any MLI is proposed, that maintained the
inverter voltage levels and the THDs constant irrespective of the
reference voltages. In the proposed control technique, the variation of
inverter voltage magnitude is implemented by controlling the DC-link
voltage of the MAIN inverter using a close-loop voltage control
technique. The frequency of the inverter voltage varied by the NLC
method in such a way that, the inverter voltage levels remained
constant at any reference voltage. The proposed control scheme has
been implemented in real-time using an OPAL-RT platform and
tested on a laboratory prototype of a nine-level cascaded inverter
(asymmetrical) experimental set-up for an IM (open end winding)
drive. The experiment is carried out at different stator voltage (or
stator frequency) below and above the rated speed and few
experimental results are presented. It is observed that, at different
speeds of operation, the number of inverter voltage levels are always
same and hence their THD also remains nearly constant. It is also
observed that, the control of the DC-link voltages perfectly track the
reference DC-link voltages for different inverter voltage (or frequency).
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7 Appendix
See Table 1.
Table 1 Components and their specification for experimental prototype
and simulation purposes
Components Ratings/
specifications
input DC supply voltage of the DC–DC converter, Vs 200 V
maximum DC-link voltage of MAIN inverter 190 V
(VDC = 3VDC)
maximum DC-link voltage of AUX inverter (VDC) 63.3 V
multi-winding step-down transformer rating 1 kVA, 200/66 V
IGBT for DC–DC converters and inverters (MAIN K75T60 (600 V, 75 A)
inverters and inverters of AC-link system)
rating of the capacitor in DC–DC Converter 470 µF, 400 V
rating of the Inductor in DC–DC Converter 150 mH
P-MOSFET for AUX inverters IRFP460 (500 V,
20 A)
rating of the capacitor in auxiliary inverters 450 µF, 400 V
open end winding IM 1 HP, 200 V, 50 Hz
switching frequency of IGBT for the DC–DC 12 kHz
converter
switching frequency of IGBT for the AC-link inverter 3 kHz
proportional gain of the voltage controller, Kp 10
integral gain of the voltage controller, Ki 0.1
79